DE3475856D1 - Method for aligning a connecting line above an electrical contact hole of an integrated circuit - Google Patents

Method for aligning a connecting line above an electrical contact hole of an integrated circuit

Info

Publication number
DE3475856D1
DE3475856D1 DE8484401636T DE3475856T DE3475856D1 DE 3475856 D1 DE3475856 D1 DE 3475856D1 DE 8484401636 T DE8484401636 T DE 8484401636T DE 3475856 T DE3475856 T DE 3475856T DE 3475856 D1 DE3475856 D1 DE 3475856D1
Authority
DE
Germany
Prior art keywords
aligning
integrated circuit
electrical contact
contact hole
connecting line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484401636T
Other languages
German (de)
English (en)
Inventor
Pierre Jeuch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR8313282A external-priority patent/FR2550660B2/fr
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Application granted granted Critical
Publication of DE3475856D1 publication Critical patent/DE3475856D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
DE8484401636T 1983-08-12 1984-08-06 Method for aligning a connecting line above an electrical contact hole of an integrated circuit Expired DE3475856D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8313282A FR2550660B2 (fr) 1982-04-14 1983-08-12 Perfectionnement au procede de positionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre

Publications (1)

Publication Number Publication Date
DE3475856D1 true DE3475856D1 (en) 1989-02-02

Family

ID=9291605

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401636T Expired DE3475856D1 (en) 1983-08-12 1984-08-06 Method for aligning a connecting line above an electrical contact hole of an integrated circuit

Country Status (4)

Country Link
US (1) US4541892A (https=)
EP (1) EP0139549B1 (https=)
JP (1) JPS6055642A (https=)
DE (1) DE3475856D1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575402A (en) * 1985-02-13 1986-03-11 Hewlett-Packard Company Method for fabricating conductors in integrated circuits
JP2544100B2 (ja) * 1985-05-20 1996-10-16 ヤマハ株式会社 金属パタ−ン形成法
JPH0680739B2 (ja) * 1987-05-19 1994-10-12 日本電気株式会社 半導体装置の製造方法
JPS63292649A (ja) * 1987-05-25 1988-11-29 Nec Corp 半導体装置の製造方法
JPS63299251A (ja) * 1987-05-29 1988-12-06 Toshiba Corp 半導体装置の製造方法
US5081516A (en) * 1987-12-02 1992-01-14 Advanced Micro Devices, Inc. Self-aligned, planarized contacts for semiconductor devices
US4851368A (en) * 1987-12-04 1989-07-25 Cornell Research Foundation, Inc. Method of making travelling wave semi-conductor laser
JPH01214046A (ja) * 1988-02-22 1989-08-28 Nec Corp 半導体装置の製造方法
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
DE4231312C2 (de) * 1992-09-18 1996-10-02 Siemens Ag Antireflexschicht und Verfahren zur lithografischen Strukturierung einer Schicht
US5324689A (en) * 1993-07-28 1994-06-28 Taiwan Semiconductor Manufacturing Company Critical dimension control with a planarized underlayer
KR100366910B1 (ko) * 1994-04-05 2003-03-04 소니 가부시끼 가이샤 반도체장치의제조방법
JPH1140664A (ja) * 1997-07-17 1999-02-12 Mitsubishi Electric Corp 半導体装置の製造方法
US6693038B1 (en) * 1999-02-05 2004-02-17 Taiwan Semiconductor Manufacturing Company Method for forming electrical contacts through multi-level dielectric layers by high density plasma etching

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5222071A (en) * 1975-08-13 1977-02-19 Hitachi Ltd Method of selective etching of film of polyamide resin
JPS588579B2 (ja) * 1975-08-20 1983-02-16 松下電器産業株式会社 ハンドウタイソウチノセイゾウホウホウ
FR2428915A1 (fr) * 1978-06-14 1980-01-11 Fujitsu Ltd Procede de fabrication d'un dispositif a semi-conducteurs
US4244799A (en) * 1978-09-11 1981-01-13 Bell Telephone Laboratories, Incorporated Fabrication of integrated circuits utilizing thick high-resolution patterns
JPS5593225A (en) * 1979-01-10 1980-07-15 Hitachi Ltd Forming method of minute pattern
EP0049400B1 (en) * 1980-09-22 1984-07-11 Kabushiki Kaisha Toshiba Method of smoothing an insulating layer formed on a semiconductor body
US4492717A (en) * 1981-07-27 1985-01-08 International Business Machines Corporation Method for forming a planarized integrated circuit
JPS59163826A (ja) * 1983-03-08 1984-09-14 Toshiba Corp ドライエツチング方法
US4478679A (en) * 1983-11-30 1984-10-23 Storage Technology Partners Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors

Also Published As

Publication number Publication date
EP0139549A1 (fr) 1985-05-02
US4541892A (en) 1985-09-17
EP0139549B1 (fr) 1988-12-28
JPS6055642A (ja) 1985-03-30
JPH0418457B2 (https=) 1992-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee