DE3467661D1 - Semiconductor device, in particular a transistor including a protection means against overvoltage - Google Patents
Semiconductor device, in particular a transistor including a protection means against overvoltageInfo
- Publication number
- DE3467661D1 DE3467661D1 DE8484201177T DE3467661T DE3467661D1 DE 3467661 D1 DE3467661 D1 DE 3467661D1 DE 8484201177 T DE8484201177 T DE 8484201177T DE 3467661 T DE3467661 T DE 3467661T DE 3467661 D1 DE3467661 D1 DE 3467661D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor device
- transistor including
- protection means
- means against
- against overvoltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
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- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
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Landscapes
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Die Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Fuses (AREA)
- Electrodes Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Bipolar Transistors (AREA)
- Noodles (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8313372A FR2550886B1 (fr) | 1983-08-17 | 1983-08-17 | Procede de realisation de transistors de puissance incluant des moyens de protection contre les surcharges et dispositifs ainsi obtenus |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3467661D1 true DE3467661D1 (en) | 1987-12-23 |
Family
ID=9291651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484201177T Expired DE3467661D1 (en) | 1983-08-17 | 1984-08-15 | Semiconductor device, in particular a transistor including a protection means against overvoltage |
Country Status (5)
Country | Link |
---|---|
US (1) | US4635091A (de) |
EP (1) | EP0135230B1 (de) |
JP (1) | JPS6074541A (de) |
DE (1) | DE3467661D1 (de) |
FR (1) | FR2550886B1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4922366A (en) * | 1988-05-12 | 1990-05-01 | Transnational Energy Systems, Inc., Dba Tesco | Meltable conductor to be used in series with voltage suppressors |
US5260604A (en) * | 1988-09-27 | 1993-11-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with improved immunity to contact and conductor defects |
US5047833A (en) * | 1990-10-17 | 1991-09-10 | International Rectifier Corporation | Solderable front metal contact for MOS devices |
JP2944840B2 (ja) * | 1993-03-12 | 1999-09-06 | 株式会社日立製作所 | 電力用半導体装置 |
US5477409A (en) * | 1993-11-24 | 1995-12-19 | Vlsi Technology Inc. | Fusion heat sink for integrated circuit |
US5424901A (en) * | 1994-01-26 | 1995-06-13 | Illinois Tool Works Inc. | Sidactor fail-safe device |
US5488535A (en) * | 1994-01-26 | 1996-01-30 | Illinois Tool Works Inc. | Arc suppressor for sidactors |
US6337507B1 (en) * | 1995-09-29 | 2002-01-08 | Intel Corporation | Silicide agglomeration fuse device with notches to enhance programmability |
US5708291A (en) | 1995-09-29 | 1998-01-13 | Intel Corporation | Silicide agglomeration fuse device |
JP3352360B2 (ja) * | 1996-07-19 | 2002-12-03 | シャープ株式会社 | 電力制御素子 |
US6288437B1 (en) * | 1999-02-26 | 2001-09-11 | Micron Technology, Inc. | Antifuse structures methods and applications |
DE19936112A1 (de) | 1999-07-31 | 2001-02-01 | Mannesmann Vdo Ag | Halbleiterschalter |
US6166421A (en) * | 1999-08-18 | 2000-12-26 | National Semiconductor Corporation | Polysilicon fuse that provides an open current path when programmed without exposing the fuse to the environment |
DE10334433B4 (de) * | 2003-07-28 | 2009-10-22 | Infineon Technologies Ag | Vorrichtung zur Unterbrechung des Stromflusses zu einem oder von einem Halbleiterkörper eines Halbleiterbauelements |
DE102006009236A1 (de) * | 2006-02-28 | 2007-09-06 | Infineon Technologies Ag | Vorrichtung und Verfahren zur temperaturunterbrechenden Absicherung eines elektrischen Bauelements |
KR100976650B1 (ko) * | 2007-12-07 | 2010-08-18 | 주식회사 케이이씨 | 다이 본딩 구조 및 그 방법 |
US8319596B2 (en) * | 2009-05-20 | 2012-11-27 | GM Global Technology Operations LLC | Active material circuit protector |
US8816390B2 (en) | 2012-01-30 | 2014-08-26 | Infineon Technologies Ag | System and method for an electronic package with a fail-open mechanism |
US9082737B2 (en) | 2012-11-15 | 2015-07-14 | Infineon Technologies Ag | System and method for an electronic package with a fail-open mechanism |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3461462A (en) * | 1965-12-02 | 1969-08-12 | United Aircraft Corp | Method for bonding silicon semiconductor devices |
FR2230078B1 (de) * | 1973-05-18 | 1977-07-29 | Radiotechnique Compelec | |
US3925808A (en) * | 1974-08-08 | 1975-12-09 | Westinghouse Electric Corp | Silicon semiconductor device with stress-free electrodes |
DE2649773A1 (de) * | 1976-10-29 | 1978-05-11 | Bosch Gmbh Robert | Halbleiteranordnung |
US4392010A (en) * | 1979-01-16 | 1983-07-05 | Solarex Corporation | Photovoltaic cells having contacts and method of applying same |
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1983
- 1983-08-17 FR FR8313372A patent/FR2550886B1/fr not_active Expired
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1984
- 1984-08-10 US US06/639,642 patent/US4635091A/en not_active Expired - Fee Related
- 1984-08-15 EP EP84201177A patent/EP0135230B1/de not_active Expired
- 1984-08-15 DE DE8484201177T patent/DE3467661D1/de not_active Expired
- 1984-08-17 JP JP59170509A patent/JPS6074541A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
EP0135230B1 (de) | 1987-11-19 |
FR2550886B1 (fr) | 1986-10-24 |
JPS6074541A (ja) | 1985-04-26 |
US4635091A (en) | 1987-01-06 |
FR2550886A1 (fr) | 1985-02-22 |
JPH0160950B2 (de) | 1989-12-26 |
EP0135230A1 (de) | 1985-03-27 |
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