DE3424078C2 - - Google Patents

Info

Publication number
DE3424078C2
DE3424078C2 DE3424078A DE3424078A DE3424078C2 DE 3424078 C2 DE3424078 C2 DE 3424078C2 DE 3424078 A DE3424078 A DE 3424078A DE 3424078 A DE3424078 A DE 3424078A DE 3424078 C2 DE3424078 C2 DE 3424078C2
Authority
DE
Germany
Prior art keywords
carry
decimal
digit
sum
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3424078A
Other languages
German (de)
English (en)
Other versions
DE3424078A1 (de
Inventor
Toru Ohtsuki
Yoshio Oshima
Sako Ishikawa
Hideaki Yabe
Masaharu Hadano Jp Fukuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3424078A1 publication Critical patent/DE3424078A1/de
Application granted granted Critical
Publication of DE3424078C2 publication Critical patent/DE3424078C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE19843424078 1983-07-01 1984-06-29 Dezimalmultiplikations-einrichtung Granted DE3424078A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58119556A JPS6011927A (ja) 1983-07-01 1983-07-01 １０進乗算装置

Publications (2)

Publication Number Publication Date
DE3424078A1 DE3424078A1 (de) 1985-01-10
DE3424078C2 true DE3424078C2 (US20100056889A1-20100304-C00004.png) 1989-06-29

Family

ID=14764235

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19843424078 Granted DE3424078A1 (de) 1983-07-01 1984-06-29 Dezimalmultiplikations-einrichtung

Country Status (3)

Country Link
US (1) US4677583A (US20100056889A1-20100304-C00004.png)
JP (1) JPS6011927A (US20100056889A1-20100304-C00004.png)
DE (1) DE3424078A1 (US20100056889A1-20100304-C00004.png)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140429A (ja) * 1983-12-28 1985-07-25 Hitachi Ltd １０進乗算装置
US4947364A (en) * 1985-10-23 1990-08-07 Hewlett-Packard Company Method in a computing system for performing a multiplication
DE3608914A1 (de) * 1986-03-18 1987-10-01 Thomson Brandt Gmbh Verfahren zur korrektur
JPH0769784B2 (ja) * 1987-09-29 1995-07-31 日本電気株式会社 １０進加算装置
US7546328B2 (en) * 2004-08-31 2009-06-09 Wisconsin Alumni Research Foundation Decimal floating-point adder
US7743084B2 (en) * 2004-09-23 2010-06-22 Wisconsin Alumni Research Foundation Processing unit having multioperand decimal addition
US7519647B2 (en) 2005-02-09 2009-04-14 International Business Machines Corporation System and method for providing a decimal multiply algorithm using a double adder
US7475104B2 (en) 2005-02-09 2009-01-06 International Business Machines Corporation System and method for providing a double adder for decimal floating point operations
US8577952B2 (en) * 2008-12-08 2013-11-05 International Business Machines Corporation Combined binary/decimal fixed-point multiplier and method
US8566385B2 (en) * 2009-12-02 2013-10-22 International Business Machines Corporation Decimal floating point multiplier and design structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1196298A (en) * 1966-10-04 1970-06-24 Zentralen Inst Istchislitelna Electric Circuit for Performing the Operation 'Multiplication', Especially in Electronic Calculators
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array
DE2952229A1 (de) * 1979-01-03 1980-07-17 Honeywell Inf Systems Verfahren und einrichtung zur multiplikation von dezimalzahlen in einer dv-anlage
US4484300A (en) * 1980-12-24 1984-11-20 Honeywell Information Systems Inc. Data processor having units carry and tens carry apparatus supporting a decimal multiply operation
JPS58129653A (ja) * 1982-01-29 1983-08-02 Hitachi Ltd 乗算方式

Also Published As

Publication number Publication date
JPH0234054B2 (US20100056889A1-20100304-C00004.png) 1990-08-01
US4677583A (en) 1987-06-30
JPS6011927A (ja) 1985-01-22
DE3424078A1 (de) 1985-01-10

Similar Documents

Publication Publication Date Title
DE1956209C3 (de) Multipliziervorrichtung
DE2712224A1 (de) Datenverarbeitungsanlage
DE3424078C2 (US20100056889A1-20100304-C00004.png)
DE2623986A1 (de) Parallelrechenwerk
DE3229452A1 (de) Arithmetiklogikeinheit
DE3303269C2 (US20100056889A1-20100304-C00004.png)
DE3447634C2 (US20100056889A1-20100304-C00004.png)
EP0265555B1 (de) Verfahren und Schaltungsanordnung zur Addition von Gleitkommazahlen
DE3434777C2 (US20100056889A1-20100304-C00004.png)
DE3784684T2 (de) Fehlerkorrekturdecoder fuer schnelle behandlung von pufferueberlaeufen.
DE2743575A1 (de) Verfahren und einrichtung zur multiplikation einer ersten zahl mit einer zweiten zahl
DE3440680A1 (de) Verfahren und vorrichtung zur dezimaldivision
DE2727051C3 (de) Einrichtung zur binären Multiplikation einer ersten Zahl als Multiplikand mit einer den Multiplikator ergebenden Summe aus einer zweiten und dritten Zahl im Binärcode
DE1449564C3 (de) Recheneinrichtung zur Subtraktion mehrerer Operanden oder zu deren Addition durch Verwendung von Komplementärwerten eines der Operanden
DE3302013C2 (US20100056889A1-20100304-C00004.png)
DE2913729C2 (de) Schaltungsanordnung zur bitparallelen Binäraddition oder zum Shiften von Binärzahlen
DE2046685A1 (de) Einrichtung zum Konvertieren einer Dezimalzahl in eine Binarzahl
DE2855946A1 (de) Pla-addierschaltung
DE1549105C3 (de) Codeprüfanordnung für die Korrektur fehlerhaft übertragener Zeichen
DE1499227B2 (de) Schaltungsanordnung für arithmetische und logische Grundoperationen
DE1549461C3 (US20100056889A1-20100304-C00004.png)
DE1094020B (de) Periodisch arbeitende numerische Rechenmaschine
DE1549485B2 (de) Anordnung zur division binaerer operanden ohne rueckstellung des restes
DE2737483C3 (de) Korrektur-Schaltungsanordnung für Additions- oder Substraktionsoperationen mit nicht-hexadezimalen Operanden in hexadezimalen Rechenwerken
DE4408789A1 (de) Ein rechnergestütztes Verfahren zum Konstruieren eines Addierers mit vorgreifender Übertragsbildung

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee