DE3410196C2 - - Google Patents
Info
- Publication number
- DE3410196C2 DE3410196C2 DE19843410196 DE3410196A DE3410196C2 DE 3410196 C2 DE3410196 C2 DE 3410196C2 DE 19843410196 DE19843410196 DE 19843410196 DE 3410196 A DE3410196 A DE 3410196A DE 3410196 C2 DE3410196 C2 DE 3410196C2
- Authority
- DE
- Germany
- Prior art keywords
- island
- webs
- frame
- conductor
- conductor strip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004020 conductor Substances 0.000 claims description 28
- 241001601011 Stegastes Species 0.000 claims 3
- 238000000034 method Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 241000607479 Yersinia pestis Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 206010022000 influenza Diseases 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Packaging Frangible Articles (AREA)
- Elimination Of Static Electricity (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19843410196 DE3410196A1 (de) | 1984-03-20 | 1984-03-20 | Leiterband fuer die montage von integrierten schaltkreisen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19843410196 DE3410196A1 (de) | 1984-03-20 | 1984-03-20 | Leiterband fuer die montage von integrierten schaltkreisen |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3410196A1 DE3410196A1 (de) | 1985-09-26 |
| DE3410196C2 true DE3410196C2 (enrdf_load_stackoverflow) | 1993-03-11 |
Family
ID=6231068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19843410196 Granted DE3410196A1 (de) | 1984-03-20 | 1984-03-20 | Leiterband fuer die montage von integrierten schaltkreisen |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE3410196A1 (enrdf_load_stackoverflow) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3674292D1 (de) * | 1985-07-23 | 1990-10-25 | Fairchild Semiconductor | Verpackungsanordnung fuer halbleiterchip und verfahren zum erleichtern deren pruefung und montage auf ein substrat. |
| CA1278618C (en) * | 1987-07-20 | 1991-01-02 | George Erdos | Plastic encapsulated integrated circuit package with electrostatic shield |
| US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1550834A (en) * | 1975-07-24 | 1979-08-22 | Telcon Metals Ltd | Semiconductor devices |
| US4177480A (en) * | 1975-10-02 | 1979-12-04 | Licentia Patent-Verwaltungs-G.M.B.H. | Integrated circuit arrangement with means for avoiding undesirable capacitive coupling between leads |
| GB2091035B (en) * | 1981-01-12 | 1985-01-09 | Avx Corp | Integrated circuit device and sub-assembly |
| EP0086724A3 (en) * | 1982-02-16 | 1985-04-24 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Integrated circuit lead frame with improved power dissipation |
-
1984
- 1984-03-20 DE DE19843410196 patent/DE3410196A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE3410196A1 (de) | 1985-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8110 | Request for examination paragraph 44 | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |