DE3381230D1 - Decodierschaltung. - Google Patents

Decodierschaltung.

Info

Publication number
DE3381230D1
DE3381230D1 DE8383305879T DE3381230T DE3381230D1 DE 3381230 D1 DE3381230 D1 DE 3381230D1 DE 8383305879 T DE8383305879 T DE 8383305879T DE 3381230 T DE3381230 T DE 3381230T DE 3381230 D1 DE3381230 D1 DE 3381230D1
Authority
DE
Germany
Prior art keywords
decoder circuit
decoder
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383305879T
Other languages
English (en)
Inventor
Teruo Seki
Takahiko Yamauchi
Keizo Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3381230D1 publication Critical patent/DE3381230D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
DE8383305879T 1982-09-29 1983-09-29 Decodierschaltung. Expired - Fee Related DE3381230D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57168273A JPS5958688A (ja) 1982-09-29 1982-09-29 デコ−ダ回路

Publications (1)

Publication Number Publication Date
DE3381230D1 true DE3381230D1 (de) 1990-03-29

Family

ID=15864957

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383305879T Expired - Fee Related DE3381230D1 (de) 1982-09-29 1983-09-29 Decodierschaltung.

Country Status (4)

Country Link
US (1) US4571510A (de)
EP (1) EP0107395B1 (de)
JP (1) JPS5958688A (de)
DE (1) DE3381230D1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60235525A (ja) * 1984-05-09 1985-11-22 Hitachi Ltd 半導体集積回路
JPS60239991A (ja) * 1984-05-14 1985-11-28 Mitsubishi Electric Corp デコ−ダ回路
JPS6154098A (ja) * 1984-08-23 1986-03-18 Fujitsu Ltd パルス発生回路
JPS6366789A (ja) * 1986-09-09 1988-03-25 Mitsubishi Electric Corp Ｃｍｏｓ行デコ−ダ回路
KR960006373B1 (ko) * 1992-10-31 1996-05-15 삼성전자주식회사 반도체 메모리 장치의 워드라인 구동회로
US5399919A (en) * 1993-02-25 1995-03-21 Texas Instruments Incorporated Apparatus for detecting switch actuation
JP2768298B2 (ja) * 1995-03-30 1998-06-25 日本電気株式会社 論理回路
US6316960B2 (en) * 1999-04-06 2001-11-13 Intel Corporation Domino logic circuit and method
US6529045B2 (en) 1999-09-28 2003-03-04 Intel Corporation NMOS precharge domino logic
US6275071B1 (en) 1999-12-29 2001-08-14 Intel Corporation Domino logic circuit and method
US6492837B1 (en) 2000-03-17 2002-12-10 Intel Corporation Domino logic with output predischarge
US6486706B2 (en) 2000-12-06 2002-11-26 Intel Corporation Domino logic with low-threshold NMOS pull-up
US6404234B1 (en) 2001-05-09 2002-06-11 Intel Corporation Variable virtual ground domino logic with leakage control
US7652947B2 (en) * 2008-02-28 2010-01-26 International Business Machines Corporation Back-gate decode personalization

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651342A (en) * 1971-03-15 1972-03-21 Rca Corp Apparatus for increasing the speed of series connected transistors
GB1381963A (en) * 1971-05-07 1975-01-29 Tokyo Shibaura Electric Co Counter using insulated gate field effect transistors
US4024512A (en) * 1975-06-16 1977-05-17 Fairchild Camera And Instrument Corporation Line-addressable random-access memory
JPS5493335A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Decoder circuit
JPS5522238A (en) * 1978-07-31 1980-02-16 Fujitsu Ltd Decoder circuit
US4258272A (en) * 1979-03-19 1981-03-24 National Semiconductor Corporation TTL to CMOS input buffer circuit
US4337525A (en) * 1979-04-17 1982-06-29 Nippon Electric Co., Ltd. Asynchronous circuit responsive to changes in logic level
JPS5641579A (en) * 1979-09-10 1981-04-18 Toshiba Corp Address selector
GB2070372B (en) * 1980-01-31 1983-09-28 Tokyo Shibaura Electric Co Semiconductor memory device
JPS6042554B2 (ja) * 1980-12-24 1985-09-24 富士通株式会社 Ｃｍｏｓメモリデコ−ダ回路
US4404474A (en) * 1981-02-06 1983-09-13 Rca Corporation Active load pulse generating circuit
US4398102A (en) * 1981-02-06 1983-08-09 Rca Corporation Gated parallel decoder

Also Published As

Publication number Publication date
EP0107395A2 (de) 1984-05-02
EP0107395B1 (de) 1990-02-21
US4571510A (en) 1986-02-18
EP0107395A3 (en) 1986-07-02
JPS5958688A (ja) 1984-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee