DE3378703D1 - Voltage balancing circuit for memory systems - Google Patents

Voltage balancing circuit for memory systems

Info

Publication number
DE3378703D1
DE3378703D1 DE8383102806T DE3378703T DE3378703D1 DE 3378703 D1 DE3378703 D1 DE 3378703D1 DE 8383102806 T DE8383102806 T DE 8383102806T DE 3378703 T DE3378703 T DE 3378703T DE 3378703 D1 DE3378703 D1 DE 3378703D1
Authority
DE
Germany
Prior art keywords
memory systems
balancing circuit
voltage balancing
voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383102806T
Other languages
German (de)
English (en)
Inventor
Charles Joseph Masenas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3378703D1 publication Critical patent/DE3378703D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
DE8383102806T 1982-04-19 1983-03-22 Voltage balancing circuit for memory systems Expired DE3378703D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/369,970 US4555776A (en) 1982-04-19 1982-04-19 Voltage balancing circuit for memory systems

Publications (1)

Publication Number Publication Date
DE3378703D1 true DE3378703D1 (en) 1989-01-19

Family

ID=23457700

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383102806T Expired DE3378703D1 (en) 1982-04-19 1983-03-22 Voltage balancing circuit for memory systems

Country Status (5)

Country Link
US (1) US4555776A (enExample)
EP (1) EP0092062B1 (enExample)
JP (1) JPS58188934A (enExample)
DE (1) DE3378703D1 (enExample)
PH (1) PH20134A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093654A (en) * 1989-05-17 1992-03-03 Eldec Corporation Thin-film electroluminescent display power supply system for providing regulated write voltages
US5297089A (en) * 1992-02-27 1994-03-22 International Business Machines Corporation Balanced bit line pull up circuitry for random access memories

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786442A (en) * 1972-02-24 1974-01-15 Cogar Corp Rapid recovery circuit for capacitively loaded bit lines
US3949385A (en) * 1974-12-23 1976-04-06 Ibm Corporation D.C. Stable semiconductor memory cell
US3936810A (en) * 1975-01-20 1976-02-03 Semi, Inc. Sense line balancing circuit
FR2304991A1 (fr) * 1975-03-15 1976-10-15 Ibm Agencement de circuits pour memoire semi-conductrice et son procede de fonctionnement
JPS538528A (en) * 1976-07-12 1978-01-26 Nec Corp Memory circuit
DE2738678C3 (de) * 1977-08-27 1982-03-04 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte Speicherzelle
US4272834A (en) * 1978-10-06 1981-06-09 Hitachi, Ltd. Data line potential setting circuit and MIS memory circuit using the same
DE2855866C3 (de) * 1978-12-22 1981-10-29 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers
US4302823A (en) * 1979-12-27 1981-11-24 International Business Machines Corp. Differential charge sensing system
US4404662A (en) * 1981-07-06 1983-09-13 International Business Machines Corporation Method and circuit for accessing an integrated semiconductor memory

Also Published As

Publication number Publication date
JPH0378714B2 (enExample) 1991-12-16
JPS58188934A (ja) 1983-11-04
EP0092062B1 (en) 1988-12-14
US4555776A (en) 1985-11-26
EP0092062A2 (en) 1983-10-26
PH20134A (en) 1986-10-02
EP0092062A3 (en) 1986-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee