DE3366431D1 - Emitter coupled logic circuit - Google Patents

Emitter coupled logic circuit

Info

Publication number
DE3366431D1
DE3366431D1 DE8383303428T DE3366431T DE3366431D1 DE 3366431 D1 DE3366431 D1 DE 3366431D1 DE 8383303428 T DE8383303428 T DE 8383303428T DE 3366431 T DE3366431 T DE 3366431T DE 3366431 D1 DE3366431 D1 DE 3366431D1
Authority
DE
Germany
Prior art keywords
logic circuit
emitter coupled
coupled logic
emitter
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383303428T
Other languages
English (en)
Inventor
Hirofumi Takeda
Hirokazu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3366431D1 publication Critical patent/DE3366431D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE8383303428T 1982-06-29 1983-06-14 Emitter coupled logic circuit Expired DE3366431D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57110619A JPS592435A (ja) 1982-06-29 1982-06-29 Ｅｃｌ回路

Publications (1)

Publication Number Publication Date
DE3366431D1 true DE3366431D1 (en) 1986-10-30

Family

ID=14540387

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383303428T Expired DE3366431D1 (en) 1982-06-29 1983-06-14 Emitter coupled logic circuit

Country Status (5)

Country Link
US (1) US4551639A (de)
EP (1) EP0098074B1 (de)
JP (1) JPS592435A (de)
DE (1) DE3366431D1 (de)
IE (1) IE54541B1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60144022A (ja) * 1983-12-30 1985-07-30 Hitachi Ltd 差動形論理回路
EP0270296A3 (de) * 1986-12-01 1990-02-07 Fujitsu Limited Halbleiter-Logikschaltung
US4871931A (en) * 1987-10-30 1989-10-03 Gazelle Microcircuits, Inc. Logic circuit resistant to errors due to supply fluctuations
US5001361A (en) * 1988-05-13 1991-03-19 Fujitsu Limited Master-slave flip-flop circuit
DE3883389T2 (de) * 1988-10-28 1994-03-17 Ibm Zweistufige Adressendekodierschaltung für Halbleiterspeicher.
DE58906599D1 (de) * 1989-09-11 1994-02-10 Siemens Ag Kippschaltung mit Schalthysterese.
US5079452A (en) * 1990-06-29 1992-01-07 Digital Equipment Corporation High speed ECL latch with clock enable
DE69124176T2 (de) * 1990-08-29 1997-07-10 Motorola Inc Logischer BICMOS Schaltkreis mit einem CML-Ausgang
US5258661A (en) * 1992-04-20 1993-11-02 International Business Machines Corporation High noise tolerance receiver
US5751169A (en) * 1996-05-02 1998-05-12 Motorola, Inc. Emitter coupled logic (ECL) gate which generates intermediate signals of four different voltages
US6847233B1 (en) 2001-07-12 2005-01-25 Mediatek Inc. Emitter coupled logic circuit with a data reload function

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3321639A (en) * 1962-12-03 1967-05-23 Gen Electric Direct coupled, current mode logic
DE1941264C3 (de) * 1969-08-13 1975-07-17 Siemens Ag, 1000 Berlin Und 8000 Muenchen Asynchrone RS-Kippstufe in ECL-Technik
US3906212A (en) * 1971-08-18 1975-09-16 Siemens Ag Series-coupled emitter coupled logic (ECL) circuit having a plurality of independently controllable current paths in a lower plane
JPS522161A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Logic circuit
GB1592246A (en) * 1976-09-23 1981-07-01 Isaac T P Sound projection system
JPS54128656A (en) * 1978-03-30 1979-10-05 Nec Corp Flip flop circuit of current selection type
US4347446A (en) * 1979-12-10 1982-08-31 Amdahl Corporation Emitter coupled logic circuit with active pull-down
JPS56107641A (en) * 1980-01-31 1981-08-26 Nec Corp Semiconductor circuit equipment

Also Published As

Publication number Publication date
EP0098074B1 (de) 1986-09-24
IE54541B1 (en) 1989-11-08
EP0098074A1 (de) 1984-01-11
JPS592435A (ja) 1984-01-09
US4551639A (en) 1985-11-05
IE831528L (en) 1983-12-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee