DE3340956C2 - - Google Patents

Info

Publication number
DE3340956C2
DE3340956C2 DE3340956A DE3340956A DE3340956C2 DE 3340956 C2 DE3340956 C2 DE 3340956C2 DE 3340956 A DE3340956 A DE 3340956A DE 3340956 A DE3340956 A DE 3340956A DE 3340956 C2 DE3340956 C2 DE 3340956C2
Authority
DE
Germany
Prior art keywords
address
per
memory
access
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3340956A
Other languages
German (de)
English (en)
Other versions
DE3340956A1 (de
Inventor
Kiyoshi Yata
Hideo Hadano Jp Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3340956A1 publication Critical patent/DE3340956A1/de
Application granted granted Critical
Publication of DE3340956C2 publication Critical patent/DE3340956C2/de
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Prevention of errors by analysis, debugging or testing of software
    • G06F11/362Debugging of software
    • G06F11/3636Debugging of software by tracing the execution of the program
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
DE19833340956 1982-11-12 1983-11-11 Verfahren und vorrichtung zur erfassung von speicherzugriffen Granted DE3340956A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57197495A JPS5987566A (ja) 1982-11-12 1982-11-12 メモリアクセス検出方式

Publications (2)

Publication Number Publication Date
DE3340956A1 DE3340956A1 (de) 1984-05-24
DE3340956C2 true DE3340956C2 (https=) 1987-11-26

Family

ID=16375417

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833340956 Granted DE3340956A1 (de) 1982-11-12 1983-11-11 Verfahren und vorrichtung zur erfassung von speicherzugriffen

Country Status (4)

Country Link
US (1) US4641277A (https=)
JP (1) JPS5987566A (https=)
DE (1) DE3340956A1 (https=)
GB (1) GB2132797B (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0652511B2 (ja) * 1984-12-14 1994-07-06 株式会社日立製作所 情報処理装置のアドレス変換方式
US5233700A (en) * 1987-03-03 1993-08-03 Nec Corporation Address translation device with an address translation buffer loaded with presence bits
JP2580587B2 (ja) * 1987-03-03 1997-02-12 日本電気株式会社 アドレス変換バッファ
FR2617997A1 (fr) * 1987-07-07 1989-01-13 Mitsubishi Electric Corp Micro-ordinateur a memoire programmable, pour le controle du nombre des temps d'ecriture dans la memoire
US5265227A (en) * 1989-11-14 1993-11-23 Intel Corporation Parallel protection checking in an address translation look-aside buffer
DE10340861A1 (de) * 2003-09-04 2005-04-07 Infineon Technologies Ag Prozessorschaltung und Verfahren zum Zuordnen eines Logikchips zu einem Speicherchip
US7685381B2 (en) * 2007-03-01 2010-03-23 International Business Machines Corporation Employing a data structure of readily accessible units of memory to facilitate memory access
US7899663B2 (en) 2007-03-30 2011-03-01 International Business Machines Corporation Providing memory consistency in an emulated processing environment
US8090933B2 (en) * 2008-02-12 2012-01-03 International Business Machines Corporation Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1410631A (en) * 1972-01-26 1975-10-22 Plessey Co Ltd Data processing system interrupt arrangements
US3815101A (en) * 1972-11-08 1974-06-04 Sperry Rand Corp Processor state and storage limits register auto-switch
US4048671A (en) * 1976-06-30 1977-09-13 Ibm Corporation Address match for data processing system with virtual addressing
DE2837241C2 (de) * 1978-08-25 1982-05-06 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum Sichern von Daten gegen unberechtigten Zugriff
US4430705A (en) * 1980-05-23 1984-02-07 International Business Machines Corp. Authorization mechanism for establishing addressability to information in another address space

Also Published As

Publication number Publication date
JPS5987566A (ja) 1984-05-21
DE3340956A1 (de) 1984-05-24
GB8329748D0 (en) 1983-12-14
US4641277A (en) 1987-02-03
GB2132797A (en) 1984-07-11
GB2132797B (en) 1986-02-19

Similar Documents

Publication Publication Date Title
DE3011552C2 (https=)
DE2725718C2 (de) Datenverarbeitungsanordnung zum Übersetzen von virtuellen Adressen
DE69225622T2 (de) Adressenübersetzungspufferspeicher mit per Eingabe veränderlicher Seitengrösse
DE69022716T2 (de) Mehrrechnersystem mit verteilten gemeinsamen Betriebsmitteln und dynamischer und selektiver Vervielfältigung globaler Daten und Verfahren dafür.
DE69329590T2 (de) Periphere Festkörperspeichervorrichtung
DE69215538T2 (de) Verfahren zur verbesserung von partiellen streifenschreib-operationen einer speicherplattenanordnung
DE68923863T2 (de) Ein-/Ausgabecachespeicherung.
DE2428348C2 (de) Verfahren zur Weiterbenutzung eines fehlerhaften Datenspeichers und Einrichtung zur Durchführung dieses Verfahrens
DE69029173T2 (de) Mikroprozessor
DE3048365A1 (de) Speicherschutzsystem und datenverarbeitungssystem mit einem solchen speicherschutzsystem
EP0013737A1 (de) Mehrstufige Speicherhierarchie für ein Datenverarbeitungssystem
DE2226382A1 (de) Datenverarbeitungsanlage
DE3502147C2 (https=)
DE3102150A1 (de) "schaltungsanordnung mit einem cachespeicher fuer eine zentraleinheit einer datenverarbeitungsanlage
DE3825028C2 (https=)
DE3131204A1 (de) Adressumrechnungs- und generatoranordnung
DE2939411C2 (de) Datenverarbeitungsanlage mit virtueller Speicheradressierung
DE3750175T2 (de) Mikroprozessor mit einem Cache-Speicher.
DE1901806A1 (de) Schaltungsanordnung zur Kompensation schadhafter Speicherzellen in Datenspeichern
DE3340956C2 (https=)
DE3911721C2 (https=)
DE3873388T2 (de) Cache-speicher.
DE4117672A1 (de) Verfahren und vorrichtung zur steuerung eines zwischen einer zentraleinheit und einem arbeitsspeicher angeordneten cache-speichers
DE68927306T2 (de) Emulationssystem, fähig zur Anpassung an Mikrorechner mit verschiedenen On-Chip-Speicherkapazitäten
DE3586524T2 (de) Durch beide, physikalische und virtuelle addressen, addressierbarer cache-speicher.

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee