DE3279896D1 - Memory circuit - Google Patents

Memory circuit

Info

Publication number
DE3279896D1
DE3279896D1 DE8282109005T DE3279896T DE3279896D1 DE 3279896 D1 DE3279896 D1 DE 3279896D1 DE 8282109005 T DE8282109005 T DE 8282109005T DE 3279896 T DE3279896 T DE 3279896T DE 3279896 D1 DE3279896 D1 DE 3279896D1
Authority
DE
Germany
Prior art keywords
memory circuit
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282109005T
Other languages
English (en)
Inventor
Akira Nagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3279896D1 publication Critical patent/DE3279896D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8282109005T 1981-09-29 1982-09-29 Memory circuit Expired DE3279896D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56154347A JPS5856287A (ja) 1981-09-29 1981-09-29 半導体回路

Publications (1)

Publication Number Publication Date
DE3279896D1 true DE3279896D1 (en) 1989-09-21

Family

ID=15582168

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282109005T Expired DE3279896D1 (en) 1981-09-29 1982-09-29 Memory circuit

Country Status (4)

Country Link
US (1) US4500974A (de)
EP (1) EP0075942B1 (de)
JP (1) JPS5856287A (de)
DE (1) DE3279896D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4627032A (en) * 1983-11-25 1986-12-02 At&T Bell Laboratories Glitch lockout circuit for memory array
JPS60163295A (ja) * 1984-02-03 1985-08-26 Hitachi Ltd 半導体記憶装置
JPS62197990A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp 半導体記憶回路
US4870616A (en) * 1987-09-29 1989-09-26 Maryland Compact register set using a psram array
JPH0430388A (ja) * 1990-05-25 1992-02-03 Oki Electric Ind Co Ltd 半導体記憶回路
US5272676A (en) * 1990-11-20 1993-12-21 Hitachi, Ltd. Semiconductor integrated circuit device
US5430680A (en) * 1993-10-12 1995-07-04 United Memories, Inc. DRAM having self-timed burst refresh mode
US6587896B1 (en) * 1998-02-27 2003-07-01 Micron Technology, Inc. Impedance matching device for high speed memory bus
US7095642B1 (en) 2003-03-27 2006-08-22 Cypress Semiconductor Corporation Method and circuit for reducing defect current from array element failures in random access memories
US8072834B2 (en) * 2005-08-25 2011-12-06 Cypress Semiconductor Corporation Line driver circuit and method with standby mode of operation
US20080080284A1 (en) * 2006-09-15 2008-04-03 Peter Mayer Method and apparatus for refreshing memory cells of a memory
JP6429260B1 (ja) * 2017-11-09 2018-11-28 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 疑似スタティックランダムアクセスメモリおよびそのリフレッシュ方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693363A (en) * 1979-12-04 1981-07-28 Fujitsu Ltd Semiconductor memory

Also Published As

Publication number Publication date
EP0075942A2 (de) 1983-04-06
EP0075942A3 (en) 1986-01-29
JPH0223958B2 (de) 1990-05-25
EP0075942B1 (de) 1989-08-16
JPS5856287A (ja) 1983-04-02
US4500974A (en) 1985-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee