DE3278184D1 - Cmos devices with self-aligned channel stops - Google Patents
Cmos devices with self-aligned channel stopsInfo
- Publication number
- DE3278184D1 DE3278184D1 DE8282304479T DE3278184T DE3278184D1 DE 3278184 D1 DE3278184 D1 DE 3278184D1 DE 8282304479 T DE8282304479 T DE 8282304479T DE 3278184 T DE3278184 T DE 3278184T DE 3278184 D1 DE3278184 D1 DE 3278184D1
- Authority
- DE
- Germany
- Prior art keywords
- self
- cmos devices
- channel stops
- aligned channel
- aligned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/95—Multilayer mask including nonradiation sensitive layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/297,903 US4411058A (en) | 1981-08-31 | 1981-08-31 | Process for fabricating CMOS devices with self-aligned channel stops |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3278184D1 true DE3278184D1 (en) | 1988-04-07 |
Family
ID=23148206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282304479T Expired DE3278184D1 (en) | 1981-08-31 | 1982-08-25 | Cmos devices with self-aligned channel stops |
Country Status (4)
Country | Link |
---|---|
US (1) | US4411058A (de) |
EP (1) | EP0074215B1 (de) |
JP (1) | JPH0691201B2 (de) |
DE (1) | DE3278184D1 (de) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4399605A (en) * | 1982-02-26 | 1983-08-23 | International Business Machines Corporation | Method of making dense complementary transistors |
US4471523A (en) * | 1983-05-02 | 1984-09-18 | International Business Machines Corporation | Self-aligned field implant for oxide-isolated CMOS FET |
US4710477A (en) * | 1983-09-12 | 1987-12-01 | Hughes Aircraft Company | Method for forming latch-up immune, multiple retrograde well high density CMOS FET |
US4570331A (en) * | 1984-01-26 | 1986-02-18 | Inmos Corporation | Thick oxide field-shield CMOS process |
US4535532A (en) * | 1984-04-09 | 1985-08-20 | At&T Bell Laboratories | Integrated circuit contact technique |
DE3584113D1 (de) * | 1984-06-15 | 1991-10-24 | Harris Corp | Verfahren zum herstellen selbstjustierter bereiche in einem substrat. |
US4599789A (en) * | 1984-06-15 | 1986-07-15 | Harris Corporation | Process of making twin well VLSI CMOS |
US4578859A (en) * | 1984-08-22 | 1986-04-01 | Harris Corporation | Implant mask reversal process |
US4696092A (en) * | 1984-07-02 | 1987-09-29 | Texas Instruments Incorporated | Method of making field-plate isolated CMOS devices |
US4600445A (en) * | 1984-09-14 | 1986-07-15 | International Business Machines Corporation | Process for making self aligned field isolation regions in a semiconductor substrate |
US4558508A (en) * | 1984-10-15 | 1985-12-17 | International Business Machines Corporation | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step |
JPS6197859A (ja) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | 相補型mos集積回路の製造方法 |
US4584027A (en) * | 1984-11-07 | 1986-04-22 | Ncr Corporation | Twin well single mask CMOS process |
US4578128A (en) * | 1984-12-03 | 1986-03-25 | Ncr Corporation | Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants |
US4604790A (en) * | 1985-04-01 | 1986-08-12 | Advanced Micro Devices, Inc. | Method of fabricating integrated circuit structure having CMOS and bipolar devices |
NL8501992A (nl) * | 1985-07-11 | 1987-02-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
WO1987005443A1 (en) * | 1986-03-04 | 1987-09-11 | Motorola, Inc. | High/low doping profile for twin well process |
US4889825A (en) * | 1986-03-04 | 1989-12-26 | Motorola, Inc. | High/low doping profile for twin well process |
US4707455A (en) * | 1986-11-26 | 1987-11-17 | General Electric Company | Method of fabricating a twin tub CMOS device |
US5292671A (en) * | 1987-10-08 | 1994-03-08 | Matsushita Electric Industrial, Co., Ltd. | Method of manufacture for semiconductor device by forming deep and shallow regions |
NL8802219A (nl) * | 1988-09-09 | 1990-04-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin door ionenimplantaties halfgeleidergebieden worden gevormd. |
JPH0824171B2 (ja) * | 1990-05-02 | 1996-03-06 | 三菱電機株式会社 | 半導体記憶装置およびその製造方法 |
KR920008951A (ko) * | 1990-10-05 | 1992-05-28 | 김광호 | 더블도우프된 채널스톱층을 가지는 반도체장치 및 그 제조방법 |
DE69415040T2 (de) * | 1993-10-12 | 1999-07-15 | H.B. Fuller Licensing & Financing, Inc., Wilmington, Del. | Polystyrol-ethylen/buthylen-polystyrol schmelzkleber |
US5863977A (en) * | 1993-10-12 | 1999-01-26 | H. B. Fuller Licensing & Financing, Inc. | High molecular weight S-EB-S hot melt adhesive |
US5619053A (en) * | 1995-05-31 | 1997-04-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an SOI structure |
US5956583A (en) * | 1997-06-30 | 1999-09-21 | Fuller; Robert T. | Method for forming complementary wells and self-aligned trench with a single mask |
US6133077A (en) | 1998-01-13 | 2000-10-17 | Lsi Logic Corporation | Formation of high-voltage and low-voltage devices on a semiconductor substrate |
US6093585A (en) * | 1998-05-08 | 2000-07-25 | Lsi Logic Corporation | High voltage tolerant thin film transistor |
US6323103B1 (en) | 1998-10-20 | 2001-11-27 | Siemens Aktiengesellschaft | Method for fabricating transistors |
US6348736B1 (en) * | 1999-10-29 | 2002-02-19 | International Business Machines Corporation | In situ formation of protective layer on silsesquioxane dielectric for dual damascene process |
US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
US6764890B1 (en) * | 2003-01-29 | 2004-07-20 | Cypress Semiconductor Corporation | Method of adjusting the threshold voltage of a mosfet |
KR100685926B1 (ko) * | 2003-06-11 | 2007-02-23 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 및 이의 제조방법 |
US7087476B2 (en) * | 2004-07-28 | 2006-08-08 | Intel Corporation | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit |
US8497167B1 (en) * | 2007-01-17 | 2013-07-30 | National Semiconductor Corporation | EDS protection diode with pwell-nwell resurf |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3892609A (en) * | 1971-10-07 | 1975-07-01 | Hughes Aircraft Co | Production of mis integrated devices with high inversion voltage to threshold voltage ratios |
US3983620A (en) * | 1975-05-08 | 1976-10-05 | National Semiconductor Corporation | Self-aligned CMOS process for bulk silicon and insulating substrate device |
JPS5270779A (en) * | 1975-12-09 | 1977-06-13 | Fujitsu Ltd | Manufacture of complementary-type integrated circuit |
JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
US4013484A (en) * | 1976-02-25 | 1977-03-22 | Intel Corporation | High density CMOS process |
US4046606A (en) * | 1976-05-10 | 1977-09-06 | Rca Corporation | Simultaneous location of areas having different conductivities |
JPS52143782A (en) * | 1976-05-26 | 1977-11-30 | Hitachi Ltd | Construction of complementary mis-ic and its production |
JPS5413779A (en) * | 1977-07-04 | 1979-02-01 | Toshiba Corp | Semiconductor integrated circuit device |
US4224733A (en) * | 1977-10-11 | 1980-09-30 | Fujitsu Limited | Ion implantation method |
GB2024504B (en) * | 1978-06-29 | 1982-10-20 | Philips Electronic Associated | Manufacture of integrated circuits |
JPS5529116A (en) * | 1978-08-23 | 1980-03-01 | Hitachi Ltd | Manufacture of complementary misic |
IT1166587B (it) * | 1979-01-22 | 1987-05-05 | Ates Componenti Elettron | Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate |
US4306916A (en) * | 1979-09-20 | 1981-12-22 | American Microsystems, Inc. | CMOS P-Well selective implant method |
JPS5691461A (en) * | 1979-12-25 | 1981-07-24 | Fujitsu Ltd | Manufacturing of complementary mos integrated circuit |
US4315781A (en) * | 1980-04-23 | 1982-02-16 | Hughes Aircraft Company | Method of controlling MOSFET threshold voltage with self-aligned channel stop |
-
1981
- 1981-08-31 US US06/297,903 patent/US4411058A/en not_active Expired - Lifetime
-
1982
- 1982-08-25 EP EP82304479A patent/EP0074215B1/de not_active Expired
- 1982-08-25 DE DE8282304479T patent/DE3278184D1/de not_active Expired
- 1982-08-31 JP JP57150164A patent/JPH0691201B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0691201B2 (ja) | 1994-11-14 |
EP0074215A2 (de) | 1983-03-16 |
EP0074215B1 (de) | 1988-03-02 |
JPS5878453A (ja) | 1983-05-12 |
US4411058A (en) | 1983-10-25 |
EP0074215A3 (en) | 1984-12-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |