DE3277598D1 - Scan-out circuitry - Google Patents
Scan-out circuitryInfo
- Publication number
- DE3277598D1 DE3277598D1 DE8282306522T DE3277598T DE3277598D1 DE 3277598 D1 DE3277598 D1 DE 3277598D1 DE 8282306522 T DE8282306522 T DE 8282306522T DE 3277598 T DE3277598 T DE 3277598T DE 3277598 D1 DE3277598 D1 DE 3277598D1
- Authority
- DE
- Germany
- Prior art keywords
- counter
- shift register
- scan
- operator
- constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56196746A JPS58121458A (ja) | 1981-12-09 | 1981-12-09 | スキヤンアウト方式 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3277598D1 true DE3277598D1 (en) | 1987-12-10 |
Family
ID=16362911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282306522T Expired DE3277598D1 (en) | 1981-12-09 | 1982-12-07 | Scan-out circuitry |
Country Status (7)
Country | Link |
---|---|
US (1) | US4491935A (de) |
EP (1) | EP0081966B1 (de) |
JP (1) | JPS58121458A (de) |
AU (1) | AU539000B2 (de) |
CA (1) | CA1181846A (de) |
DE (1) | DE3277598D1 (de) |
ES (1) | ES518009A0 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2564619B1 (fr) * | 1984-05-21 | 1986-09-26 | Enertec | Dispositif elementaire de traitement de donnees |
DE3431785A1 (de) * | 1984-08-29 | 1986-03-13 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung fuer einen nach dem warteschlangenprinzip arbeitenden steuerspeicher (fifo-speicher) |
JPS63291134A (ja) * | 1987-05-22 | 1988-11-29 | Toshiba Corp | 論理集積回路 |
US6128758A (en) * | 1998-05-20 | 2000-10-03 | National Semiconductor Corporation | Modular re-useable bus architecture |
US6851080B1 (en) * | 1999-02-05 | 2005-02-01 | 3Com Corporation | Automatic activation of ASIC test mode |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3806891A (en) * | 1972-12-26 | 1974-04-23 | Ibm | Logic circuit for scan-in/scan-out |
JPS5352029A (en) * | 1976-10-22 | 1978-05-12 | Fujitsu Ltd | Arithmetic circuit unit |
US4169289A (en) * | 1977-07-08 | 1979-09-25 | Bell Telephone Laboratories, Incorporated | Data processor with improved cyclic data buffer apparatus |
JPS5853774B2 (ja) * | 1978-12-29 | 1983-12-01 | 株式会社日立製作所 | 情報処理装置 |
-
1981
- 1981-12-09 JP JP56196746A patent/JPS58121458A/ja active Granted
-
1982
- 1982-12-02 AU AU91088/82A patent/AU539000B2/en not_active Ceased
- 1982-12-07 DE DE8282306522T patent/DE3277598D1/de not_active Expired
- 1982-12-07 ES ES518009A patent/ES518009A0/es active Granted
- 1982-12-07 EP EP82306522A patent/EP0081966B1/de not_active Expired
- 1982-12-07 US US06/447,659 patent/US4491935A/en not_active Expired - Lifetime
- 1982-12-08 CA CA000417266A patent/CA1181846A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4491935A (en) | 1985-01-01 |
AU9108882A (en) | 1983-06-16 |
ES8401807A1 (es) | 1984-01-01 |
ES518009A0 (es) | 1984-01-01 |
CA1181846A (en) | 1985-01-29 |
JPS58121458A (ja) | 1983-07-19 |
EP0081966A3 (en) | 1985-05-29 |
JPS6150340B2 (de) | 1986-11-04 |
EP0081966B1 (de) | 1987-11-04 |
EP0081966A2 (de) | 1983-06-22 |
AU539000B2 (en) | 1984-09-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |