DE3275619D1 - Input signal responsive pulse generating and biasing circuit for integrated circuits - Google Patents
Input signal responsive pulse generating and biasing circuit for integrated circuitsInfo
- Publication number
- DE3275619D1 DE3275619D1 DE8282111812T DE3275619T DE3275619D1 DE 3275619 D1 DE3275619 D1 DE 3275619D1 DE 8282111812 T DE8282111812 T DE 8282111812T DE 3275619 T DE3275619 T DE 3275619T DE 3275619 D1 DE3275619 D1 DE 3275619D1
- Authority
- DE
- Germany
- Prior art keywords
- input signal
- integrated circuits
- pulse generating
- biasing circuit
- signal responsive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/466—Sources with reduced influence on propagation delay
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Logic Circuits (AREA)
- Pulse Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/340,438 US4433252A (en) | 1982-01-18 | 1982-01-18 | Input signal responsive pulse generating and biasing circuit for integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3275619D1 true DE3275619D1 (en) | 1987-04-09 |
Family
ID=23333353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282111812T Expired DE3275619D1 (en) | 1982-01-18 | 1982-12-20 | Input signal responsive pulse generating and biasing circuit for integrated circuits |
Country Status (4)
Country | Link |
---|---|
US (1) | US4433252A (de) |
EP (1) | EP0084146B1 (de) |
JP (1) | JPS58124322A (de) |
DE (1) | DE3275619D1 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5493572A (en) * | 1981-04-17 | 1996-02-20 | Hitachi, Ltd. | Semiconductor integrated circuit with voltage limiter having different output ranges for normal operation and performing of aging tests |
USRE35313E (en) * | 1981-04-17 | 1996-08-13 | Hitachi, Ltd. | Semiconductor integrated circuit with voltage limiter having different output ranges from normal operation and performing of aging tests |
US5566185A (en) * | 1982-04-14 | 1996-10-15 | Hitachi, Ltd. | Semiconductor integrated circuit |
JPS60103589A (ja) * | 1983-11-11 | 1985-06-07 | Nec Corp | タイミング信号発生回路 |
US4694197A (en) * | 1986-01-06 | 1987-09-15 | Rca Corporation | Control signal generator |
US4918334A (en) * | 1988-08-15 | 1990-04-17 | International Business Machines Corporation | Bias voltage generator for static CMOS circuits |
US5051630A (en) * | 1990-03-12 | 1991-09-24 | Tektronix, Inc. | Accurate delay generator having a compensation feature for power supply voltage and semiconductor process variations |
KR0142960B1 (ko) * | 1995-05-25 | 1998-08-17 | 김광호 | 전원 변동에 안정된 반도체 메모리 장치 |
US6097618A (en) * | 1997-12-11 | 2000-08-01 | Cypress Semiconductor Corporation | Apparatus and method for correcting data in a non-volatile random access memory |
IT1304117B1 (it) * | 1998-12-17 | 2001-03-07 | St Microelectronics Srl | Generatore di impulsi di corrente con tempi di commutazionesimmetrici ed indipendenti dal processo e dalla temperatura |
US8072834B2 (en) * | 2005-08-25 | 2011-12-06 | Cypress Semiconductor Corporation | Line driver circuit and method with standby mode of operation |
US7859925B1 (en) | 2006-03-31 | 2010-12-28 | Cypress Semiconductor Corporation | Anti-fuse latch self-test circuit and method |
US7859906B1 (en) | 2007-03-30 | 2010-12-28 | Cypress Semiconductor Corporation | Circuit and method to increase read margin in non-volatile memories using a differential sensing circuit |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3508084A (en) * | 1967-10-06 | 1970-04-21 | Texas Instruments Inc | Enhancement-mode mos circuitry |
US3778784A (en) * | 1972-02-14 | 1973-12-11 | Intel Corp | Memory system incorporating a memory cell and timing means on a single semiconductor substrate |
DE2232274C2 (de) * | 1972-06-30 | 1982-05-06 | Ibm Deutschland Gmbh, 7000 Stuttgart | Statischer Halbleiterspeicher mit Feldeffekttransistoren |
US3757200A (en) * | 1972-07-10 | 1973-09-04 | Gen Instrument Corp | Mos voltage regulator |
US3906464A (en) * | 1974-06-03 | 1975-09-16 | Motorola Inc | External data control preset system for inverting cell random access memory |
US3959781A (en) * | 1974-11-04 | 1976-05-25 | Intel Corporation | Semiconductor random access memory |
GB1533231A (en) * | 1974-11-07 | 1978-11-22 | Hitachi Ltd | Electronic circuits incorporating an electronic compensating circuit |
US3970875A (en) * | 1974-11-21 | 1976-07-20 | International Business Machines Corporation | LSI chip compensator for process parameter variations |
US3961269A (en) * | 1975-05-22 | 1976-06-01 | Teletype Corporation | Multiple phase clock generator |
US4016434A (en) * | 1975-09-04 | 1977-04-05 | International Business Machines Corporation | Load gate compensator circuit |
US4239991A (en) * | 1978-09-07 | 1980-12-16 | Texas Instruments Incorporated | Clock voltage generator for semiconductor memory |
DE2855724A1 (de) * | 1978-12-22 | 1980-07-03 | Ibm Deutschland | Verfahren und vorrichtung zur angleichung der unterschiedlichen signalverzoegerungszeiten von halbleiterchips |
-
1982
- 1982-01-18 US US06/340,438 patent/US4433252A/en not_active Expired - Lifetime
- 1982-12-20 JP JP57222230A patent/JPS58124322A/ja active Granted
- 1982-12-20 EP EP82111812A patent/EP0084146B1/de not_active Expired
- 1982-12-20 DE DE8282111812T patent/DE3275619D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0084146A2 (de) | 1983-07-27 |
EP0084146B1 (de) | 1987-03-04 |
JPH0241928B2 (de) | 1990-09-20 |
US4433252A (en) | 1984-02-21 |
EP0084146A3 (en) | 1984-10-03 |
JPS58124322A (ja) | 1983-07-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
GB2067836B (en) | Control signal generating circuit and a semiconductor integrated circuit including such a circuit | |
GB2124846B (en) | Pulse signal processing circuits | |
GB2074372B (en) | Integrated circuit field effect transistors | |
GB2028585B (en) | On board integrated circuit chip signal source abstract of the disclosure | |
GB2121632B (en) | Signal comparing circuits | |
DE3378814D1 (en) | Electronic circuit device | |
DE3275619D1 (en) | Input signal responsive pulse generating and biasing circuit for integrated circuits | |
DE3370269D1 (en) | An electronic device comprising integrated circuits | |
JPS56167358A (en) | Input protecting device for integrated circuit | |
PT78978A (en) | Signal transition enhancement circuit | |
DE3066849D1 (en) | Delay signal generating circuit | |
EP0162460A3 (en) | Integrated circuit with an input protective device | |
GB2134736B (en) | Signal generating circuit | |
EP0140744A3 (en) | Integrated circuit device | |
DE3377963D1 (en) | Signal input circuit | |
EP0219291A3 (en) | Cmos integrated circuit for signal delay | |
JPS57100528A (en) | Set value inputting device for electronic circuit device | |
EP0120586A3 (en) | Signal processing circuits | |
JPS5734355A (en) | Integrated circuit device | |
DE3378807D1 (en) | Integrated circuit comprising an input protection device | |
DE3372155D1 (en) | Signal processing circuits | |
JPS57113259A (en) | Integrated circuit device | |
GB2149130B (en) | Testing electronic circuits | |
GB2181612B (en) | Output circuit for electronic circuits | |
JPS56116699A (en) | Electronic circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |