DE3273853D1 - Circuit for generating a substrate bias voltage - Google Patents

Circuit for generating a substrate bias voltage

Info

Publication number
DE3273853D1
DE3273853D1 DE8282303325T DE3273853T DE3273853D1 DE 3273853 D1 DE3273853 D1 DE 3273853D1 DE 8282303325 T DE8282303325 T DE 8282303325T DE 3273853 T DE3273853 T DE 3273853T DE 3273853 D1 DE3273853 D1 DE 3273853D1
Authority
DE
Germany
Prior art keywords
generating
circuit
bias voltage
substrate bias
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282303325T
Other languages
German (de)
English (en)
Inventor
Takumi Miyashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3273853D1 publication Critical patent/DE3273853D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Logic Circuits (AREA)
DE8282303325T 1981-06-29 1982-06-25 Circuit for generating a substrate bias voltage Expired DE3273853D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101125A JPS583328A (ja) 1981-06-29 1981-06-29 基板電圧発生回路

Publications (1)

Publication Number Publication Date
DE3273853D1 true DE3273853D1 (en) 1986-11-20

Family

ID=14292349

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282303325T Expired DE3273853D1 (en) 1981-06-29 1982-06-25 Circuit for generating a substrate bias voltage

Country Status (4)

Country Link
US (1) US4454571A (enExample)
EP (1) EP0068842B1 (enExample)
JP (1) JPS583328A (enExample)
DE (1) DE3273853D1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4581546A (en) * 1983-11-02 1986-04-08 Inmos Corporation CMOS substrate bias generator having only P channel transistors in the charge pump
US4571505A (en) * 1983-11-16 1986-02-18 Inmos Corporation Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits
NL8402764A (nl) * 1984-09-11 1986-04-01 Philips Nv Schakeling voor het opwekken van een substraatvoorspanning.
US4704547A (en) * 1984-12-10 1987-11-03 American Telephone And Telegraph Company, At&T Bell Laboratories IGFET gating circuit having reduced electric field degradation
US4628214A (en) * 1985-05-22 1986-12-09 Sgs Semiconductor Corporation Back bias generator
JPS62159917A (ja) * 1986-01-08 1987-07-15 Toshiba Corp 集積回路におけるインバ−タ回路
JP3556679B2 (ja) 1992-05-29 2004-08-18 株式会社半導体エネルギー研究所 電気光学装置
JP2738335B2 (ja) * 1995-04-20 1998-04-08 日本電気株式会社 昇圧回路
US5880593A (en) * 1995-08-30 1999-03-09 Micron Technology, Inc. On-chip substrate regulator test mode
JPH09293789A (ja) * 1996-04-24 1997-11-11 Mitsubishi Electric Corp 半導体集積回路
US6275395B1 (en) * 2000-12-21 2001-08-14 Micrel, Incorporated Accelerated turn-off of MOS transistors by bootstrapping
US6510062B2 (en) * 2001-06-25 2003-01-21 Switch Power, Inc. Method and circuit to bias output-side width modulation control in an isolating voltage converter system
US20050077950A1 (en) * 2003-10-14 2005-04-14 Robinson Curtis B. Negative charge pump
JP2005151777A (ja) * 2003-11-19 2005-06-09 Sanyo Electric Co Ltd チャージポンプ回路およびアンプ
US9819260B2 (en) * 2015-01-15 2017-11-14 Nxp B.V. Integrated circuit charge pump with failure protection
JP6658112B2 (ja) * 2016-03-04 2020-03-04 セイコーエプソン株式会社 温度補償機能付き時計

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574182B2 (enExample) * 1974-02-14 1982-01-25
CH1057575A4 (enExample) * 1975-08-14 1977-03-15
US4045719A (en) * 1976-06-14 1977-08-30 Rca Corporation Regulated voltage source
US4115710A (en) * 1976-12-27 1978-09-19 Texas Instruments Incorporated Substrate bias for MOS integrated circuit
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation
JPS5632758A (en) * 1979-08-27 1981-04-02 Fujitsu Ltd Substrate bias generating circuit

Also Published As

Publication number Publication date
EP0068842B1 (en) 1986-10-15
US4454571A (en) 1984-06-12
EP0068842A1 (en) 1983-01-05
JPH0157533B2 (enExample) 1989-12-06
JPS583328A (ja) 1983-01-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee