DE3220205A1 - ELECTRICAL CIRCUIT ARRANGEMENT - Google Patents

Description

DESCRIPTION

The invention relates to an electronic circuit arrangement, as indicated in the preamble of claim 1.

It relates to an electronic circuit with a push-pull output stage, in particular an electronic one Circuit used in an EPROM (electrically programmable read-only memory).

In recent years, electronic circuit arrangements in the form of integrated semiconductor circuits services are being produced, increasing requirements with regard to a high quality level and a high level of integration been asked.

In the case of an electronic circuit arrangement such as an EPROM, various push-pull output stages can be provided such as for the purpose of driving a desired load with a relatively large dynamic range to be able to provide a signal with a relatively high speed, as well as the To achieve the property of relatively low power consumption, etc.

A push-pull output stage requires an inverted and a non-inverted signal in order to contain two To control transistors in push-pull. The inverted and the non-inverted signal can be from a suitable Driver circuit comprising an inverter can be made available. However, the driver circuit has an operating delay on. As a result, the timing of changes to the. inverted and the non-inverted signals changed in an undesirable manner. The two are the push-pull output stage forming transistors are simultaneously brought into the "on" state by the fact that the inverted and the non-inverted signals assume a certain level, for example a high level, at the same time. Hence, a through current of one relatively develops great value. The through current of the push-pull

Output stage causes an undesirable potential fluctuation on the supply voltage line of the circuit.

Accordingly, the inverted and the non-inverted signal must be set to sizes that are mutually exclusive are in reasonable proportion.

A circuit including a bootstrap capacitor may be coupled to the push-pull output stage to provide the To increase the level of a signal it delivers in a suitable manner. Becomes a push-pull output stage this way so it is used to charge the bootstrap capacitor a signal "with suitable timing is required.

The present invention is directed to improvements in electronic circuitry that includes a Has push-pull output stage, in particular a push-pull output stage, to which a circuit having a bootstrap capacitor is connected.

An object of the invention is to provide an electronic circuit which is suitable for manufacture as integrated semiconductor circuit is suitable.

Another object of the invention is to provide an electronic circuit arrangement in which the surfaces occupied by the circuit elements, wirings, etc. composing the circuit are reduced.

Another object of the invention is to provide an EPROM which has few malfunctions and for one High speed operation is suitable.

The invention will now be described and explained in more detail below with reference to the exemplary embodiments shown in the figures.
Fig. 1 shows a block diagram of an EPROM to which

the invention is applied; Figs. 2 and 3 show circuit diagrams of the block X-DCR

of Fig. 1;

Fig. 4 shows a block diagram for an embodiment of the invention;

Fig. 5 shows a diagram of the waveform for the Operation of the circuit of Figure 4;

Fig. 6 also shows the waveform in a diagram for operation of the circuit of FIG. 4;

Fig. 7 shows in a diagram the layout for circuit elements / which form a push-pull circuit;

FIG. 8 shows a section along the line AA ¹ of FIG. 7;

9 shows a diagram of a layout of circuit elements, which form a bootstrap circuit;

Fig. 10 is a circuit diagram showing a delay circuit;

Figs. 11, 12 and 13 show cross sections of delay devices ;

Fig. 14 is a circuit diagram showing another delay

contraption.

The invention will now be described in detail with reference to the figures.

Fig. 1 shows the circuit blocks of an EPROM in which the invention is embodied.

The entire EPROM, i.e. the various circuit blocks that are within the double-dotted line of the Fig. 1 are located with the known MIS (metal insulator semiconductor) integrated circuit technology as a single integrated circuit arrangement formed.

The EPROM has external connections A1 to An, -Vcc, GND, I / O, Vpp, PRG, OE and CE provided. The external connections A1 to An are supplied with address signals, the external connection Vcc is supplied with a supply voltage of for example + 5 volts supplied. The external terminal I / O receives a data signal from a write-in circuit (not shown) supplied in a data writing process or a programming process, and it delivers in the data read out process Data. An external terminal Vpp is connected to a high write-in voltage of, for example, 25 volts a data write operation. An external connection

During the data readout process, Vpp receives a comparatively low potential of, for example, 0 or 5 volts. The external Connections PRG, OE and CE are each provided with a program control signal or an output enable signal or supplied with a chip enable signal.

A first address buffer circuit is designated by ADB1, the internal address signals al and ÄT to aS with a non-inverted level and one inverted. Provides levels that correspond to the address signals that correspond to the external connections A1 to A8.

X-DCR denotes an X decoding circuit, the operation of which is controlled by control signals ce and ce supplied by control circuits CONT2 and CONT3 and forms the word line control signals for selecting word lines W1 to W256 of the memory array MARY. The X-DCR circuit is brought into the operating state in such a way that the control signals ce and ce assume the low level and the high level, respectively. In the operating state, the X-DCR supplies a signal of a high level, which is a selection level, to a word line which corresponds to the states of the internal address signals a1 and T to ΈΕ. When the control signals ce and ce are high and low, respectively, the X-DCR is in the inoperative state. In this case, all of the word lines W1 to W256 keep the low or the non-selection level regardless of how the combination of the internal address signals a1, äT to ä ~ 8 is,

Ois ßp§iph ^ i ^: f # 3ä M & ftY stilled §y§ §Ιβ§γ Vislgahl of semiconductor permanent storage elements F1 to F256 ¹ , which are arranged in the form of a matrix, from word lines W1 to W256 and from bit lines B1 to Bn.

Without being restricted to this, each of the memory elements FI to F256 'consists of a FAMOS (floating gate avalanche injection MOS) transistor, which has a floating (potential-free) gate and a control gate.

In the case of the memory array MARY, the drain electrodes are those Storage elements arranged in the same row are jointly connected to the bit line

which is assigned to the individual row, while the control gate electrodes of those memory elements that are arranged in the same column are shared with those of this particular one Column assigned word line are connected. Without being restricted to this, the exemplary embodiment has switch MISFETs S1 to S256 in a one-to-one correspondence to the respective memory element columns of the memory field MARY shown in FIG. 1 in order to prevent that leakage currents flow to the unselected memory cells during the writing process. The drain electrode of the switch MISFET corresponding to a column is connected to the common source electrode of the respective Column corresponding storage elements are connected, the gate electrode of the switch MISFET is connected to that of the individual Column corresponding word line connected. The source electrodes of the switch MISFETs S1 to S256 are connected to the Ground point of the circuit connected.

A second address buffer circuit is designated with ADB2, the internal address signals a9 to an with when the address signals arrive at the external connections A9 to An forms an inverted and a non-inverted level. From the internal address signals a9 to an that of the second address buffer circuit ADB2 are supplied, the signals an-1 to are sent to a first control circuit CONT1, the remaining signals are fed to a Y decoder circuit Y-DCR supplied. The Y decoder Y-DCR decodes those supplied from the second address buffer circuit ADB2 Address signals and thus forms selection signals CS1 to CS8, which are fed to a column switch circuit CSW.

The operation of the column switch circuit CSW is controlled by the selection signals CS1 to CS8.

Without being particularly restricted to this, the memory field MARY of FIG. 1 has bit lines B1 to Bn with a Total number of 32 on. Four common bit lines CB1 to CB4 are provided for the 32 bit lines. Accordingly, eight bit lines correspond to a common bit line.

Accordingly, when a selection signal has been supplied from the Y decoding circuit Y-DCRI, four become the selection signal corresponding bit lines via the column switch circuit CSW with the respectively corresponding common Bit lines connected.

If in accordance with the above description a plurality is provided by common bit lines, the capacitances of stray capacitors, parasitic capacitances etc. which are coupled to or exist on each common bit line are made smaller are than in the case where only one common bit line is provided for the 32 bit lines B1-Bn. According to With the structure of the embodiment, the capacitances that limit the signal change speed can be reduced so that a signal can be applied to the common bit line at a higher speed.

The common bit lines CB1 to CB4 are each connected to associated read / write circuits R / W1 to R / W4 connected. The read / write circuits R / W1 to R / W4 are in their respective operating modes by signals controlled by the first control circuit CONT1 and the second control circuit CONT 2 are supplied.

The first control circuit CONT1 actually works as a decoder which receives the internal address signals supplied by the ADB 2 an-1 - an decoded. The output signals of the CONT1 are fed to the read / write circuits R / W1-R / W4 as drive control signals.

Of the four read / write circuits R / W1 to R / W4, output control signals from the first control circuit C0NT1 brought only one into the operating state. The mode of operation of the read / write circuit shown in is brought to the working state is controlled by the control signal supplied from the second control circuit ~ CONT2.

The read / write circuit in the operating state is brought into the writing mode in accordance with the high level of the control signal we. The mode of operation of registered mail is followed by a registered

nal, the one from the external port I / O via a Input / output buffer circuit IOC corresponds to the data signal supplied from the readout / Write circuit supplied to the associated common bit line. The remaining common bit lines are on a certain potential, i.e. to the ground potential corresponding to the inoperative state of the respectively assigned Read / write circuits laid.

The read / write circuit held in the operating state is operated in accordance with the low level of the control signal we brought into the operating mode of reading.

In the read-out mode, the signal of the common bit line sent to the read-out / write-in circuit is supplied to the input / output buffer circuit IOC through the specific read / write circuit. Signals on the remaining common bit lines are neglected because the respective associated read / write circuits are not in the operating state.

In the case where data of one byte (8 bits) is written and read out by means of the address signals A1 to An should / the number of bit lines of the memory field MARY is set to 32 χ 8, i.e. to 256. In this Case will be circuits CSW, R / W and IOC similar to those of Fig. 1 for each group of the 32 bit lines intended.

The second control circuit CONT2 forms internal control signals cJe, we, es etc. according to the chip release signal, of the output enable signal, the program signal and a high write-in voltage, which are respectively the external connections CE or OE, or PRG or Vpp are supplied. The third control circuit CONT3 forms the internal control signal ce which has an opposite phase to the internal control signal ei.

FIG. 2 shows a practical embodiment of a circuit for the decoder X-DCR in the EPROM of FIG. 1.

Without being restricted to this, the decoder X-DCR is divided into three circuit parts, namely into the address

decoding parts DCR1, DCR2 and DCR3.

The operation of the address decoding part DCR1 is carried out by the control signals ce and ce controlled, it delivers the non-inverted signal and the inverted signal in which it the internal address signals of the lower three bits a1 to a3 are decoded. The operation of the address decoding part DCR3 is controlled by the output signals of the address decoding part DCR1, the address decoding part DCR3 decodes the internal address signals of the middle three bits. The address decoding part On receipt of the internal address signals, DCR2 supplies the upper two bits and the output signal of the Address decoding part DCR3 the word line selection signals.

Fig. 2 shows only a unit circuit which forms the address decoding part DCRI; this address decoding part DCR1 consists of a large number of unit circuits which have AND and NAND functions. At internal address signals of the lower three bits and the control signal ce are applied to each unit circuit of the DCR1. The DCR1 contains eight unit circuits so that it has eight states indicated by the address signals of the three bits decoded. The structure and operation of a unit circuit constituting the address decoding part DCR1 becomes with reference to FIG. 3 described in detail below.

Without being limited thereto, the address decoding part DCR3 consists of a plurality of unit circuits with OR-NAND functions. Fig. 2 shows only a unit circuit Ond which is the address decoding part DCR3 forms.

According to the figure, the unit circuit Ond is composed of a load MISFET Q2 of the depletion type, of driver MISFETs Q3 to Q6 of the enhancement type, their respective electrodes with the output signal dcr1 of the DCR1 and the internal address signals of the three bits a6 to a8 supplied and an enhancement type power switch MISFET Q1 connected between the load MISFET Q2 and the power supply terminal Vcc is arranged

and to the gate electrode of which the output signal dcr1 of the DCR1 is applied.

Without limitation, it is provided in particular that in this exemplary embodiment a unit circuit Ond corresponds to four word lines. Accordingly, there are 64 Unit circuits Ond are provided for the 256 word lines W1 to W256.

As a result of this measure, unit circuits of the DCR3 can be constructed without reducing the spacing between the word lines are subject to restrictions in the integrated circuit arrangement. In other words, the packing density must be the A large number of storage elements in the storage field MARY are not reduced.

The output signals dcr1 and der 1 of the respective unit circuits of the address decoding part DCR1 become the corresponding eight unit circuits in the address decoding part DCR3 supplied.

Since the associated decoded address signals dcr1 are supplied by the associated unit circuits of the DCR1 the number of driver MISFETs in the unit Ond the DCR3 can be reduced.

Because of the arrangement described above, the output dcr3 from a unit circuit of the DCR3 becomes high Level only when the address signals of six bits have been brought into a predetermined state. That means, that of the outputs of the 64 unit circuits in the DCR3 only the output of that unit circuit den goes high, which corresponds to the status of the DCR1 and DGR3 supplied 6-bit address signals.

The output signal dcr3 from a unit circuit of the DCR3 is applied to the electrodes on one side of four transmission gate MISFETs Q7, Q9, Q11 and Q13 dated Enrichment type fed together, each corresponding to a word line. These transmission gate MISFETs are "on" and "off" controlled by the output signals of the address decoding part DCR2.

The address decoding part DCR2 is composed of four unit circuits each of which receives the address signals of two

Bits decoded and thus the non-inverted signal and supplies the inverted signal. Fig. 2 illustrates one unit circuit Nnd of the four unit circuits, which form the address decoding part · DCR2. The output signal dcr2 of the unit circuit Nnd is supplied to the gate electrode of the transmission gate MISFET Q7. In appropriate Thus, the gate electrodes of the remaining transmission gates -MI SFETs Q9, Q11 and Q13 do not receive the output signals of the shown unit circuits supplied. The transmission gate MISFETs Q 7, Ql1 and Q13 are replaced by the Address decoding part DCR2 supplied signals alternatively brought into the "on" state. Accordingly, it becomes an output signal of the address decoding part DCR2 via one of the four transmission gate MISFETs to the electrode on the the other side, i.e. the output electrode of the individual MIS-FET.

Between the respective output terminals of the transmission gate MISFETs Q7, Q9, Q11 and Q13 are of the enhancement type and the ground potential terminal GND of the circuit Enrichment type MISFETs Q8, Q10, Q12 and Q14 are switched. The signal of FIG. 2 supplied by the unit circuit Nnd is applied to the gate of the MISFET Q8. In a corresponding way become the gate electrodes of the MISFETs Q10, Q12 and Q14, respectively Signals are supplied which are phase to the signals which the gates of the transmission gate MISFETs Q9, Q11 and Q13 are opposite. Accordingly becomes one consisting of a MISFET and a transfer MISFET (for example, consisting of transistors Q8 and Q7) set complementarily connected and operated.

Between the respective output side electrodes of the transmission gate MISFETs Q7, Q9, Q11 and Q13 and the Word lines WI to W4 corresponding to these output electrodes, are transmission gate MISFETs Q15-Q18 of the depletion type arranged. A write-in signal is commonly applied to the gates of the transmission gate MISFETs Q15-Q18 we created. MISFETs Q19, Q20, etc. are arranged between the word lines and the terminal Vpp of the high write-in voltage, where the gate electrode and the source electrode

are connected to each other and which serve as a load. Without being limited to this, the MISFETs have Q15 through Q2O of the depletion type, a layered gate structure so that they have drain breakdown voltages whose value is greater than a high voltage applied to terminal Vpp for the high writing voltage is applied.

The 256 (64 χ 4) word lines W1 to W256 can be used in of the above embodiment can be selected by the X-DCR.

As can be seen from the following description, the unselected word lines are given a low level, which is approximately equal to the ground potential (0 volts) of the circuit. In contrast, received during the readout process the selected word lines will have a high level approximately equal to that applied to the Vcc terminal Supply voltage (+ 5 volts), and during a writing process they receive a high voltage that is im is substantially equal to the high voltage (+25 volts) applied to the input terminal Vpp.

Fig. 3 shows an embodiment of a unit circuit with which the address decoding part DCR1 is formed will.

Referring to Fig. 3, the decoding part has a depletion type load MISFET Q21 whose gate electrode is connected to its source electrode, furthermore driver MISFETs Q23 to Q25, each of which has internal gate electrodes Address signals a1 to a3 are applied, as well as a-MISFET Q22, the one between the interconnected source electrodes of the driver MISFETs Q23 to Q25 and the ground potential connection is arranged and at the gate of which the control signal ce is applied. The output of the decoding part is connected once to the gate electrodes of a MISFET Q28 and an output MISFET via an isolating MISFET Q26 Q3O applied to the side of the power supply connection and, on the other hand, it is applied to the gate electrodes of enhancement type driver MISFETs Q37 and Q40 created.

An inverter circuit has a load MISFET Q36 from Depletion type whose gate electrode is connected to its source electrode, and further comprises a driver MISFET Enrichment type Q37, as well as a power switch MISFET Q38 of the enhancement type, to the gate of which the control signal ce is applied. The output of this Inverter circuit is connected to the gate electrodes of the output MISFETs Q32 and Q39 as well as through a delay circuit CR3 is applied to the gate electrode of a MISFET Q31. As will be described in detail with reference to Fig. 4, the delay circuit CR3 is provided so as to a bootstrap capacitor CB can store a large amount of charges.

A first push-pull output circuit comprises enhancement MISFETs Q40 and Q41, which are connected in series and at the gate electrodes of which the output signal of the Decoding part and the control signal ce are applied, it also has an output MISFET Q39, at its gate the output of the inverter circuit is applied.

The first push-pull output circuit supplies a decoding signal dcr1 which is related to the output signal of the decoding part is inverted.

The output MISFETs Q30 and Q32 form a second push-pull output circuit. Corresponding to the switching circuit shown in the figure, the decoding signal dcr1 occurs at the common connection point of the output MISFETs Q30 and Q32. .

In Fig. 3, the MISFETs Q28 and Q31 and form the Bootstrap capacitor CB a bootstrap circuit.

The level of the decoding signal, which is supplied to the gate electrodes of the output MISFETs Q30 and Q33 via the isolating MISFET Q26, is raised above the supply voltage Vcc by the bootstrap circuit. The gate potential of the output MISFET Q3O is raised sufficiently so that it receives the "on" resistance sufficiently low. Due to the sufficiently low "on" resistance of the output MISFET Q30, the slew rate of the decoding

signals dcr1 must be sufficiently high, even if the DCR3 represents a relatively large capacitive load. Farther the drop in the word line selection level with respect to the power supply voltage Vcc in the reading operation can be made small because the level of the decoding signal dcr1 is sufficient can be raised.

According to Fig. 3, a MISFET Q27 is provided to the to be able to dissipate charges stored in the bootstrap capacitor CB, its "on" and "off" states controlled by the control signal ce.

In the circuit of FIG. 3 there is also a voltage divider circuit and a resistance device is provided for the readout operation to be carried out in one state can, in which a high voltage of, for example, 25 volts is applied to the terminal Vpp for high writing voltage can and thus the so-called verify process (check for Match) can be performed.

An enhancement MISFET Q34 and a depletion MISFET Q35 constituting a voltage dividing circuit are between the terminal Vpp for the high write voltage and the terminal Vcc for the logic supply voltage in series switched. The gate electrodes of these MISFETs Q34 and Q35 are connected to the respective drain electrodes. Without being limited thereto, the MISFETs Q34 and Q35 a stacked gate structure so that they have relatively high drain breakdown voltages. For example, if When a high write voltage of 25 volts is applied to the terminal Vpp, it is applied to the connection point the MISFETs Q34 and Q35 applied a voltage that was higher is than the supply voltage at the terminal Vcc. In the verify process, it is better that the potential of the word line to be selected receives a level which is essentially is equal to the voltage level that the word line assumes during the process of reading out data, i.e. one Level which is substantially equal to the supply voltage Vcc. Obtained according to the description below the potential level of the word line that is under the word lines

2 is selected, a value that is substantially is equal to the level which the output signal dcr3 of the decoding part DCR3 assumes during the verify operation.

Accordingly, the high level of the output signal dcr3 must be substantially equal to the level of the supply voltage Vcc during the verify operation regardless of the presence of the enhancement type power switch MISFET Q1. The voltage obtained when the high write voltage of 25 volts is applied to the Vpp terminal at the connection point the MISFETs Q34 and Q35 accrues, receives a value of about +7 volts around the power switch MISFET Q1 cheap in to bring the "on" state. This voltage can be obtained by looking at the power ratio between the MISFETs Q34 and Q35 is set appropriately.

via a MISFET Q33 that serves as a resistor this + 7 volt voltage to the source of the output MISFET Q30 created. When the signal dcr1 through the MISFET Q33 is raised to the level of +7 volts, the output MISFET Q3O must go into the "off" state.

Assuming that the gate voltage of the output MISFET Q30 is increased by the threshold voltage of the MISFET above the voltage of the When the Vcc terminal increases, this output MISFET Q30 remains "on" even if its source potential is the same is the voltage of the terminal Vcc. Accordingly, the high level of the decoding signal dcr1 becomes substantial through the "on" output MISFET Q3O held on the voltage of the terminal Vcc.

In order to prevent the high level of the Decoding signal dcr1 limited by the output MISFET Q30 there is a clamp MISFET Q29 between the supply voltage connection Vcc and the gate electrode of the MISFET Q30 is provided. The threshold voltage of MISFET Q29 is smaller than that of the MISFET Q30.

The clamp MISFET Q29 falls into the "on" state when the bootstrap voltage exceeds its threshold voltage .the supply voltage Vcc has risen. Accordingly the bootstrap voltage is held at a value

which is essentially equal to the sum between the supply voltage Vcc and the threshold voltage of MISFET Q29. Due to the retention of the bootstrap tension in in this way, the output MISFET Q3O is automatically turned "off" when its source potential is around is equal to the supply voltage Vcc. As a result, the high level of the decoding signal dcr1 can be large which is in the vicinity of the voltage formed by the voltage dividing circuit (Q34, Q35).

The operation of the address decoding part DCR1, the shown in Fig. 3 will be described below.

If by the high level of the control signal applied to the external terminal CE of FIG. 1, the state of the chip non-selection is displayed, the internal control signal ce receives the low level and the signal ce accordingly the high level. In this chip unselected state, the power switch MISFET Q22 is activated by the Internal control signal ce at a low level is brought into the "off" state. The decoding part therefore provides a Voltage which is substantially equal to the voltage of the terminal Vpp, regardless of those present therein Address signals applied to driver MISFETs Q23 to Q25. There the power switch MISFET Q41 is kept in the "off" state by the control signal ce, which is at a low level, the decoding signal dcr1 assumes a high level, which is im is essentially equal to the voltage of the terminal Vpp. Since the output MISFET Q32 is held in the "on" state, the decoding signal dcr1 receives a low level which is essentially equal to the ground potential of the circuit.

At the same time, the MISFET Q27 goes high internal control signal ce is held in the "on" state. The MISFETs Q28 and Q30 are brought into the "off" state, because their gate electrodes are held low by the "on" MISFET Q27.

Accordingly, the output MISFETs Q3O and Q31 no through current. The bootstrap capacitor CB becomes put into the discharge state because its two

Conclusions by the "on" state MISFETs Q27 and Q31 are set to a low level.

When the control signal applied to the external terminal CE assumes a low level, the chip select level, so the internal control signals ce and ce are given the low level and the high level, respectively. As a result, the decoding part becomes of Fig. 3 brought into the operating state. When the address signals a1 to a3 are not in one to be decoded State, i.e., when at least one of the address signals a1 to a3 is high, at least one of the MISFETs Q23 to Q25 becomes the "on" state brought and thus the decoding part delivers a signal of the low level, namely the signal with the non-selection level. The decoding signals dcr1 and dcr1 remain unchanged at the high and the low level.

When the address signals a1 to a3 are in a state to be decoded, all of the MISFETs Q23 to Q25 in the "off" state so that the decoding part supplies a signal of the high level, i.e. a signal with the selection level. Change according to this signal the decoding signals dcr1 and dcr1 in the low level and the high level.

The following are the operations of the second push-pull output circuit and the bootstrap circuit for the time when the output signal of the decoding part has changed as described above.

When the internal control signal ce assumes the low level and in order to bring the MISFET Q27 into the "off" state, the output signal of the decoding part is above the isolating MISFET Q26 to the gate of the output MISFET Q3O and to one Connection of the bootstrap capacitor CB applied. To the gate of the output_MISFET Q32, the low level signal is applied from the drain of the MISFET Q37. As a result, the decoding signal is obtained dcr1 the high level.

The drain voltage of the MISFET Q37 gets the low level according to the high level output signal of the decoding part, when the internal control signal ce has the high level

has accepted. The low drain voltage of the MISFET Q37 is supplied to the gate electrode of the MISFET Q31 via the delay circuit CS3.

The MISFET Q31 is held in the "on" state until the delay time set by the delay circuit CR3 has expired because the internal control signals ce and ce have assumed the high and the low level, respectively. The bootstrap capacitor is charged accordingly CB due to the high level output of the decoding part.

The MISFET Q31 is brought into the "off" state after the time set by the delay circuit CR3. The other terminal of the bootstrap capacitor CB is accordingly at a comparatively high voltage supplied from the source of MISFET Q28. Accordingly, the gate of the output MISFET Q3O is the Bootstrap voltage applied. At this point the disconnect MISFET Q26 will automatically go into the "off" state by the Bootstrap tension brought. Accordingly, the isolation MISFET Q2 6 prevents the bootstrap capacitor from being charged CB begins to drain in an undesirable manner. Since the undesired discharging of those located in the bootstrap capacitor CB Charging is prevented, the bootstrap voltage remains on one for a relatively long time good level received.

In a case where the delay circuit CR3 is removed from the arrangement of Fig. 3, the MISFET becomes Q31 brought into the "off" state as soon as the drain output of MISFET Q37 goes low. Hence it will difficult to set a suitable time period for charging the bootstrap capacitor CB. Not enough there Charges are stored in the bootstrap capacitor CB, it becomes impossible to have a bootstrap voltage with a sufficient one To apply levels to the gate electrodes of the MISFETs Q30 and Q33. As a result, it becomes difficult to use the output MISFET Q3O and the MISFET Q33 satisfactory in to bring the "on" state.

The circuit arrangement of FIG. 3 can be replaced by an arrangement in which the drain output of the MISFET Q33 together via a delay circuit Gates of the MISFETs Q31 and Q32 is supplied. However, there are the following problems. Since the switching process of the MISFET Q32 is delayed by a delay time, the time for the generation of the decoding signal dcr1 not be accelerated. Furthermore, the output MISFETs Q3O and Q32 are turned on simultaneously for a period of time approximately is equal to the delay time of the delay circuit, held in the "on" state. As a result, flows over a a comparatively large through current to the output MISFETs Q30 and Q32 for a comparatively long time.

In the circuit of FIG. 3, the voltage of the supply voltage connection is applied to the gate of the isolating MISFET Q26 Vcc applied. Therefore, during chip nonselection, a direct current flows to the load MISFET Q21, the isolation MISFET Q26 and the MISFET Q27 of the decoding part. If during The internal control signal ce can be sent to the gate of the isolating MISFET Q26 can be created. Although not shown, a practical embodiment of the address decoding part DCR2 can be constructed similarly to the circuit of the address decoding part DCR1 of FIG.

However, the unit circuit constituting the address decoding part DCR2 is different from that shown in FIG The circuit differs in two respects, namely in that it is supplied with the address signals of the middle two bits and that it is not provided with MISFETs that the MISFETs Q38 and Q41 correspond.

Accordingly, the signal with the non-inverted receives Levels such as the signal dcr2 supplied by the address decoding part DCR2 in the mode of operation of the Reading out data the selection level, which is substantially equal to the supply voltage Vcc, or the non-selection level, which is substantially equal to the ground potential; in the case of the registered operation or the verify operation

it receives the selection level lying in the vicinity of 7 volts or that essentially in the vicinity of the ground potential lying non-selection level. The signal with the inverted level such as the signal dcr2 receives the selection level, which is substantially equal to the ground potential, or the nonselection level which is substantially the same (Vcc - Vth), where Vth is the threshold voltage of the MISFET, e.g., MISFET Q39 in FIG.

The MISFET such as the transmission gate MISFET QT, which corresponds to the word line to be selected, is advantageously set to the "on" state even in the verify mode of operation, because the output signal of the address decoding part DCR2 assumes the level corresponding to the description above.

In order to make the threshold voltage of the isolating MISFET Q29 smaller than that of the address decoding parts DCR1 and DCR2 Making output MISFET Q3Ö becomes the 'short channel effect' used, but "is not limited to this."

This means that the MISFET Q29 has a smaller channel length possesses as the output MISFET Q3O. In this case, the relationship between the magnitudes of the threshold voltages the MiSfETs of different channel lengths are not significantly due to variations in the manufacturing process of an IC influenced. Accordingly, the gate voltage of a MISFET such as the output MISFET Q30 becomes an appropriate one Level held by another MISFET such as MISFET Q29. The method of using the "short channel effect" has the advantage that the number of steps in the manufacturing process of the IC need not be increased.

The operation of the EPROM of FIGS. 1 to 3 described.

A FAMOS transistor used as a storage element is in a state in which the information is erased is a comparatively low threshold voltage of, for example, + 2 volts, i.e. in a state in which in the floating gate of the FAMOS essentially no charge is stored. The FAMOS transistor has a comparative

wise high threshold voltage of e.g. +7 volts or higher in a state in which information is written, i.e. in which charges are stored in the floating gate.

The writing of data into the FAMOS transistor is carried out as described below. A high writing voltage tens of volts or more is generated by the read / write circuit and to the bit line through the CSW to which the memory element to be selected is connected. Simultaneously, a signal is sent with a high level of e.g. 25 volts from the X-DCR to the word line to be selected applied. Because of these tensions, selections will be made in the vicinity of the drainage area FAMOS transistor created by the high drain voltage and the channel current hot electrons. The hot electrons flow into the floating gate through the gate insulating film. In unselected FAMOS transistors, their drain electrodes are connected to the selected bit line, no data is written because the corresponding Word lines are held at the low level, the nonselection level, which is approximately equal to 0 volts.

When information is read out from the memory element, the selected word line receives one between one low threshold voltage and a higher threshold voltage of the storage element lying level, so a level that is approximately equal to the supply voltage Vcc while the unselected word lines have an unselected level of about 0 volts. When information is read out, the selected memory element therefore falls into the "on" state or the "off" state in accordance with the lower threshold voltage that was previously generated by the written data was determined.

The verify operation will now be described in the following. A high voltage is generated in the verify operation of e.g. +25 volts is applied to the connection Vpp for the high write-in voltage.

It is now assumed that certain signals of the internal address signals a1 to a8 are at the low level.

have taken such that the word line W1 shown in Fig. 2 is selected. In this case, the decoding signal dcr1 of the address decoding part DCR1 shown in Fig. 2 brought to a high level of about 7 volts, while the Decoding signal dcr1 has a low level of approximately the ground potential accepts. The decoding signal dcr2 of the address decoding part DCR2 receives a high level of about 7 volts, while the decoding signal dcr2 is given a low level of approximately the ground potential.

The load MISFET Q1 in Fig. 2 is brought into the "on" state by the decode signal dcr1 of high level. A voltage of approximately 5 volts, which is approximately equal to the level of the supply voltage Vcc, is applied to the drain electrode of the MISFET Q2 via the MISFET Q1. By the low level of the decoding signal dcr1 and the low level of the address signals a6 to a8, the MISFETs Q3 to QS are brought into the "off" state, with the result that the decoding signal

dcr3 goes high around 5 volts. The transmission gate MISFET Q7 is brought into the "off" state because the decoding signal dcr2 has assumed a high level of about 7 volts. Accordingly, the decoding signal dcr3 becomes about 5 volts the output electrode of the transmission MISFET Q7. Verify operation is determined, for example, by that the external connections PRG and OE assume the high and the low level. With the Verify operation, the internal control signal we have a high level of, for example, 5 volts, which is equal to the voltage of the voltage supply connection Vcc is. The depletion type MISFETs Q15 and Q18 are brought into the "on" states by the high level internal control signal we. As a result the decoding signal dcr3 transmitted to the output electrode of the transmission gate MISFET Q7 via the Depletion MISFET Q15 is further transferred to word line W1.

When the high level of the decoding signal dcr2 is approximately equal to the high level of the decoding signal dcr3, so becomes the selected word line W1 in the verify operation

placed at a high level of about 25 volts in accordance with the write-in voltage applied to terminal Vpp, as described below.

The input electrode of the transmission gate MISFET Q7 works as a source electrode. The transmission gate MISFET Q7 is essentially brought into the "off" state because the level difference between the decoding signal dcr3 applied to its source electrode and that applied to its gate electrode applied decoding signal der2 is small. As a result, will the voltage applied to the word line W1 is raised by the MISFET Q19 to a voltage which is essentially is equal to the voltage applied to the terminal Vpp.

If each unit circuit constituting the decoding part DCR2 is similar to the above-described circuit of FIG is constructed, the decoding signal dcr2 has a high level of a sufficiently large voltage. The transmission gate MISFET Q7 is advantageously determined by the decoding signal dcr2 applied to its gate electrode from brought high voltage into the "on" state. As a result, the word line W1 to be selected can be set to the desired one Value of about + 5 volts can be placed.

Word lines other than the word line W1 (i.e., the unselected word lines) are each given one low level, which is approximately equal to the ground potential, because the MISFETs Q10, Q12, Q14 etc. by the inverted signal of the address decoding part DCR2 are brought into the "on" state. -

In the writing process, the levels of the respective word lines are set as described below.

If the word line W1 is to be selected, the Transfer gate MISFET Q7 turned "on" as described above. As a result, the Transfer gate MISFET Q7 to the source of the depletion type transfer gate MISFET Q15 the decode signal der3 applied with about + 5 volts. The gate electrode of the transmission gate MISFET Q15 is through the internal Control signal we held at about 0 volts. Accordingly

For example, transmission gate MISFET Q15 is driven "off" because its gate potential equals about minus 5 volts when its source is considered to be at about 0 volts.
The MISFET Q19 serving as a high resistance is located between the word line W1 and the terminal Vpp. When the transmission gate MISFET Q15 is turned "off", the word line W1 is at about 25 volts because of the voltage supplied from the terminal Vpp through the load MISFET Q19. In contrast, the unselected word lines are at a low level approximately equal to the ground potential because, similar to the description above, the MISFETs Q10, Q12, OJ4, etc. are brought into the "on" state, whereby the transmission gate MISFETs Q16 to Q18 in FIG be brought to the "on" state. During the read-out process, the connection Vpp receives a voltage of approximately 5 volts for the high write-in voltage.

The enhancement type MISFET Q34 forming the voltage dividing circuit shown in FIG the connection Vpp is set to + 5 volts, brought into the "off" state. As a result, MISFET Q34 cannot take harmful effect on the readout process.

Since this.-Ausfühirungsbeispiel the decoder parts have a circuit structure corresponding to FIGS. 2 and 3, the writing depth of information in the memory element or the threshold voltage of the storage element can be determined in accordance with the description below.

To set the threshold voltage, the connection Vpp for the high write-in voltage is first of all in agreement with the threshold voltage level to be determined, for example of +12 volts. Below are the Read out data of the associated memory elements in the verify mode of operation. The ones supplied to the output port I / O Data signals are compared with expected values. During operation to determine the threshold voltage supplies the voltage divider circuit, which divides the voltage falling across the terminals Vpp and Vcc, one opposite

the mentioned voltage of + 7 volts lower divided Voltage because the voltage of the terminal Vpp a comparatively receives a low value of, for example, +12 volts. Lowering the shared voltage results in a Decrease in the high level of the decoding signals supplied from the decoding part DCR2. The Transmission Gate MISFETsQ7, Q9, Q11, Q13 etc. cannot be in the "On" state occurs even when high level signals are supplied from the decoding part DCR2. Accordingly, will the word line to be selected, for example the word line W1, is brought into coincidence with a voltage that corresponds to that of the Connection Vpp is the same, i.e. the determination level. The unselected word lines are given a low level, which has about ground potential., because the respectively assigned MISFETs QIO, Q12, Q14 etc. are affected by the output signals of the Decoding part DCR2 are brought into the "on" state,

The storage element having a higher threshold voltage is essentially not brought into the "on" state, even if a voltage with the determination level at its Gate electrode is applied. Accordingly, by taking into account of the data signal supplied to the external output terminal I / O, it can be determined whether the threshold voltage of each storage element greater than the voltage of the Connection is Vpp.

The in FIGS. The circuits shown in FIGS. 1 to 3 can be modified.

For example, the voltage divider circuit can be modified in various ways including an embodiment where it consists only of resistances. Furthermore, an embodiment of the X-DCR can be any circuit, those for the formation of the word line signals in an output stage transmission gate MISFETs of the enhancement type used. Furthermore, a voltage clamping device such as the MISFET Q29 can also be a device that uses a Diode or the like used.

Fig. 4 shows an embodiment of a control circuit, which forms the internal control signals ce and ce with appropriate levels when coming from an external terminal

CO receives the control signal.

The circuit of FIG. 4 consists of a first circuit PC which essentially consists of a push-pull circuit constructed, and from a second circuit BC, which is constructed from a push-pull circuit with a bootstrap circuit is.

The signal waveforms appearing at the various nodes in the circuit of the figure are shown in FIG. shown. The symbols added to the signal waveforms of FIG. 5 correspond to the nodes indicated in FIG .

First, the second circuit BC will be explained. These second circuit BC has an enhancement MISFET E5, at the gate of which the output signal of the first circuit PC is present, it also contains a depletion MISFET D3, an isolation MISFET E6, a depletion MISFET D4, a Enrichment MISFET E7, a bootstrap capacitor CB, Enhancement MISFETs E8, E9, E10 and E11 and a delay circuit CR2.

The MISFETs E5 and D3 form an inverter circuit. In a corresponding manner, the MISFETs E7 and D4 form an inverter circuit. The MISFETs E10 and E11 form a push-pull output stage .

As shown in the figure, there is a delay circuit CR2 consists of a resistor R2 and capacitors CS3 and CS4, and it is between the gate electrode of MISFET E11 and the gate electrode of MISFET E9.

The isolation MISFET E6 is provided to electrically isolate a node E and a node H from each other when the voltage level of the node H has been raised above the supply voltage Vcc. Because the isolating MISFET E6 is provided is, the charges stored in the bootstrap capacitor CB can be prevented from being undesirably Way to be discharged (drained).

The operation of the second circuit BC will now be described.

If a node D is on one of the ground potential in the lower

MISFET E5 is kept in the "off" state. The "off" state of MISFET E5 brings node E high, the is substantially equal to the supply voltage Vcc. The node H gets in accordance with the high level of the node E has a high level. Node F is held low because MISFET E7 is high of the node E is kept in the "on" state. Similar to the node F, a node G is kept low. Since node H is held at a high level and node F is held at a low level, the output from the MISFETs provides E10 and E11 existing push-pull output stage an output signal ce high level.

In the case where the node D is at a level substantially equal to the level of the power supply voltage Vcc is held, the output signal of the push-pull stage has a depth substantially equal to the ground potential Level because the MISFETs E1O and Ε1Ί in the "off" or. the "on" state can be brought.

The bootstrap capacitor CB is used in a comparative short period then charged when the node E has been set from low to high.

In particular, if the node E is kept at a low level, because of the high level at the node G, the MISFET E9 held in the "on" state. Because the MISFET E9 is held in the "on" state, a node I becomes on a the ground potential is kept substantially the same, low level. Since the gate electrode of the isolation MISFET E6 is on the Supply voltage Vcc is held, it remains in the "on" state as long as that of its input and output electrodes, operating as the source electrode is held at a value lower than (Vcc - Vth), where Vth denotes the threshold voltage of the MISFET E6. Accordingly, the bootstrap capacitor becomes via the MISFETs E6 and E5 unload.

When the node E from the low level to one of the Supply voltage essentially the same high level

has been brought, the node H accordingly receives a high level. The node I is given a high level by the fact that the MISFET E9, which was in the "on" state, in the "Off" state is brought. Accordingly, the bootstrap capacitor CB is charged in a period after the node E goes high and before the MISFET E9 goes into the "off" state.

When the MISFET E9 has been brought into the "off" state is, the node I assumes the high level via the MISFET E8. The node H receives an above supply voltage Vcc lying potential through the previously charged bootstrap capacitor CB. Since the potential of the node H increases above the supply voltage, the output MISFET E10 assumes a sufficiently low "on" resistance.

Since the potential of the gate electrode of the MISFET E1O via the Supply voltage Vcc is raised, it is advantageously brought into the "on" state even when the Potential of an output terminal OUT has essentially reached the supply voltage Vcc. Hence it is possible to send a signal of high speed and sufficient level to a capacitive load, not shown which is connected to the output terminal OUT.

The charging rate of the bootstrap capacitor CB is determined by the "on" resistors of the MISFETs D3, E6 and E9 limited. If the delay circuit CR2 is omitted in the second circuit BC shown in FIG. 4 ', so the MISFET E9 becomes within a comparatively short time after the node E has assumed the high level, brought into the "off" state. As a result, it becomes difficult to use in the bootstrap capacitor CB a sufficient number of to make stored charges available. If the bootstrap capacitor CB is insufficiently charged difficult to raise the bootstrap voltage enough. In that, in the embodiment, the delay circuit CR2 is provided, on the other hand, the signal applied to the MISFET E9 becomes sufficient Measure delayed compared to the signal at node E.

Accordingly, as shown in FIG. 5, the MISFET E9 can be kept in the "on" state for a period of time after the MISFET E11 has fallen into the "off" state. This becomes the time period t _ during which the node H is high with respect to node I, long in the circuit of FIG. 3, so that in the bootstrap capacitor CB stored amount of charge becomes large. As a result, when the MISFET E9 is from the "on" state has switched to the "off" state, the level of the node H is kept sufficiently high and it becomes possible to apply a sufficiently high voltage to the gate electrode of the MISFET E1O. Therefore, the Steilhet gm des MISFET E10 is sufficiently large that the drive capacity for the load is increased.

The first circuit PC will now be described, which as Pre-stage circuit for the second circuit BC is constructed.

The first circuit PC has an inverter circuit which has an enhancement driver MISFET E1, its gate electrode is connected to the input node IN, and a depletion load M-ISFET D1, which is connected to the MISFET E1 connected; the first circuit PC further comprises a An inverter circuit comprising an enhancement driver MISFET E2 and a depletion load MISFET D2, furthermore one Push-pull output circuit consisting of enhancement MISFETs E3 and E4, and finally a delay circuit CR1. Without being limited to this, the delay circuit exists CR1 consists of a resistor R1 and capacitors CS1 and CS2, it is between the gate electrode of the MISFET E2 and the gate electrode of MISFET E4 switched.

By properly setting the values of the resistor R1 and the capacitors CS1 and CS2, the delay circuit becomes CR1 is provided with a delay characteristic substantially equal to the characteristic of the inverter circuit formed from the MISFETs D2 and E2. As will be described below, the Delay circuit CR1 the power consumption of the push-pull circuit PC reduced. Furthermore, the

delay circuit CR1 the generation of interference and noise in the circuit. When the entire circuit of the 4 is designed as an integrated circuit, this circuit and other circuits based on built on the same chip, stable with a comparatively small voltage source can be operated. Better the reason why the delay circuit CR1 is used To understand, the operation of the circuit will first be described in the case where the delay circuit CR1 does not exist.

An output signal given from the inverter circuit composed of the MISFETs D2 and E2 is passed through delays the parasitic capacitances which are coupled to its output terminal and which the Dra.Lncapacitance of the MISFET E2, the source capacitance of the MISFET D2, the gate capacitance of the MISFET E3 and the conductor path capacitances (from this is not shown in the figure).

If the delay circuit CR1 is not present, thus, an inverted signal which is transmitted to a node C by the inverter circuit formed by the MIS-FETs D2 and E2 is supplied, delayed relative to a signal that a Node B is supplied, or a signal which is supplied to a node A. The signal delay increases accordingly indicates the tenting period during which nodes B and C are simultaneously above the threshold values of the MISFETs. this leads to the following problems:

(i) the time period during which both the MISFET E3 how the MISFET E4 are in the "on" state rises, and a through current flows into these MISFETs E3 and E4. That The control signal ce formed by the MISFETs E3 and E4 is common to a plurality of circuits in accordance with FIG. 3 fed. These plurality of circuits have a large input capacitance as a whole even if the input capacitance of each of them is comparatively small.

As a result, a comparatively large capacitive load is applied to the output terminal of the MISFETs E3 and E4 Push-pull output circuit connected. the end

for this reason, the MISFETs E3 and E4 are given comparatively large dimensions so that a comparatively large current can flow to the output node D.

As a result, the through current flowing through the series-connected MISFETs E3 and E4 decreases in comparison to those currents flowing through the other inverter circuits, etc., a comparatively high value. The aforementioned through current increases the power consumption of the EPROM relatively strongly.

(ii) In the case of an integrated semiconductor circuit, the supply voltage lines have on the semiconductor substrate are formed, such as the supply voltage conductor layer / connection line for a Voltage source and the feed for a voltage source Resistance components and inductance components that are not are negligible. Furthermore, the wiring of the power supply creates undesirable coupling capacities with different signal trace layers of the circuit. The through current that occurs in the transition period of a Signal change flowing to the serially connected MISFETs E3 and E4, caused in the power supply lines relatively large changes in potential, which are to be regarded as disturbances. In the case of an integrated semiconductor circuit a large number of circuits are connected to an identical supply voltage line. Accordingly changes in potential on the supply voltage line are sent directly to various circuits (not shown) transfer. The various circuits are prone to malfunctions, since their reference potential is caused by a change in potential is changed on the supply voltage line.

A fluctuating potential of the supply voltage line leads further because of the undesirable effects mentioned above Coupling capacitances to an undesired change in potential on the signal line, which is to be regarded as a disturbance. For example a capacitive coupling occurs between the positive supply voltage line Vcc and the node E.

4 has a capacity not shown. Therefore, the level of the node E fluctuates in accordance with the fluctuation the level of positive supply voltage attention, and a malfunction or a decrease in the operating speed occurs with this circuit.

(iii) An experiment has shown that when a comparatively large through-current through the series switched MISFETs E3 and E4 flows, the level of the output node D changes as indicated by the solid line Curve NO of Fig. 6 is shown. In view of the fact that the signal level is at about half Level increases within the drop of the output signal shown by the solid curve NO of FIG. 6, could the cause of this cannot be adequately clarified. However, it is believed that rapid changes of positive Side of the supply voltage and the reference potential side of the supply voltage due to the through current and the Inductance components, the capacitance components, etc., which are linked to the supply voltage lines.

If a signal occurs at the output node D which changes in accordance with the solid curve NO in FIG. 6, in any case, the fall time of the signal at this output node is considerably increased with the result, that the operating speed of the EPROM is limited. In Fig. 6, the level of the threshold voltage Vth for the in Fig. 3 shown circuit to which the signal of the output node D is applied, by the dash-dotted line Line indicated.

On the other hand, when the delay circuit CR1 is provided with the delay characteristic described above the problems described above are solved.

If the level of the node A according to the representation B of FIG. 5 from the low level to the high Level is set, the signal at the node C responds to it and becomes according to the representation C of FIG after a delay determined by the inverter (D2, E2)

time is lower than the threshold voltage Vth of the MISFET E3. On the other hand, the signal at the node B becomes one Time adjustment with respect to the signal of the node A as shown in FIG. 5, because the delay circuit CR1 is present. That is, the time period in which the signal at the node B is higher than the threshold voltage Vth of the MISFET E4 is equal to the time period in which the signal of the node C is lower than the threshold voltage Vth of the MISFET E3. As a result, a period of time is prevented from occurring during which the MISFETs E3 and E4 are simultaneously in the "on" state, whereby the flowing through the MISFETs E3 and E4 Through current is reduced remarkably. In this case, the signal at node D falls within one a comparatively short time, as shown by the dashed line N1 in FIG.

As a result, the EPROM can be operated at a comparatively high speed.

In contrast to the above case, when the level of node A is set from high level to low level, Because of the presence of the delay circuit CR1, a period of time may occur during which Both node B and node C go high. However, such a period of time can be substantially reduced to one negligible value can be abbreviated by putting the MISFET D2 in the inverter (B2, E2) an appropriate size receives. '

Specifically, when the level of the node A is switched from a high level to a low level, so the driver MISFET E2 responds to this and falls into the "off" state, and consequently the level of the node rises C from the low level to the high level. In this case, the slew rate for the signal level of node C is determined by the characteristics of the load MISFET D2 and the parasitic capacitances, for example the gate capacitance of the MISFET E3, which is essentially coupled to the node C. Therefore, the

The rise time of the signal level of the node C can be appropriately set by making the load MISFET D2 an appropriate dimension. The time period during which the signal at the node C assumes at least the threshold voltage Vth of the MISFET E3 is appropriately determined relative to the time period during which the signal of the node B does not become higher than the threshold voltage of the MISFET E4, whereby according to the illustration F. 5, the time period t ₁ during which the MISFET E3 and E4 are simultaneously in the "on" state can be shortened. Accordingly, the through current is given a comparatively small value, as indicated by ID in illustration F of the figure.

In the circuit of FIG. 4, the delay circuit CR1 can be modified into a circuit in which two with no other degree of inverter circuits, all of which are made up of MISFETs D2 and E1, connected in series are. Even in such a case, according to the above finding, the through current can be substantially reduced to one negligible value can be brought by the dimension of the (not shown) MISFElT of the inverter circuit is set appropriately for the signal delay.

Suitable structures are in accordance with the present invention for the "switching elements which form the push-pull circuit and the delay circuit.

FIG. 7 shows a plan view of the switching elements which form the first circuit PC in the circuit of FIG. 4; FIG. 8 shows a section through a semiconductor substrate along part AA ¹ of FIG. 7.

Without being particularly restricted to this, those in FIGS. 7 and 8 shown switching elements with the known technique of selective oxidation, the technique of so-called self-alignment, in which a polycrystalline silicon layer, which is used as a conductor track or as the gate electrode of a MISFET, as a mask is used when introducing the dopant. The MISFETs are of the n-channel type, they are made in a p-type silicon

substrate formed.

In Fig. 7, patterns of semiconductor regions such as the drain regions and the source regions of the MISFETs are through dash-dotted lines provided with two dots indicated, and the patterns of polycrystalline silicon layers, which are used as gate electrodes and conductor track layers of the MISFETs are indicated with dashed lines. Pattern of conductor track layers made from vapor-deposited aluminum layers exist are indicated with solid lines. The channel regions of MISFETs are through to the right ascending hatching indicated. The contact parts between the conductor track layers and the semiconductor areas and those between the conductor layers and the polycrystalline silicon layers are made up of square patterns added x-signs indicated.

The main surface of a semiconductor substrate 1 that consists of a p-type silicon single crystal is coated with a comparatively thick field oxide film 2, the is formed by local oxidation with a thickness of, for example, 1 μm. Those parts of the main surface de's semiconductor substrate 1 that is not covered with the field oxide film 2 are covered, are used as active areas for the formation of the switching elements or as semiconductor conductor track areas. On the active areas of the semiconductor substrate 1 is a for the conductor track layers or gate electrodes polycrystalline silicon layer 3 formed over a comparatively thin gate oxide film. If necessary, extends the polycrystalline silicon layer 3 is also on the field oxide film 2. On the one to be provided with the active areas The surfaces of the semiconductor substrate 1 are in parts that are not covered with the polycrystalline silicon layer 3 are, with η-like semiconductor regions for the formation of the source and drain regions of the MISFETs or the semiconductor conductor track regions educated. On the main surface of the semiconductor substrate 1 and also on the polycrystalline Silicon layer 3, an insulation film 4 is also applied as an interlayer insulator, which is made of phosphorus silicon

katglass consists. A conductor track layer lies on the insulation film 4 for the power supply lines or signal lines, which are made of vapor-deposited aluminum.

In Fig. 7, there is the MISFET such as the MISFET D1 an η-like semiconductor region RG1 as a drain region, an η-like semiconductor region RG2 as a source region, and an η-like polycrystalline silicon layer PS1 as Gate electrode formed over a channel region enclosed between regions RG1 and RG2.

In Fig. 7, the drain region RG1 is the MISFET D1 connected to the interconnect layer ME1, which is supplied with the supply voltage Vcc, while the source region of the MISFET E1 is connected to a conductor track layer ME2, which is held at the reference potential GND. That common semiconductor region RG2, which serves as the source region of the MISFET D1 and as the drain region of the MISFET E1, is over a conductor track layer ME1 with an end part as a gate electrode of the MISFET D1 serving polycrystalline silicon layer PS1 connected.

The other end of the gate electrode PS1 is the MISFET D1 via a conductor layer ME4 with an end part of a polycrystalline silicon layer connected, which forms the gate electrode of the inverter circuit of the following stages Driver MISFET E2 is. The respective drain region and the source region of the MISFETs E2 and D2 consist of a common one Semiconductor area. This common semiconductor region is connected to the gate electrode via a conductor track layer of the MISFET D2 forming polycrystalline silicon layer connected. According to the figure, the other end part hangs the polycrystalline silicon layer, which forms the gate electrode of the MISFET E2, with a polycrystalline Silicon layer, which forms the gate electrode of the MISFET E4, with which the push-pull output circuit is constructed. Similarly, the other end part is the polycrystalline silicon layer which is the gate electrode of the MISFET D2, formed contiguously with a polycrystalline silicon layer, which forms the gate electrode

of the MISFET E3. In the structure of the switching elements shown in Fig. 7, a delay circuit is constructed, which takes advantage of the fact that the polycrystalline silicon layer in comparison with layers of metal like for example, aluminum is large, such as the fact that when a thin insulating film such as the gate insulating film is used as an insulation film, a comparatively large capacitance between the polycrystalline silicon layer and the semiconductor substrate 1 or between the polycrystalline Silicon layer and the source region of the MISFET is formed. This means that the delay circuit im is essentially built up with the polycrystalline silicon layer forming the gate electrode of the MISFET E2.

According to the structure of Fig. 7, as described above, the delay circuit is essentially comprised of the MISFET E2 educated. Therefore, despite the presence of the delay circuit, the required area of the semiconductor substrate becomes not enlarged.

FIG. 9 shows a plan view of the switching elements which form the second circuit BC in FIG. 4. The section AA ¹ through the MISFET E11 is essentially the same as that of FIG. 8.

The bootstrap capacitor consists of an n-type semiconductor area that is connected to the drain area of the MISFET E9, and a polycrystalline silicon layer formed on a thin gate oxide film thereover. the polycrystalline silicon layer serves as an electrode of the bootstrap capacitor and is over a conductor layer connected to the gate electrodes of the MISFETs E8 and E10.

In the figure there is an η-like polycrystalline silicon layer PS3 as the gate electrode of the MISFET D4 directly with a an η-type polycrystalline silicon layer PS4 which forms a conductor path and extends on the field oxide film 2. This η-like polycrystalline silicon layer PS4 is directly at one end of an η-like polycrystalline silicon layer PS5, which forms the gate electrode of the output MISFET E11. The other end of the η-like polycrystalline

PS5 silicon layer is over a vapor-deposited aluminum existing conductor layer ME5 to an η-like polycrystalline silicon layer forming the gate electrode of the MISPET E9 PS6 connected.

According to the construction shown, the stray capacitance receives the between the n-type polycrystalline silicon layer PS4 forming the conductor track and the semiconductor substrate 1 is formed, a comparatively small capacitance value, because according to the above description of the field oxide film is comparatively thick. Accordingly, the time constant given by the resistance value of the n-type polycrystalline silicon layer PS4 itself and determined by the stray capacitance, a relatively small one Value.

In contrast, the stray capacitance obtained by the η-type polycrystalline silicon layer PS5 which forms the gate electrode of the output MISFET G11, and of the semiconductor substrate 1 has a relatively large capacitance value because the gate oxide film is thin and because, as shown in the figure, the output MISFET E11 has comparatively large dimensions. Accordingly receives the time constant which is determined by the resistance of the η-type polycrystalline silicon layer PS5 itself and is determined by the stray capacitor, a relatively large value.

As a result, the delayed signal supplied to the MISFET E9 is essentially passed through the gate electrode of the MISFET E11.

FIG. 10 shows a circuit diagram of a further exemplary embodiment of the delay circuit. With this one Embodiment, two inverter circuits each consist of combinations of a depletion MISFET D5 and one Enrichment MISFETs E12 and MISFETs D6 and E13, the are connected in cascade. The number of inverter circuits can also be one of two different even numbers, one an even number is selected to make the input IN and the output OUT in phase.

-ί as ":

11 shows in a cross section a further exemplary embodiment for a delay circuit.

In this exemplary embodiment, an n-type polycrystalline silicon layer 3, which is used as a conductor track, runs on a comparatively thin insulation film 2 '. For example, the insulation film 2 ^{1 is formed} simultaneously with the gate insulation films of the MISFETs. Since the insulating film 2 'is comparatively thin, a comparatively large stray capacitance is formed by the polycrystalline silicon layer 3 and the semiconductor substrate 1, similarly to the gate electrode of the MISFET E11. Accordingly, the delay circuit is formed by the resistance of the polycrystalline silicon layer 3 itself and by the stray capacitance.

12 shows a cross section through a delay device of another embodiment. The section through the delay device of this embodiment is similar to that through a depletion MISFET. In detail, an η-like polycrystalline silicon layer 3 extends on a thin insulating film 2 '. In the surface a p-type semiconductor substrate 1, which is under the Insulation film 2 'lies, a depletion region RG12 is formed. The area RG12 is provided with η-like areas RG10 and RG11, which are simultaneously with the drain area and the source area of a MISFET. The depletion region RG12 is over the semiconductor regions RG1O and RG11 on the Ground potential of the circuit held.

Accordingly, the delay circuit consists essentially of the polycrystalline silicon layer 3.

The delay device of the embodiment shown in Fig. 12 has the advantage described below.

In the case of the delay devices shown in FIGS. 7 to 9, which are connected to the gate electrodes of the enrichment MISFETs are formed, the stray capacitance coupled to the gate electrode decreases as the capacitance to the gate electrodes increases applied signal level, similar to a typical

MOS capacitor.

On the other hand, in the delay device shown in FIG the electric field exerted by the polycrystalline silicon layer on the depletion region RG12 is exercised, positive. Accordingly, in the surface of the depletion region RG12, despite the increase in the polycrystalline silicon layer 3 applied signal level does not induce a depletion layer. Because in the impoverished area RG12, no depletion layer is induced, the stray capacitance coupled to the polycrystalline silicon layer 3 becomes not changed. As a result, the delay characteristic of the delay device shown in Fig. 12 becomes not affected by the signal level.

Fig. 13 shows another embodiment of a Delay device. In this embodiment, the delay means consists of the resistor between Source and drain of a depletion MISFET with its gate connected to the Ground point is connected / and from the capacitance existing between the resistor and the ground point.

The delay circuit CR1 of the push-pull circuit Pc. can also consist of an Aaa fuse MISFET E14 and a capacitor CS5, as shown in FIG.

In the circuits of FIGS. 11 to 13 will be the thin one Insulation film, which is formed simultaneously with the gate insulation film of the MISFET, is used for the formation of the capacitance . Accordingly, these circuits have the advantage that the delay circuit is remarkably small Area can be occupied and manufactured without a special, additional manufacturing step is necessary.

The invention can also use delay circuits other than the delay circuits described above insert.

As described above, according to the invention, the drive capability for a load can be increased and the occupied area will be reduced.

RS / CG

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Claims (19)

SHIP ν. FÜNER STREHL SCHÜBEL-HOPF EBBINGHAUS FINCK MARIAHILFPLATZ 2 A 3, MÖNCHEN 90 POST ADDRESS: POST BOX Θ5 O1 6O, D-8OOO MUNICH Θ5 HITACHI, LTD. - May 28, 1982 DEA-25 664 ELECTRONIC CIRCUIT ARRANGEMENT PATENT CLAIMS 1 Λ Electronic circuit arrangement, characterized by a first node to which an input signal
is created, an inverter circuit which provides an output signal related to the applied to the first node Input signal is inverted, a delay device which supplies a delay signal related to the to the first node applied input signal is delayed, an exit node, a first MISFET whose drain-source path between a voltage supply connection and the output node is connected, and the output signal is connected to its gate electrode the inverter circuit is applied, and by a second MISFET with its drain-source path between an output node and the other terminal of the supply voltage is connected, and to its gate electrode the delayed signal is applied. 2. Electronic circuit arrangement according to claim 1, characterized in that the delay device from a resistance element and a capacitance element is constructed, and that the resistance element and the capacitance element each with the gate electrode of one MISPET or with the stray capacitance coupled to the gate electrode is formed. 3. Electronic circuit arrangement according to claim 1, characterized in that the delay device a polycrystalline silicon layer, which over a semiconductor substrate on a comparatively thin insulating film is formed. 4. Electronic circuit arrangement according to claim 1, characterized in that the delay device a semiconductor region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type, and which is at the potential of a other terminal of the voltage source is held, and has a polycrystalline silicon layer, which on a comparatively thin insulation film over the semiconductor area is formed. 5. Electronic circuit arrangement according to claim 1, characterized in that the delay device with the drain-source path of a depletion MISFET is formed. 6. Electronic circuit arrangement according to claim 5, characterized in that the gate electrode of the depletion MISFET is held at the potential of one terminal of the supply voltage source. . 7. Electronic circuit arrangement according to claim 1, characterized in that the delay device is formed with an even number of signal inverting devices connected in cascade. 8. Electronic circuit arrangement according to claim 1, characterized in that the inverter circuit is formed with a driver MISFET having a drain electrode, a source electrode and a gate electrode to which the input signal is applied, and a load MISFET which is connected to the drain electrode of the driver MISFET is connected, and that the delay device is a resistance element which is substantially connected to the Gate electrode of the load MISFET is formed, and has a stray capacitance that is applied to the gate electrode of the load MISFET connected. 9. Electronic circuit arrangement, g e k e η η - is characterized by a first circuit, which is a signal inverter circuit, a first output node for outputting a first signal / a second output node for delivering a second signal with one opposite to the first Signal has inverted level, a bootstrap circuit, which first and second MISFETs, their drain electrodes and scjurce electrodes in series between a pair of power supply terminals are connected and a bootstrap capacitor connected between the gate electrode and the source electrode of the first MISFET are connected, a connection device which applies the first signal to the gate electrode of the first MISFET, and through a delay device which sends the second signal to the gate electrode with a predetermined delay time a second MISFET applies. 10. Electronic circuit arrangement according to claim 9, characterized in that the coupling device a third MISFET having its drain and source in series between the first output node and the gate electrode of the first MISFET are connected. 11. Electronic circuit arrangement according to claim 10, characterized in that the gate electrode the supply voltage of the third MISFET is laying. 12. Electronic circuit arrangement according to claim 10, characterized in that the delay device is constructed from a resistance element and a capacitance element, the resistance element and the capacitance element in each case with the gate electrode of a MISFET or with one coupled to the gate electrode Stray capacitance are formed. 13. Electronic circuit arrangement according to claim 10, characterized in that the delay device has a polycrystalline silicon layer which is arranged on a comparatively thin insulating film over the semiconductor substrate. 14. Electronic circuit arrangement according to claim 10, characterized in that the delay device a semiconductor region of a second conductivity type, which on the semiconductor substrate of a first conductivity type is formed, and that on the potential of the other connection of the supply voltage source is held, and that the delay device comprises a polycrystalline silicon layer, which is formed on a comparatively thin insulating film over the semiconductor region. 15. Electronic circuit arrangement according to claim 10, characterized in that the delay device comprises the drain-source path of a depletion MISFET. 16. Electronic circuit arrangement according to claim 15, characterized in that the gate electrode of the depletion MISFET at the potential of one Connection of the supply voltage is maintained. 17. Electronic circuit arrangement according to claim 10, characterized in that the delay device has an even number of signal inverters, which are connected in cascade. 18. Electronic circuit arrangement according to claim 10, characterized in that a push-pull output circuit is provided which has a fourth MISFET, its drain electrode and source electrode are connected between one of the two supply voltage connections and a third output node, and which has a fifth MISFET whose drain electrode and source electrode between the third output node and the other of the supply voltage connections are switched, wherein the gate electrodes of the first and fourth MISFETs are supplied with the first signal via the coupling device and the gate electrode of the fifth MISFET is supplied with the second signal. 19. Electronic circuit arrangement according to claim 18, characterized in that the delay device has a resistance element and a stray capacitance which is substantially connected to the gate electrode of the fifth MISFET are formed.