DE3177272D1 - Speicherschnittstellensystem. - Google Patents

Speicherschnittstellensystem.

Info

Publication number
DE3177272D1
DE3177272D1 DE8787107092T DE3177272T DE3177272D1 DE 3177272 D1 DE3177272 D1 DE 3177272D1 DE 8787107092 T DE8787107092 T DE 8787107092T DE 3177272 T DE3177272 T DE 3177272T DE 3177272 D1 DE3177272 D1 DE 3177272D1
Authority
DE
Germany
Prior art keywords
memory interface
interface system
memory
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787107092T
Other languages
English (en)
Inventor
Stephen P Hamilton
Arthur C Hunter
Kenneth A Lies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/163,023 external-priority patent/US4443845A/en
Priority claimed from US06/163,238 external-priority patent/US4383184A/en
Priority claimed from US06/163,025 external-priority patent/US4516218A/en
Priority claimed from US06/163,237 external-priority patent/US4503494A/en
Priority claimed from US06/163,024 external-priority patent/US4430724A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE3177272D1 publication Critical patent/DE3177272D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/141—Battery and back-up supplies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Power Engineering (AREA)
  • Power Sources (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Calculators And Similar Devices (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8787107092T 1980-06-26 1981-06-23 Speicherschnittstellensystem. Expired - Lifetime DE3177272D1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US06/163,023 US4443845A (en) 1980-06-26 1980-06-26 Memory system having a common interface
US06/163,238 US4383184A (en) 1980-06-26 1980-06-26 Power controller
US06/163,025 US4516218A (en) 1980-06-26 1980-06-26 Memory system with single command selective sequential accessing of predetermined pluralities of data locations
US06/163,237 US4503494A (en) 1980-06-26 1980-06-26 Non-volatile memory system
US06/163,024 US4430724A (en) 1980-06-26 1980-06-26 Memory interface system having combined command, address and data buss

Publications (1)

Publication Number Publication Date
DE3177272D1 true DE3177272D1 (de) 1992-03-26

Family

ID=27538676

Family Applications (2)

Application Number Title Priority Date Filing Date
DE8787107092T Expired - Lifetime DE3177272D1 (de) 1980-06-26 1981-06-23 Speicherschnittstellensystem.
DE8181302817T Expired - Lifetime DE3177144D1 (de) 1980-06-26 1981-06-23 Datenverarbeitungsspeichersystem.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8181302817T Expired - Lifetime DE3177144D1 (de) 1980-06-26 1981-06-23 Datenverarbeitungsspeichersystem.

Country Status (3)

Country Link
EP (2) EP0043222B1 (de)
JP (2) JPH0242532A (de)
DE (2) DE3177272D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506346A (en) * 1982-12-01 1985-03-19 At&T Bell Laboratories Programmable cartridge telephone communication system
JPS6087001U (ja) * 1983-11-15 1985-06-15 パイオニア株式会社 制御回路のバツクアツプ電源回路
JPS6142235A (ja) * 1984-08-01 1986-02-28 東芝テック株式会社 バツテリ−バツクアツプ回路
US4694395A (en) * 1985-11-25 1987-09-15 Ncr Corporation System for performing virtual look-ahead memory operations
JPH04192047A (ja) * 1990-11-27 1992-07-10 Toshiba Corp パーソナルコンピュータ
KR940007605B1 (ko) * 1991-11-07 1994-08-20 주식회사 금성사 반도체 레이저 다이오드 제조방법
CN112882978B (zh) * 2021-03-02 2023-09-15 北京伟兴彦科技有限公司 一种串行数据传输装置、方法及数据处理设备

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962683A (en) * 1971-08-31 1976-06-08 Max Brown CPU programmable control system
US3821715A (en) * 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer
JPS50139641A (de) * 1974-04-24 1975-11-08
US4007441A (en) * 1975-05-29 1977-02-08 Burroughs Corporation Method of data communications in a heterogenous environment
US4041461A (en) * 1975-07-25 1977-08-09 International Business Machines Corporation Signal analyzer system
US4136400A (en) * 1977-08-08 1979-01-23 Rockwell International Corporation Micro-programmable data terminal
JPS5440342A (en) * 1977-09-05 1979-03-29 Sharp Corp Solar heat collector
US4314353A (en) * 1978-03-09 1982-02-02 Motorola Inc. On chip ram interconnect to MPU bus

Also Published As

Publication number Publication date
JPH056314A (ja) 1993-01-14
EP0253095A3 (en) 1988-08-31
JPH0242532A (ja) 1990-02-13
EP0043222B1 (de) 1990-01-10
EP0253095B1 (de) 1992-02-19
JPH0320779B2 (de) 1991-03-20
EP0043222A2 (de) 1982-01-06
EP0253095A2 (de) 1988-01-20
DE3177144D1 (de) 1990-02-15
JPH0816889B2 (ja) 1996-02-21
EP0043222A3 (en) 1984-10-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition