DE3174802D1 - Method for forming an integrated injection logic circuit - Google Patents

Method for forming an integrated injection logic circuit

Info

Publication number
DE3174802D1
DE3174802D1 DE8181104798T DE3174802T DE3174802D1 DE 3174802 D1 DE3174802 D1 DE 3174802D1 DE 8181104798 T DE8181104798 T DE 8181104798T DE 3174802 T DE3174802 T DE 3174802T DE 3174802 D1 DE3174802 D1 DE 3174802D1
Authority
DE
Germany
Prior art keywords
forming
logic circuit
integrated injection
injection logic
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181104798T
Other languages
German (de)
English (en)
Inventor
Shakir Ahmed Abbas
Ingrid Emese Magdo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3174802D1 publication Critical patent/DE3174802D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/09—Resistor-transistor logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8181104798T 1980-07-08 1981-06-23 Method for forming an integrated injection logic circuit Expired DE3174802D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/167,173 US4322883A (en) 1980-07-08 1980-07-08 Self-aligned metal process for integrated injection logic integrated circuits

Publications (1)

Publication Number Publication Date
DE3174802D1 true DE3174802D1 (en) 1986-07-17

Family

ID=22606253

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181104798T Expired DE3174802D1 (en) 1980-07-08 1981-06-23 Method for forming an integrated injection logic circuit

Country Status (4)

Country Link
US (1) US4322883A (enExample)
EP (1) EP0044426B1 (enExample)
JP (1) JPS5730360A (enExample)
DE (1) DE3174802D1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378630A (en) * 1980-05-05 1983-04-05 International Business Machines Corporation Process for fabricating a high performance PNP and NPN structure
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4378627A (en) * 1980-07-08 1983-04-05 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
JPS5936432B2 (ja) * 1980-08-25 1984-09-04 株式会社東芝 半導体装置の製造方法
US4398338A (en) * 1980-12-24 1983-08-16 Fairchild Camera & Instrument Corp. Fabrication of high speed, nonvolatile, electrically erasable memory cell and system utilizing selective masking, deposition and etching techniques
US4508579A (en) * 1981-03-30 1985-04-02 International Business Machines Corporation Lateral device structures using self-aligned fabrication techniques
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs
US4424621A (en) 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
JPS6046074A (ja) * 1983-08-24 1985-03-12 Toshiba Corp 電界効果トランジスタの製造方法
US4584761A (en) * 1984-05-15 1986-04-29 Digital Equipment Corporation Integrated circuit chip processing techniques and integrated chip produced thereby
JPS61191043A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
FR2579826B1 (fr) * 1985-03-26 1988-04-29 Radiotechnique Compelec Procede de realisation de contacts metalliques d'un transistor, et transistor ainsi obtenu
US4666737A (en) * 1986-02-11 1987-05-19 Harris Corporation Via metallization using metal fillets
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4785337A (en) * 1986-10-17 1988-11-15 International Business Machines Corporation Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts and gate electrodes
GB2219434A (en) * 1988-06-06 1989-12-06 Philips Nv A method of forming a contact in a semiconductor device
JP3489265B2 (ja) * 1995-05-19 2004-01-19 ソニー株式会社 半導体装置の製法
US6902867B2 (en) * 2002-10-02 2005-06-07 Lexmark International, Inc. Ink jet printheads and methods therefor
KR101631165B1 (ko) * 2009-12-14 2016-06-17 삼성전자주식회사 반도체 셀 구조체의 형성방법, 상기 반도체 셀 구조체를 포함하는 반도체 장치의 형성 방법 및 상기 반도체 장치를 포함하는 반도체 모듈의 형성방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643235A (en) * 1968-12-30 1972-02-15 Ibm Monolithic semiconductor memory
US3750268A (en) * 1971-09-10 1973-08-07 Motorola Inc Poly-silicon electrodes for c-igfets
DE2212168C2 (de) * 1972-03-14 1982-10-21 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierte Halbleiteranordnung
DE2262297C2 (de) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau
US3984822A (en) * 1974-12-30 1976-10-05 Intel Corporation Double polycrystalline silicon gate memory device
GB1527894A (en) * 1975-10-15 1978-10-11 Mullard Ltd Methods of manufacturing electronic devices
US4103415A (en) * 1976-12-09 1978-08-01 Fairchild Camera And Instrument Corporation Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
GB2003660A (en) 1977-08-19 1979-03-14 Plessey Co Ltd Deposition of material on a substrate
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4234362A (en) * 1978-11-03 1980-11-18 International Business Machines Corporation Method for forming an insulator between layers of conductive material
US4236294A (en) * 1979-03-16 1980-12-02 International Business Machines Corporation High performance bipolar device and method for making same

Also Published As

Publication number Publication date
US4322883A (en) 1982-04-06
EP0044426A3 (en) 1983-09-14
EP0044426B1 (en) 1986-06-11
EP0044426A2 (en) 1982-01-27
JPS5730360A (en) 1982-02-18
JPS626346B2 (enExample) 1987-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee