DE3174777D1 - Method of fabricating integrated circuit structure - Google Patents

Method of fabricating integrated circuit structure

Info

Publication number
DE3174777D1
DE3174777D1 DE8181401665T DE3174777T DE3174777D1 DE 3174777 D1 DE3174777 D1 DE 3174777D1 DE 8181401665 T DE8181401665 T DE 8181401665T DE 3174777 T DE3174777 T DE 3174777T DE 3174777 D1 DE3174777 D1 DE 3174777D1
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit structure
fabricating integrated
fabricating
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181401665T
Other languages
English (en)
Inventor
Madhukar B Vora
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Application granted granted Critical
Publication of DE3174777D1 publication Critical patent/DE3174777D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
DE8181401665T 1980-10-23 1981-10-22 Method of fabricating integrated circuit structure Expired DE3174777D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US19977180A 1980-10-23 1980-10-23

Publications (1)

Publication Number Publication Date
DE3174777D1 true DE3174777D1 (en) 1986-07-10

Family

ID=22738957

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181401665T Expired DE3174777D1 (en) 1980-10-23 1981-10-22 Method of fabricating integrated circuit structure

Country Status (4)

Country Link
EP (1) EP0052038B1 (de)
JP (1) JPS57100763A (de)
CA (1) CA1179786A (de)
DE (1) DE3174777D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6074477A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd 半導体装置及びその製造方法
EP0137992A3 (de) * 1983-09-29 1987-01-21 Fujitsu Limited Lateraler, bipolarer Transistor hergestellt in einem Silizium-auf-Isolator(SOI)-Substrat
NL8303467A (nl) * 1983-10-10 1985-05-01 Philips Nv Werkwijze voor het vervaardigen van een patroon van geleidend materiaal.
JPS6081864A (ja) * 1983-10-12 1985-05-09 Fujitsu Ltd ラテラル型トランジスタ
US4897698A (en) * 1984-10-31 1990-01-30 Texas Instruments Incorporated Horizontal structure thin film transistor
EP0180363B1 (de) * 1984-10-31 1994-04-13 Texas Instruments Incorporated Transistor mit horizontaler Struktur und Verfahren zu dessen Herstellung
GB2178593B (en) * 1985-08-02 1989-07-26 Stc Plc Transistor manufacture
US4792837A (en) * 1986-02-26 1988-12-20 Ge Solid State Patents, Inc. Orthogonal bipolar transistor
US4784966A (en) * 1987-06-02 1988-11-15 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US5005066A (en) * 1987-06-02 1991-04-02 Texas Instruments Incorporated Self-aligned NPN bipolar transistor built in a double polysilicon CMOS technology
US4922315A (en) * 1987-11-13 1990-05-01 Kopin Corporation Control gate lateral silicon-on-insulator bipolar transistor
US5043786A (en) * 1989-04-13 1991-08-27 International Business Machines Corporation Lateral transistor and method of making same
JPH0483173A (ja) * 1990-07-26 1992-03-17 Tele Syst:Yugen 電力量計

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1352044A (en) * 1971-04-21 1974-05-15 Garyainov S A Glazkov I M Raik Planar semiconductor device
JPS4915374A (de) * 1972-05-18 1974-02-09
JPS49123274A (de) * 1973-03-29 1974-11-26
US4201603A (en) * 1978-12-04 1980-05-06 Rca Corporation Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon

Also Published As

Publication number Publication date
EP0052038B1 (de) 1986-06-04
JPH0241170B2 (de) 1990-09-14
CA1179786A (en) 1984-12-18
EP0052038A2 (de) 1982-05-19
EP0052038A3 (en) 1983-01-12
JPS57100763A (en) 1982-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

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