DE3144849C2 - - Google Patents

Info

Publication number
DE3144849C2
DE3144849C2 DE19813144849 DE3144849A DE3144849C2 DE 3144849 C2 DE3144849 C2 DE 3144849C2 DE 19813144849 DE19813144849 DE 19813144849 DE 3144849 A DE3144849 A DE 3144849A DE 3144849 C2 DE3144849 C2 DE 3144849C2
Authority
DE
Germany
Prior art keywords
glass master
alignment marks
adjustment
layer
radial distances
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19813144849
Other languages
German (de)
English (en)
Other versions
DE3144849A1 (de
Inventor
Peter Dr.Rer.Nat. 8031 Eichenau De Mengel
Guenter Dr.-Ing. 8150 Holzkirchen De Doemens
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19813144849 priority Critical patent/DE3144849A1/de
Publication of DE3144849A1 publication Critical patent/DE3144849A1/de
Application granted granted Critical
Publication of DE3144849C2 publication Critical patent/DE3144849C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/056—Using an artwork, i.e. a photomask for exposing photosensitive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0008—Apparatus or processes for manufacturing printed circuits for aligning or positioning of tools relative to the circuit board

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Length Measuring Devices By Optical Means (AREA)
DE19813144849 1981-11-11 1981-11-11 Opto-elektronisches justierverfahren bei der herstellung von mehrlagenschaltungen Granted DE3144849A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19813144849 DE3144849A1 (de) 1981-11-11 1981-11-11 Opto-elektronisches justierverfahren bei der herstellung von mehrlagenschaltungen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813144849 DE3144849A1 (de) 1981-11-11 1981-11-11 Opto-elektronisches justierverfahren bei der herstellung von mehrlagenschaltungen

Publications (2)

Publication Number Publication Date
DE3144849A1 DE3144849A1 (de) 1983-05-19
DE3144849C2 true DE3144849C2 (fr) 1990-07-12

Family

ID=6146166

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813144849 Granted DE3144849A1 (de) 1981-11-11 1981-11-11 Opto-elektronisches justierverfahren bei der herstellung von mehrlagenschaltungen

Country Status (1)

Country Link
DE (1) DE3144849A1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544801A (en) * 1969-05-01 1970-12-01 Fairchild Camera Instr Co Mask design for optical alignment systems
US3844655A (en) * 1973-07-27 1974-10-29 Kasper Instruments Method and means for forming an aligned mask that does not include alignment marks employed in aligning the mask
DE2812976C2 (de) * 1978-03-23 1980-03-06 Erich Ing.(Grad.) 3003 Ronnenberg Luther Verfahren zur Feststellung des Versatzes zwischen Leiterbahnen und Kontaktlöchern bei einer Leiterplatte sowie eine Leiterplatte zur Verwendung in diesem Verfahren
DE2835353C2 (de) * 1978-08-11 1982-05-13 Luther & Maelzer Gmbh, 3050 Wunstorf Verfahren zur Feststellung des Versatzes zwischen Kontaktlöchern und Leiterbahnen bei einer Leiterplatte sowie eine Leiterplatte zur Verwendung in diesem Verfahren
US4353087A (en) * 1979-03-12 1982-10-05 The Perkin-Elmer Corporation Automatic mask alignment

Also Published As

Publication number Publication date
DE3144849A1 (de) 1983-05-19

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Legal Events

Date Code Title Description
OM8 Search report available as to paragraph 43 lit. 1 sentence 1 patent law
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licenses declared (paragraph 23)
8339 Ceased/non-payment of the annual fee