DE3136223A1 - Integratable audio-frequency detector - Google Patents

Abstract

The integratable audio-frequency detector described exhibits a relatively long shift register (SR) with the aid of which an input vibration, the frequency (fe) of which is to be detected, is sampled. The sampling frequency (fs) is much higher than the frequency to be detected. The binary samples are shifted through the shift register so that a travelling wave of binary values corresponding to the input vibration is produced in this manner. Two logic circuits (L1, L2), the inputs of which are connected to stages of the shift register (SR) and the output signals of which are logically combined with one another by means of an NOR gate (G1), also generate, from waves having different wavelengths, different pulse sequences at the output (A1) of the NOR gate (G1). These pulse sequences are converted by a subsequent evaluation circuit into a yes/no decision which indicates whether the wavelength of the wave which is currently passing through the shift register (SR) has an agreed value within adjustable tolerance limits or not. The statement that the frequency (fe) of the input vibration has an agreed value or not is equivalent to this statement. <IMAGE>

Description

for

"IE KA DE Feiten & Guilloajiroc:" - " ^: .. ^: O7 ^: .Uy. 1" -VB 1 Fernmeldeanlagen GmbH P 81502

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Integrable audio frequency detector

The subject of the invention is an integrable audio frequency detector with the other, features mentioned in the preamble of claim 1.

Audio frequency detectors, which are built up from digital components and can therefore be integrated, are part of the State of the art.

An example of an integrable audio frequency detector, in which an input oscillation, its frequency is to be recognized, sampled and the sampled values shifted through a multi-stage shift register, is given in DE-OS 27 02 581.

In another audio frequency detector, which is described in German patent application P 31 33 345.1, the input vibration is sampled at an extremely high frequency; the sampling comes here to the measurement equal to the period of the input oscillation.

Should with the audio frequency detector according to the DE-OS 27 02 581 a sequence of tone frequencies can be recognized, so a different sampling frequency must be used for each frequency of the sequence. With the tone frequency sequences, of which we are talking here, the individual frequency values of the sequence only have values from a previous one agreed set of values. These agreed frequency values are usually like this - e.g. for selective call systems - that they do not emerge from one another by continually halving the frequency. Hence makes

the

the frequency detection according to DE-OS 27 02 581 still requires a special clock supply circuit, i.e., a clock supply circuit that does not consist of a simple frequency divider.

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Finally, with the circuit cited, only frequency sequences can be recognized in which the individual Frequencies are within an octave. If sequence sequences with a larger frequency range are to be recognized, an overall circuit would have to be constructed which consists of several detectors of the known type.

It is the object of the invention to provide an integrable audio frequency detector in which without special Clock supply circuit with a single shift register tone frequency sequences can be recognized whose individual frequencies may lie within a frequency interval of three octaves. In doing so, every The low input oscillation can be converted into a digitally evaluable pulse sequence with the aid of the shift register.

In a further development of the invention, a digital evaluation circuit is to be specified for the mentioned pulse sequence which by a logical "1" or "0" at its output indicates whether the frequency of the applied Input oscillation within adjustable tolerance limits with one of the agreed frequencies matches or not.

The object on which the invention is based is given by what is stated in the characterizing part of claim 1 Circuit features solved.

Further development and refinements of the invention are specified in the subclaims.

The invention is to be explained in more detail with the aid of the figures will.

Show it:

Fig.1 shows a circuit that generates an input oscillation in converts a pulse train,

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2 shows a circuit which evaluates the pulse train.

In Fig.1 the input oscillation lies with the frequency
fe to a terminal, which is also provided with the reference character fe. With each clock pulse of a shift clock whose frequency is denoted by fs - fs
let the value 62.4 kHz for the following explanations
have - becomes the instantaneous value of the input oscillation
transferred to the first stage of a shift register SR,
while the already stored binary values by one
Stage can be moved. In the shift register SR arises
in this way a running wave of binary values,
whose running speed is proportional to the frequency fs
is.

i If one now constantly compares the binary values with one another,

which are in two stages of the shift register, and

are these stages e.g. through fifty-two stages of j

Shift registers separated from each other, one has in I

the two levels of the pair of levels are always the same!

Binary value if the wavelength of the current wave

just fifty-two steps away;

speaks. ;

Transferred to the input oscillation, this means i

that their frequency fe just the fifty-second
Part of the clock frequency fs, i.e. according to the

The numerical example used is just 1.2 kHz. However, since the j

Wavelength of the current wave fluctuate statistically j

can, for example, that the input oscillation through!

Phase jitter is distorted, do you get with just one?

queried pair of stages no reliable statement about this j

whether the input frequency is 1.2 kHz or
not.

There are therefore at least two more stages - j

pairs are queried, between their levels also two

and fifty levels of the SR register. All three queried step pairs are offset from one another by at least one step.

The query is made by a logic circuit L1. It consists of three EXCLUSIVE-OR gates G11 to G13, at whose inputs the outputs of the stages of a pair of stages are connected. The three outputs of the gates are with a majority vote connected, which consists of NOR gates G12 to G17, and which emits a logical "1" at its output if the majority of the EXCLUSIVE-OR gates at the output the status "1" is present.

The majority decision described gives a permanent one at the output of the logic circuit L1, if - to stick with the numerical example given - the input oscillation is undistorted and their frequency is 1.2 kHz. If the phase jitter of the input oscillation becomes greater, then occurs for the predominant Time at the output of circuit L1 a logical "1", for the rest of the time a logical "0".

However, the circuit L1 is still predominantly a logic "1" at its output when the Input frequency deviates from the value 1.2 kHz. The further the pairs of steps are shifted from one another, the more so the frequency deviation from the value 1.2 kHz can be greater without there being predominantly at the output of the circuit L1 results in a logical "0". The shift in the pairs of steps thus turns out to be a parameter the arrangement that affects the tolerance limits for frequency detection.

If the frequency of the input oscillation is double or three times 1.2 kHz, the logic circuit L1 shows the same output as at 1.2 kHz. Therefore, L1 is with the circuit alone

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a distinction between the frequency 1.2 kHz on the one hand and. the multiples of it, on the other hand, impossible. To make this distinction possible, a further logic circuit L2 is provided, which is also on three pairs of stages of the shift register SR is connected.

There are twenty-one between the two levels of one of these pairs further stages of the shift register SR. The individual pairs are seventeen steps against each other postponed. As with circuit L1, the step pairs are of circuit L2 to the inputs of EXCLUSIVE-OR gates G21 to G23 out, with their output signals in turn a majority decision is made. Of the The majority decision maker required for this is made up of gates G24 to G27.

The distance between the stages of a pair and the displacement of the pairs against each other is measured in such a way and the majority decision maker is structured in such a way that the majority decision maker output is predominantly at logic "0" for all input frequencies between 2. It kHz and 3.6 kHz.

The combination of the output signals of the logic circuits L1 and L2 leads via a first NOR gate G1 In addition, a logic "1" is predominantly present at its output A1 only when the frequency of the input oscillation is approximately 1.2 kHz.

With the pulse sequence that occurs at output A1, an intermediate integration is first carried out. To this The purpose is - as FIG. 2 shows - the output A1 of the first NOR gate G1 with an input of a first AND gate G2 connected, at the second input of which a first clock signal f1 is applied. The clock signal f1 reaches the clock input of a counter Z1, if

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the output A1 is at logic "1"; otherwise the supply of counting pulses is interrupted by the gate G2.

If the status of the counter Z1 exceeds within one given period of time a fixed mark, about half the maximum counter reading, then this Event a first flip-flop FF1 is set. A connecting line between the highest one is used for this purpose Stage of the counter Z1 and the set input S of the flip-flop FF1.

The period of time in which the counter must come from zero to the specified mark in order for the flip-flop FP1 to be set is determined by a second clock signal f2. Its impulses are sent directly to the reset input of the counter Z1 supplied. They also serve to prevent the counter Z1 from overflowing when the frequency of the clock signal f2 is chosen so that it is less than or equal to the frequency f1: 2, where m is the Number of levels of the counter Z1 means.

The same clock pulse of the clock signal f2, which resets the counter Z1, is applied to the clock input of a second flip-flops FF2 and arrives with a slight delay - the delay is used by two Inverters not provided with reference symbols - also to the reset input of the first flip-flop FF1.

This initially - because of the connection between the Q output of the flip-flop FF1 and the data input the flip-flop FF2 - the state of the first flip-flop FF1 is transferred to the second flip-flop FF2

'' O and then the first flip-flop FF1 reset.

An up / down counter is used for further integration Z2 and a third clock signal f3, which clocks the counter Z2. Its up and down counting

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gang VR is connected to the Q output of the second flip-flop FF2. If the counter Z2 reaches half of it, for example maximum count, a logical "1" appears continuously at output A2 of the arrangement if the frequency fe the input oscillation is close to 1.2 kHz. Otherwise a logical "0" appears at output A2.

If the count of the counter Z2 is shown graphically as a function of the frequency of the input oscillation, then there is a relative maximum at 1.2 kHz. Whether the curve is steeper or flatter to the right or to the left falls from this maximum depends, among other things, on the mutual shifting of the pairs of stages of the shift register SR connected to the logic circuit L1, and also from the brand of the counter Z1 and the clock frequencies f2 and f3. However, the frequencies f1, f2 and f3 do not need special ones Conditions to be met so that they are available through continued frequency halving from the highest available standing frequency are to be derived.

The gates G3 to G6 serve to prevent overflow and underflow of the up-down counter Z2, namely the OR gate G6 blocks the counting pulses of the clock signal f3, when the counter Z2 is at zero and a logical one at its up / down counter input VR "0" is present or when the counter has reached its maximum level and at its up / down counting input '• ■ "R a logical" 1 "is present.

\ n: \ gridset G3 \ '"provided, the four inputs according ■ to the outputs of the four stages of the counter Z2 ... ^ ^- are joined The: cn counter Z2 query to the level zero, that is..?. The output of the gate G3, which is at "1" when the counter is at zero, leads to an input of the AND gate G4, the other input of which is connected to the (! ^ - output of the flip-flop FF2)

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is bound. If there is a threat of an underflow in counter Z2, it is the "Q output of the flip-flop FF2 also to" 1 ", so that the gate G4 with its" 1 "at the output the gate G6 blocks.

If the counter Z2 has reached its maximum level, a logical "0" appears at its carry-out output CO, which to which one input of the NOR gate G5 is passed. If there is a threat of overflow, the other one is also there of NOR gate G5 to "0" because it is connected to the Q output of flip-flop FF2. The "1" at the exit of NOR gate G5 now blocks gate G6 in this case.

The circuit described so far is used to detect a single frequency; as a numerical example 1.2 kHz assumed. Should with the arrangement according to the invention a frequency sequence of previously agreed frequencies must be recognized for each frequency the sequence pairs of stages of the shift register SR are connected to further logic circuits, with the distance between the pairs of steps - according to the example explained - is suitable for each frequency of the sequence choose is. A circuit as shown in FIG. 2 must also be provided for each frequency. At the equivalent to output A2 Outputs of the overall circuit can then be seen which frequency sequence at the input of the Schallung has established.

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Claims (6)

TE KA DE Feiten & Guilleawrte.:.- \ .- .. 07 _"P.9.1.? 81 Telecommunication GmbH P 8 * 1502 Claims ί 1. Integrable audio frequency detector, with which the pulse repetition frequency of an input oscillation is detected in that the input oscillation is sampled at a frequency that is significantly higher than its pulse repetition frequency and that the sampled values are shifted through a multi-stage shift register, characterized by the following circuit features: a) The inputs of a first logic circuit (Li), which has k input pairs, are connected to the Outputs of as many pairs of stages of the shift register (SR) connected, b) the two stages of each stage pair are separated by s stages of the shift register (SR) separated, c) the k pairs of stages of the shift register (SR) are offset from one another by at least one stage, d) the first logic circuit (L1) only emits a logic "1" at its output if at more than half of all k step pairs in the steps have the same binary value, e) the inputs of a second logic circuit (L2), which has w input pairs, are with the Outputs of as many pairs of stages of the shift register (SR) connected, ? ':> f) the two levels of each of the w level pairs are separated by a number of levels which is close to the value 0.4 »s, g) the w further pairs of stages are offset from one another by a number of stages, which in the Is close to the value 0.33 * s., h) the second logic circuit (L2) only emits a logic "0" at its output if at more than half of all w step pairs in the steps have the same binary value, i) the output signals of the two logic circuits (L1, L2) are via a first NOR gate (G1) linked together. 2. Integrable audio frequency detector according to claim "I, characterized in that the output (A1) of the first NOR gate (G1) is connected to one input of a first AND gate (G2), while at its other input a first clock signal ( fi) and that the output of the first AND gate (G2) leads to the counting input of a counter (ZT), to whose reset input (RZ) a second clock signal (f2) is applied, the frequency of which is selected so that the counter ( Z1) does not overflow. 3. Integrable audio frequency detector according to claim 2, characterized in that the counter (Z1) emits a pulse when a predetermined level is exceeded, which sets a first flip-flop (FF1) and that by the next clock pulse of the second clock signal (f2) the state at the Q output of the first flip-flop (FF1) is transferred to the Q output of a second flip-flop (FF2) and that the first flip-flop (FF1) is triggered by the same, slightly delayed clock pulse of the second clock signal (f2) is reset. 4. Integrable audio frequency detector according to claim 3, characterized in that the Q output of the second flip-flops (FF2) with the up-down counting input (VR) of an up-down counter (Z2) is connected, which is controlled by a third clock signal (f3) is clocked, the frequency of which is greater than the frequency of the second clock signal (f2) and that the highest Step of the up-down counter (Z2) to an output terminal (A2) of the integrable audio frequency detector leads. 5. Integrable audio frequency detector according to claim 4, characterized in that to prevent overflow or underflow of the up-down counter (Z2), the third clock signal (f3) runs via a second NOR gate (-G6), the second input of which with the Output of a second AND gate (G4) and the third input of which is connected to the output of a third NOR gate (G5) and that one input of the third NOR gate (G5) is connected to the carry-out output (CO) of the Up-down counter (Z2) leads and its other input is connected to the ÖT output of the second flip-flop (FF2) and that a fourth NOR gate (G3) is provided, which has as many inputs as the forward Reverse counter (Z2) has stages and that each stage of the up / down counter (Z2) is connected to one input of the fourth NOR gate (G3) and that the output of the fourth NOR gate (G3) and the ^ Output of the second flip-flop (FF2) to the two inputs of the second AND-Ga tters (G4) are placed. 6. Integrable audio frequency detector according to claim 1, characterized in that each input pair of the first and the second logic circuit (L1, L2) is formed by the input pair of an EXCLUSIVE-OR gate (■ 311 to G13} G21 to G23) and that the 3> Outputs of the EXCLUSIVE OR gates to the inputs connected by majority decision-makers designed in a known manner (G14 to G17; G24 to G27) are.