DE3070140D1 - Memory device - Google Patents

Memory device

Info

Publication number
DE3070140D1
DE3070140D1 DE8080101777T DE3070140T DE3070140D1 DE 3070140 D1 DE3070140 D1 DE 3070140D1 DE 8080101777 T DE8080101777 T DE 8080101777T DE 3070140 T DE3070140 T DE 3070140T DE 3070140 D1 DE3070140 D1 DE 3070140D1
Authority
DE
Germany
Prior art keywords
memory device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080101777T
Other languages
English (en)
Inventor
Shoji Ishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3070140D1 publication Critical patent/DE3070140D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE8080101777T 1979-04-04 1980-04-03 Memory device Expired DE3070140D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4067479A JPS55135392A (en) 1979-04-04 1979-04-04 Memory circuit

Publications (1)

Publication Number Publication Date
DE3070140D1 true DE3070140D1 (en) 1985-03-28

Family

ID=12587066

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080101777T Expired DE3070140D1 (en) 1979-04-04 1980-04-03 Memory device

Country Status (4)

Country Link
US (1) US4354259A (de)
EP (1) EP0017862B1 (de)
JP (1) JPS55135392A (de)
DE (1) DE3070140D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5798188A (en) * 1980-12-11 1982-06-18 Mitsubishi Electric Corp Memory circuit
JPS57162161A (en) * 1981-03-28 1982-10-05 Fujitsu Ltd Semiconductor storage device
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
JPS58147884A (ja) * 1982-02-26 1983-09-02 Toshiba Corp ダイナミック型半導体記憶装置
US4539661A (en) * 1982-06-30 1985-09-03 Fujitsu Limited Static-type semiconductor memory device
US4596004A (en) * 1983-09-14 1986-06-17 International Business Machines Corporation High speed memory with a multiplexed address bus
US5217917A (en) * 1990-03-20 1993-06-08 Hitachi, Ltd. Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor
JP2646032B2 (ja) * 1989-10-14 1997-08-25 三菱電機株式会社 Ｌｉｆｏ方式の半導体記憶装置およびその制御方法
US8503264B1 (en) * 2011-11-18 2013-08-06 Xilinx, Inc. Reducing power consumption in a segmented memory
US8743653B1 (en) 2012-06-20 2014-06-03 Xilinx, Inc. Reducing dynamic power consumption of a memory circuit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560940A (en) * 1968-07-15 1971-02-02 Ibm Time shared interconnection apparatus
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory
US3836892A (en) * 1972-06-29 1974-09-17 Ibm D.c. stable electronic storage utilizing a.c. stable storage cell
JPS5433498B2 (de) * 1972-09-19 1979-10-20
US3811117A (en) * 1972-10-19 1974-05-14 Ibm Time ordered memory system and operation
US3828320A (en) * 1972-12-29 1974-08-06 Burroughs Corp Shared memory addressor
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
US4050061A (en) * 1976-05-03 1977-09-20 Texas Instruments Incorporated Partitioning of MOS random access memory array
US4207618A (en) * 1978-06-26 1980-06-10 Texas Instruments Incorporated On-chip refresh for dynamic memory
US4241425A (en) * 1979-02-09 1980-12-23 Bell Telephone Laboratories, Incorporated Organization for dynamic random access memory

Also Published As

Publication number Publication date
JPS6227476B2 (de) 1987-06-15
JPS55135392A (en) 1980-10-22
EP0017862B1 (de) 1985-02-13
US4354259A (en) 1982-10-12
EP0017862A1 (de) 1980-10-29

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