DE3063148D1 - Process for producing polycrystalline silicium layers located on silica clad regions of a silicium board, and application to the production of a non-planar self-aligned mos transistor - Google Patents

Process for producing polycrystalline silicium layers located on silica clad regions of a silicium board, and application to the production of a non-planar self-aligned mos transistor

Info

Publication number
DE3063148D1
DE3063148D1 DE8080401252T DE3063148T DE3063148D1 DE 3063148 D1 DE3063148 D1 DE 3063148D1 DE 8080401252 T DE8080401252 T DE 8080401252T DE 3063148 T DE3063148 T DE 3063148T DE 3063148 D1 DE3063148 D1 DE 3063148D1
Authority
DE
Germany
Prior art keywords
silicium
board
production
mos transistor
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080401252T
Other languages
German (de)
English (en)
Inventor
Eugene Tonnel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE3063148D1 publication Critical patent/DE3063148D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
DE8080401252T 1979-09-18 1980-09-02 Process for producing polycrystalline silicium layers located on silica clad regions of a silicium board, and application to the production of a non-planar self-aligned mos transistor Expired DE3063148D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7923242A FR2466101A1 (fr) 1979-09-18 1979-09-18 Procede de formation de couches de silicium polycristallin localisees sur des zones recouvertes de silice d'une plaquette de silicium et application a la fabrication d'un transistor mos non plan autoaligne

Publications (1)

Publication Number Publication Date
DE3063148D1 true DE3063148D1 (en) 1983-06-16

Family

ID=9229752

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080401252T Expired DE3063148D1 (en) 1979-09-18 1980-09-02 Process for producing polycrystalline silicium layers located on silica clad regions of a silicium board, and application to the production of a non-planar self-aligned mos transistor

Country Status (5)

Country Link
US (1) US4420379A (enExample)
EP (1) EP0026686B1 (enExample)
JP (1) JPS5654072A (enExample)
DE (1) DE3063148D1 (enExample)
FR (1) FR2466101A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2165090A (en) * 1984-09-26 1986-04-03 Philips Electronic Associated Improving the field distribution in high voltage semiconductor devices
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5466616A (en) * 1994-04-06 1995-11-14 United Microelectronics Corp. Method of producing an LDMOS transistor having reduced dimensions, reduced leakage, and a reduced propensity to latch-up
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
GB2362755A (en) * 2000-05-25 2001-11-28 Nanogate Ltd Thin film field effect transistor with a conical structure

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3345274A (en) * 1964-04-22 1967-10-03 Westinghouse Electric Corp Method of making oxide film patterns
US3438873A (en) * 1966-05-11 1969-04-15 Bell Telephone Labor Inc Anodic treatment to alter solubility of dielectric films
US3627647A (en) * 1969-05-19 1971-12-14 Cogar Corp Fabrication method for semiconductor devices
US3640806A (en) * 1970-01-05 1972-02-08 Nippon Telegraph & Telephone Semiconductor device and method of producing the same
US3764491A (en) * 1971-12-13 1973-10-09 Bell Telephone Labor Inc Electrolytic oxidation of silicon
US3954523A (en) * 1975-04-14 1976-05-04 International Business Machines Corporation Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation
JPS6027179B2 (ja) * 1975-11-05 1985-06-27 日本電気株式会社 多孔質シリコンの形成方法
FR2340619A1 (fr) * 1976-02-04 1977-09-02 Radiotechnique Compelec Perfectionnement au procede de fabrication de dispositifs semiconducteurs et dispositifs ainsi obtenus
JPS5362985A (en) * 1976-11-18 1978-06-05 Toshiba Corp Mis type field effect transistor and its production
US4116720A (en) * 1977-12-27 1978-09-26 Burroughs Corporation Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Also Published As

Publication number Publication date
US4420379A (en) 1983-12-13
FR2466101B1 (enExample) 1983-07-01
FR2466101A1 (fr) 1981-03-27
JPS5654072A (en) 1981-05-13
EP0026686A1 (fr) 1981-04-08
EP0026686B1 (fr) 1983-05-11

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee