DE3001189C2 - Programmierbare sequentielle logische Schaltungseinrichtung - Google Patents
Programmierbare sequentielle logische SchaltungseinrichtungInfo
- Publication number
- DE3001189C2 DE3001189C2 DE3001189A DE3001189A DE3001189C2 DE 3001189 C2 DE3001189 C2 DE 3001189C2 DE 3001189 A DE3001189 A DE 3001189A DE 3001189 A DE3001189 A DE 3001189A DE 3001189 C2 DE3001189 C2 DE 3001189C2
- Authority
- DE
- Germany
- Prior art keywords
- flip
- field
- flop
- circuit
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP359779A JPS5595147A (en) | 1979-01-16 | 1979-01-16 | Sequence circuit |
JP54012461A JPS597970B2 (ja) | 1979-02-06 | 1979-02-06 | 系列信号発生回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3001189A1 DE3001189A1 (de) | 1980-07-24 |
DE3001189C2 true DE3001189C2 (de) | 1983-03-31 |
Family
ID=26337226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3001189A Expired DE3001189C2 (de) | 1979-01-16 | 1980-01-15 | Programmierbare sequentielle logische Schaltungseinrichtung |
Country Status (4)
Country | Link |
---|---|
US (1) | US4415818A (US07655688-20100202-C00086.png) |
DE (1) | DE3001189C2 (US07655688-20100202-C00086.png) |
FR (1) | FR2447120A1 (US07655688-20100202-C00086.png) |
GB (1) | GB2045488B (US07655688-20100202-C00086.png) |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4661922A (en) * | 1982-12-08 | 1987-04-28 | American Telephone And Telegraph Company | Programmed logic array with two-level control timing |
US4488230A (en) * | 1982-12-08 | 1984-12-11 | At&T Bell Laboratories | Programmed logic array with external signals introduced between its AND plane and its OR plane |
US4488229A (en) * | 1982-12-08 | 1984-12-11 | At&T Bell Laboratories | PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability |
US4546273A (en) * | 1983-01-11 | 1985-10-08 | Burroughs Corporation | Dynamic re-programmable PLA |
US4508977A (en) * | 1983-01-11 | 1985-04-02 | Burroughs Corporation | Re-programmable PLA |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
GB2202355B (en) * | 1985-02-27 | 1989-10-11 | Xilinx Inc | Configurable storage circuit |
US4684830A (en) * | 1985-03-22 | 1987-08-04 | Monolithic Memories, Inc. | Output circuit for a programmable logic array |
US5225719A (en) * | 1985-03-29 | 1993-07-06 | Advanced Micro Devices, Inc. | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
US4742252A (en) * | 1985-03-29 | 1988-05-03 | Advanced Micro Devices, Inc. | Multiple array customizable logic device |
US4644192A (en) * | 1985-09-19 | 1987-02-17 | Harris Corporation | Programmable array logic with shared product terms and J-K registered outputs |
US4771285A (en) * | 1985-11-05 | 1988-09-13 | Advanced Micro Devices, Inc. | Programmable logic cell with flexible clocking and flexible feedback |
US4675556A (en) * | 1986-06-09 | 1987-06-23 | Intel Corporation | Binomially-encoded finite state machine |
US4791603A (en) * | 1986-07-18 | 1988-12-13 | Honeywell Inc. | Dynamically reconfigurable array logic |
US5349670A (en) * | 1986-07-23 | 1994-09-20 | Advanced Micro Devices, Inc. | Integrated circuit programmable sequencing element apparatus |
US5477165A (en) | 1986-09-19 | 1995-12-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
FR2633407B1 (fr) * | 1988-06-27 | 1990-11-02 | Crouzet Sa | Dispositif programmable de commande de relais |
US4965472A (en) * | 1988-08-11 | 1990-10-23 | Cypress Semiconductor Corp. | Programmable high speed state machine with sequencing capabilities |
CA1292572C (en) * | 1988-10-25 | 1991-11-26 | Fernando C. Lebron | Cardiac mapping system simulator |
JPH02140804A (ja) * | 1988-11-21 | 1990-05-30 | Maikomu Kk | プログラマブルロジック回路 |
US4942319A (en) * | 1989-01-19 | 1990-07-17 | National Semiconductor Corp. | Multiple page programmable logic architecture |
US5081375A (en) * | 1989-01-19 | 1992-01-14 | National Semiconductor Corp. | Method for operating a multiple page programmable logic device |
JP2879070B2 (ja) * | 1989-02-15 | 1999-04-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | プログラム可能論理ユニット及び信号プロセッサ |
US5204555A (en) * | 1990-04-05 | 1993-04-20 | Gazelle Microcircuits, Inc. | Logic array having high frequency internal clocking |
GB2243008A (en) * | 1990-04-05 | 1991-10-16 | Gazelle Microcircuits Inc | Logic array or state machine |
US5198705A (en) | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5861760A (en) | 1991-04-25 | 1999-01-19 | Altera Corporation | Programmable logic device macrocell with improved capability |
US5621337A (en) * | 1995-08-30 | 1997-04-15 | National Semiconductor Corporation | Iterative logic circuit |
US5907719A (en) * | 1996-01-22 | 1999-05-25 | Cirrus Logic, Inc. | Communication interface unit employing two multiplexer circuits and control logic for performing parallel-to-serial data conversion of a selected asynchronous protocol |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US5936426A (en) | 1997-02-03 | 1999-08-10 | Actel Corporation | Logic function module for field programmable array |
US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6037801A (en) * | 1997-10-27 | 2000-03-14 | Intel Corporation | Method and apparatus for clocking a sequential logic circuit |
US6810513B1 (en) * | 2002-06-19 | 2004-10-26 | Altera Corporation | Method and apparatus of programmable interconnect array with configurable multiplexer |
DE102004047425B4 (de) * | 2004-09-28 | 2007-06-21 | Micronas Gmbh | Zufallszahlengenerator sowie Verfahren zur Erzeugung von Zufallszahlen |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3230355A (en) * | 1962-12-04 | 1966-01-18 | Melpar Inc | Matrix logic computer |
US3566153A (en) * | 1969-04-30 | 1971-02-23 | Texas Instruments Inc | Programmable sequential logic |
US4032894A (en) * | 1976-06-01 | 1977-06-28 | International Business Machines Corporation | Logic array with enhanced flexibility |
FR2396468A1 (fr) * | 1977-06-30 | 1979-01-26 | Ibm France | Perfectionnement aux reseaux logiques programmables |
JPS558135A (en) * | 1978-07-04 | 1980-01-21 | Mamoru Tanaka | Rewritable programable logic array |
-
1980
- 1980-01-07 US US06/110,030 patent/US4415818A/en not_active Expired - Lifetime
- 1980-01-09 GB GB8000676A patent/GB2045488B/en not_active Expired
- 1980-01-11 FR FR8000645A patent/FR2447120A1/fr active Granted
- 1980-01-15 DE DE3001189A patent/DE3001189C2/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2447120B1 (US07655688-20100202-C00086.png) | 1984-03-16 |
GB2045488A (en) | 1980-10-29 |
GB2045488B (en) | 1982-10-13 |
DE3001189A1 (de) | 1980-07-24 |
US4415818A (en) | 1983-11-15 |
FR2447120A1 (fr) | 1980-08-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OAP | Request for examination filed | ||
OD | Request for examination | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NIPPON TELEGRAPH AND TELEPHONE CORP., TOKIO/TOKYO, |
|
8328 | Change in the person/name/address of the agent |
Free format text: WENZEL, H., DIPL.-ING., 2000 HAMBURG KALKOFF, H., DIPL.-ING. WREDE, H., DIPL.-ING., PAT.-ANW., 5810WITTEN |