DE2961391D1 - Integrated circuit with a two-level interconnection structure; method of making such a circuit - Google Patents

Integrated circuit with a two-level interconnection structure; method of making such a circuit

Info

Publication number
DE2961391D1
DE2961391D1 DE7979400111T DE2961391T DE2961391D1 DE 2961391 D1 DE2961391 D1 DE 2961391D1 DE 7979400111 T DE7979400111 T DE 7979400111T DE 2961391 T DE2961391 T DE 2961391T DE 2961391 D1 DE2961391 D1 DE 2961391D1
Authority
DE
Germany
Prior art keywords
circuit
making
interconnection structure
level interconnection
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979400111T
Other languages
English (en)
Inventor
Gerard Nuzillat
Christian Arnodo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Application granted granted Critical
Publication of DE2961391D1 publication Critical patent/DE2961391D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE7979400111T 1978-03-08 1979-02-23 Integrated circuit with a two-level interconnection structure; method of making such a circuit Expired DE2961391D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7806673A FR2419586A1 (fr) 1978-03-08 1978-03-08 Circuit integre et son procede de fabrication

Publications (1)

Publication Number Publication Date
DE2961391D1 true DE2961391D1 (en) 1982-01-28

Family

ID=9205520

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979400111T Expired DE2961391D1 (en) 1978-03-08 1979-02-23 Integrated circuit with a two-level interconnection structure; method of making such a circuit

Country Status (5)

Country Link
US (1) US4263340A (de)
EP (1) EP0004219B1 (de)
JP (1) JPS54126487A (de)
DE (1) DE2961391D1 (de)
FR (1) FR2419586A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481263A (en) * 1982-05-17 1984-11-06 Raytheon Company Programmable read only memory
US4499656A (en) * 1983-08-15 1985-02-19 Sperry Corporation Deep mesa process for fabricating monolithic integrated Schottky barrier diode for millimeter wave mixers
JPS6072248A (ja) * 1983-09-28 1985-04-24 Nec Corp 半導体装置及びその製造方法
JPS63124446A (ja) * 1986-11-06 1988-05-27 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 接続孔形成方法
US5693969A (en) * 1995-03-06 1997-12-02 Motorola MESFET having a termination layer in the channel layer
JP5787251B2 (ja) * 2011-02-28 2015-09-30 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016643A (en) * 1974-10-29 1977-04-12 Raytheon Company Overlay metallization field effect transistor
DE2631873C2 (de) * 1976-07-15 1986-07-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung eines Halbleiterbauelements mit einem Schottky-Kontakt auf einem zu einem anderen Bereich justierten Gatebereich und mit kleinem Serienwiderstand

Also Published As

Publication number Publication date
FR2419586B1 (de) 1982-04-30
US4263340A (en) 1981-04-21
EP0004219A1 (de) 1979-09-19
FR2419586A1 (fr) 1979-10-05
JPS54126487A (en) 1979-10-01
EP0004219B1 (de) 1981-11-25

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee