DE2907799A1 - Verfahren und anordnung zum steuern des zugriffs zu einem arbeitsspeicher - Google Patents

Verfahren und anordnung zum steuern des zugriffs zu einem arbeitsspeicher

Info

Publication number
DE2907799A1
DE2907799A1 DE19792907799 DE2907799A DE2907799A1 DE 2907799 A1 DE2907799 A1 DE 2907799A1 DE 19792907799 DE19792907799 DE 19792907799 DE 2907799 A DE2907799 A DE 2907799A DE 2907799 A1 DE2907799 A1 DE 2907799A1
Authority
DE
Germany
Prior art keywords
memory
main memory
processor
data
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19792907799
Other languages
German (de)
English (en)
Inventor
Spurgeon Graves Hogan
Carleton Edward Werve
Edward Chor-Cheung Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2907799A1 publication Critical patent/DE2907799A1/de
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE19792907799 1978-03-07 1979-02-28 Verfahren und anordnung zum steuern des zugriffs zu einem arbeitsspeicher Ceased DE2907799A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/884,301 US4169284A (en) 1978-03-07 1978-03-07 Cache control for concurrent access

Publications (1)

Publication Number Publication Date
DE2907799A1 true DE2907799A1 (de) 1979-09-13

Family

ID=25384348

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19792907799 Ceased DE2907799A1 (de) 1978-03-07 1979-02-28 Verfahren und anordnung zum steuern des zugriffs zu einem arbeitsspeicher

Country Status (6)

Country Link
US (1) US4169284A (https=)
JP (1) JPS54118739A (https=)
DE (1) DE2907799A1 (https=)
FR (1) FR2419561A1 (https=)
GB (1) GB2015216B (https=)
IT (1) IT1164985B (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4425616A (en) 1979-11-06 1984-01-10 Frederick Electronic Corporation High-speed time share processor
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
US4493033A (en) * 1980-04-25 1985-01-08 Data General Corporation Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
JPS56169281A (en) 1980-06-02 1981-12-25 Hitachi Ltd Data processor
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words
JPS5764383A (en) * 1980-10-03 1982-04-19 Toshiba Corp Address converting method and its device
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
SE445270B (sv) * 1981-01-07 1986-06-09 Wang Laboratories Dator med ett fickminne, vars arbetscykel er uppdelad i tva delcykler
US4426682A (en) 1981-05-22 1984-01-17 Harris Corporation Fast cache flush mechanism
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
US4486856A (en) * 1982-05-10 1984-12-04 Teletype Corporation Cache memory and control circuit
US4628489A (en) * 1983-10-03 1986-12-09 Honeywell Information Systems Inc. Dual address RAM
US4755928A (en) * 1984-03-05 1988-07-05 Storage Technology Corporation Outboard back-up and recovery system with transfer of randomly accessible data sets between cache and host and cache and tape simultaneously
US4942518A (en) * 1984-06-20 1990-07-17 Convex Computer Corporation Cache store bypass for computer
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
US4695943A (en) * 1984-09-27 1987-09-22 Honeywell Information Systems Inc. Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
US4827401A (en) * 1984-10-24 1989-05-02 International Business Machines Corporation Method and apparatus for synchronizing clocks prior to the execution of a flush operation
EP0189944B1 (en) * 1985-02-01 1993-05-12 Nec Corporation Cache memory circuit capable of processing a read request during transfer of a data block
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
DE3537115A1 (de) * 1985-10-18 1987-05-27 Standard Elektrik Lorenz Ag Verfahren zum betreiben einer einrichtung mit zwei voneinander unabhaengigen befehlseingabestellen und nach diesem verfahren arbeitende einrichtung
US5001665A (en) * 1986-06-26 1991-03-19 Motorola, Inc. Addressing technique for providing read, modify and write operations in a single data processing cycle with serpentine configured RAMs
US4802125A (en) * 1986-11-21 1989-01-31 Nec Corporation Memory access control apparatus
US4953077A (en) * 1987-05-15 1990-08-28 International Business Machines Corporation Accelerated data transfer mechanism using modified clock cycle
US4928225A (en) * 1988-08-25 1990-05-22 Edgcore Technology, Inc. Coherent cache structures and methods
JPH02224043A (ja) * 1988-11-15 1990-09-06 Nec Corp キャッシュメモリ
US5454093A (en) * 1991-02-25 1995-09-26 International Business Machines Corporation Buffer bypass for quick data access
JP3920931B2 (ja) * 1992-04-17 2007-05-30 サン・マイクロシステムズ・インコーポレイテッド キャッシュされたデータを読出しおよび書込む方法ならびにデータをキャッシングする装置
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
JPH08314794A (ja) * 1995-02-28 1996-11-29 Matsushita Electric Ind Co Ltd 安定記憶装置へのアクセス待ち時間を短縮するための方法およびシステム
US6262936B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Random access memory having independent read port and write port and process for writing to and reading from the same
US6262937B1 (en) 1998-03-13 2001-07-17 Cypress Semiconductor Corp. Synchronous random access memory having a read/write address bus and process for writing to and reading from the same
US6069839A (en) 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
US6789168B2 (en) * 2001-07-13 2004-09-07 Micron Technology, Inc. Embedded DRAM cache

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2727188A1 (de) * 1976-06-18 1977-12-29 Thomson Csf Anordnung zum adressieren eines speichers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
US3670307A (en) * 1969-12-23 1972-06-13 Ibm Interstorage transfer mechanism
US4016541A (en) * 1972-10-10 1977-04-05 Digital Equipment Corporation Memory unit for connection to central processor unit and interconnecting bus
US3858183A (en) * 1972-10-30 1974-12-31 Amdahl Corp Data processing system and method therefor
US4080652A (en) * 1977-02-17 1978-03-21 Xerox Corporation Data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2727188A1 (de) * 1976-06-18 1977-12-29 Thomson Csf Anordnung zum adressieren eines speichers

Also Published As

Publication number Publication date
FR2419561A1 (fr) 1979-10-05
IT7920569A0 (it) 1979-02-27
IT1164985B (it) 1987-04-22
GB2015216B (en) 1982-03-31
GB2015216A (en) 1979-09-05
JPS5727546B2 (https=) 1982-06-11
US4169284A (en) 1979-09-25
FR2419561B1 (https=) 1984-09-28
JPS54118739A (en) 1979-09-14

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: G06F 9/00

8131 Rejection