DE2846521A1 - Zentrale recheneinheit fuer ein digitales datenverarbeitungssystem - Google Patents

Zentrale recheneinheit fuer ein digitales datenverarbeitungssystem

Info

Publication number
DE2846521A1
DE2846521A1 DE19782846521 DE2846521A DE2846521A1 DE 2846521 A1 DE2846521 A1 DE 2846521A1 DE 19782846521 DE19782846521 DE 19782846521 DE 2846521 A DE2846521 A DE 2846521A DE 2846521 A1 DE2846521 A1 DE 2846521A1
Authority
DE
Germany
Prior art keywords
register
subroutine
memory
command
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19782846521
Other languages
German (de)
English (en)
Other versions
DE2846521C2 (enrdf_load_stackoverflow
Inventor
Thomas F Hastings
David P Rodgers
Steven H Rothman
William D Strecker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE2846521A1 publication Critical patent/DE2846521A1/de
Application granted granted Critical
Publication of DE2846521C2 publication Critical patent/DE2846521C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
DE19782846521 1977-10-25 1978-10-25 Zentrale recheneinheit fuer ein digitales datenverarbeitungssystem Granted DE2846521A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US84541677A 1977-10-25 1977-10-25

Publications (2)

Publication Number Publication Date
DE2846521A1 true DE2846521A1 (de) 1979-04-26
DE2846521C2 DE2846521C2 (enrdf_load_stackoverflow) 1991-11-14

Family

ID=25295191

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782846521 Granted DE2846521A1 (de) 1977-10-25 1978-10-25 Zentrale recheneinheit fuer ein digitales datenverarbeitungssystem

Country Status (7)

Country Link
JP (1) JPS5931735B2 (enrdf_load_stackoverflow)
AU (1) AU517948B2 (enrdf_load_stackoverflow)
CA (1) CA1112368A (enrdf_load_stackoverflow)
DE (1) DE2846521A1 (enrdf_load_stackoverflow)
FR (1) FR2407521B1 (enrdf_load_stackoverflow)
GB (1) GB2007891B (enrdf_load_stackoverflow)
IT (1) IT1192334B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU634781B2 (en) * 1990-04-27 1993-03-04 Digital Equipment Corporation Normalizer
WO1996008763A2 (en) * 1994-09-16 1996-03-21 Philips Electronics N.V. Method, apparatus and instruction for performing a double jump register indirect operation transfer in a microcontroller
DE10245367A1 (de) * 2002-09-27 2004-04-15 Infineon Technologies Ag Prozessor mit expliziter Angabe über zu sichernde Informationen bei Unterprogrammsprüngen

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US3614740A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4041462A (en) * 1976-04-30 1977-08-09 International Business Machines Corporation Data processing system featuring subroutine linkage operations using hardware controlled stacks

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614741A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with instruction addresses identifying one of a plurality of registers including the program counter
US3614740A (en) * 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
US-Buch B. Sou?ek, "Microprozessors and Microcomputers", John Wiley & Sons, 1976, S. 286-291
US-Buch B. SouCek, "Microprozessors and Microcomputers", John Wiley & Sons, 1976, S. 286-291 *
US-Firmenschrift der Digital Equipment Corp. "pdp U/70 processor handbook", 1975, S. 4/58-4/60 *

Also Published As

Publication number Publication date
DE2846521C2 (enrdf_load_stackoverflow) 1991-11-14
FR2407521A1 (fr) 1979-05-25
AU4103878A (en) 1980-05-01
IT7869442A0 (it) 1978-10-24
FR2407521B1 (fr) 1988-02-05
JPS5931735B2 (ja) 1984-08-03
GB2007891A (en) 1979-05-23
IT1192334B (it) 1988-03-31
AU517948B2 (en) 1981-09-03
JPS5484945A (en) 1979-07-06
CA1112368A (en) 1981-11-10
GB2007891B (en) 1982-09-08

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition