DE2759866C2 - Arrangement for the selective insertion of a digital synchronization word in at least one digitally coded data sequence clocked at a predetermined frequency to an input - Google Patents

Description

The present invention relates to an arrangement for the selective insertion of a digital synchronization word in at least one digitally encoded with a predetermined frequency on an input Data sequence according to the preamble of the patent claim

Such an arrangement is generally in recording and reproducing devices and especially in devices Can be used for recording and reproducing television signals using digital techniques.

Ongoing technological advances have resulted in numerous changes in devices that are used in TV broadcasting stations are used. One of the more significant changes is that photographic techniques in favor of magnetic media in many commercial television broadcasting locations were abandoned. For example, films that are broadcast often no longer come from you Film strip but from a magnetic tape. News departments of television broadcasting stations also go predominantly to video tape recording systems; for the visible representation of new News is being pushed back more and more to film cameras. In addition, they are often posable Take advantage of transmission stations, which send information either directly from their location or to a station from which the information is either sent live or on a Videotape can be recorded, edited and broadcast at a later time. One of Many advantages of such a method is the ease of use, the flexibility and the Processing speed can be seen in comparison to a photographic film. These benefits are with coupled with the possibility of being able to use the magnetic tape again if the one recorded on it Information is no longer needed.

One of the last remaining domains of film in today's commercial television broadcasting stations is that Image projection using 35 mm film transparencies. This image projection is used for Obtaining still television images, which for example for program information, advertising and Messages are used. In general, the aforementioned option is used wherever in the Operation a still picture is necessary. The effort for such image projections arises from the fact

f> 5 it can be seen that a medium-sized commercial television broadcasting station a total of about 2000 to 5000 slides with 35 mm leads. The maintenance of such an overall

consisted of a large amount of work that the Introduction of new slides, the sorting out of bad slides and the permanent management of one makes exact list compilation necessary, so that slides in case of need in easier Way are accessible. If program sequences are to be compiled from such slides, see above the individual slides have to be made by hand Projection device carried, cleaned and used manually. Alone during the cleaning process For example, dust particles and scratches can be unsatisfactory even with careful handling Produce results. In addition, after they have been used, the slides must be sent for broadcasting purposes removed and returned to their storage location. The whole process of putting together the use for broadcast purposes and the return of the slides due to the associated manual activities require a lot of work. The projection process is common in many modern day Broadcasting stations are to a large extent outdated and generally not with fully automatic station operation compatible.

In contrast to projection equipment or the use of opaque graphic material A recording is used as the source for generating still video images within the scope of the invention and playback of still images, with the video information in the form of still images Images are stored on magnetic media. Ls is concerned with the use of computer-controlled Standard disk drive units (which, however, are modified in certain aspects) with magnetic storage media, eliminating the problems associated with the projection of slides be avoided. As the still images are recorded on magnetic media, occur Problems of mechanical impairment, for example from dust particles or scratches not on. Since the recorded information is still easily accessible, the same still picture can can be used practically at the same time by operators at different locations. It's in the frame the digital signal processing from DE-OS 24 46 690 already an arrangement of the aforementioned Art became known in the form of a signal multiplexer, with digital synchronization words. · Selective can be used in digitally coded video signals. In such an arrangement, however, there are specifically none Measures taken to insert the sync word when recording in such a way in video signals that a Playback device can define and synchronize its operation by means of the sync word.

DE-PS 14 62 434 describes an arrangement that works in a conventional manner in an analog manner. In this known arrangement are only conventional horizontal and vertical sync pulses in the Horizontal and vertical blanking intervals used. This takes place when the analogue is regressed Video signal after resetting the DC voltage level using conventional mixers will. In the previously known arrangement, no data is used for the purpose of inserting other data deleted from a digital data sequence. This is not possible even with an arrangement that works in an analogue manner. In addition, in the case of digital signals, for inserting other data, usually the data sequence is used stopped or otherwise interrupted; however, no data will be deleted

From US-PS 37 95 763 an arrangement is known for reducing the bandwidth in the Transmission of digital television signals the horizontal and vertical sync pulses through sync words be replaced. The horizontal and vertical sync pulses are generated from these sync words newly generated on the receiving end. However, it is also not possible for recording and playback of television information on the playback side to synchronize the operation of a corresponding device.

The present invention is based on the object of creating an arrangement of the type in question with which a synchronization word can be inserted into a television signal in such a way that it is synchronized with its color sync signal component and this synchronization is maintained even when there are changes in the timing of the television signals . The above-mentioned object is achieved according to the invention by the characterizing features of claim 1 in an arrangement of the type mentioned at the outset.

A recording and reproducing device provided with the arrangement according to the invention is processed a composite video information signal for recording on disk stacks of Compuier disk drive units, wherein during processing the hol izontalsynchroinimpuls from the signal are removed, after which samples of the analog video information signal are generated and converted into a number be transferred from digital data sequences.

The arrangement according to the invention is used to insert a unique digital synchronization word J5 generally on every other TV line the location of the previously removed horizontal sync pulse. The synchronization word serves as a reference for Correction of time base and distortion errors caused by the multitude of data bits in the data streams that must be combined to form the amount of each sample value. Since that If the synchronization word is a multi-bit word inserted into the data sequence, it can be seen that the synchronization word forming bits may occur arbitrarily during the active part of the -15 television line. For this reason, except for the presence of the clear synchronization word from the information content in the data sequences. In this way "'» Can use the circuit in the playback part for the signal easily and precisely capture the synchronization word that is used as the timing reference.

Due to the arrangement according to the invention, the entire information content of the data files is also retained removed during approximately the first half of the vertical blanking interval, leaving only the sync word occurs every other line in the first 10 to 12 lines of the vertical blanking interval. This means that there is sufficient time for the registration process Circuit provided for determining the synchronization word in the event that the circuit is no longer properly oriented for some reason. The arrangement according to the invention sets that Sync word in the right place during every other line in the horizontal blanking interval, without the generally continuously running data sequences being stopped. However, it is not an active one Video information lost Ha Has ςνικΊι ^ ηίοοΐ: «. ^

word inserted during the horizontal blanking interval will.

According to the invention, digital techniques are used to prepare video information signals for recording on disk stacks of computer disk drive devices. During the recording process, the horizontal sync pulses from analog information signal, as the NTSC television signal does not have a specific defined relationship between the horizontal sync pulse occurring in each line and the phase of the chrominance subcarrier signal having. After the horizontal sync pulses have been separated from the signal, the The signal is sampled at a repetition frequency which is preferably a multiple of the subcarrier frequency. According to a special embodiment, the cycle frequency is equal to three times the auxiliary carrier frequency, wherein the sample values are converted into a plurality of digital data sequences which are based on magnetic Media are recorded. Before the recording, however, there is a newly defined horizontal sync signal in the form of a digital multi-bit synchronization word in every second line of the Data sequences used in such a way that the synchronization words with the subcarrier (and also with the triple subcarrier Tastsignai) are phase-synchronized, so that the synchronization word in one constant phase relationship relative to the subcarrier (and to the triple subcarrier signal) will. In this way, the newly defined horizontal sync signal, i. i.e., the digital synchronization word especially when reproducing the recorded digital information as a basic reference signal used for the system.

Refinements of the inventive concept are identified in sub-claims.

The invention is described below with reference to the exemplary embodiments shown in the figures of the drawing explained in more detail. It shows

F i g. 1 is a block diagram of a coding and synchronizing word insertion circuit,

2A to 2D are a circuit diagram of the coding and sync word insertion circuit of the signal system according to FIG Block diagram r-ach F i g, 1 and

F i g. FIG. 2E shows a timing diagram to explain the mode of operation of the data coding circuit according to FIG. 2A to2D.

The arrangement according to the invention is described here in connection with the NTSC system, in which a television picture has 525 lines and the horizontal synchronizing pulses occur with a repetition frequency of approximately 15.734 Hz, i. That is, the period between successive horizontal sync pulses is approximately 63.5 microseconds. Further, the vertical Austastfrequenz in the NTSC system is 60 Hz, the chrominance information is modulated on a subcarrier with a frequency of about 3.58 MHz The Hiifsträgerfrequenz of 3.58 MHz is in the following also simply referred to as SC, whereby the simple meant Hiifsträgerfrequenz is, whereby other usual-Hch necessary clock frequencies in the device are designated accordingly with 1 / 2SC 3SC and 6SC. The triple subcarrier frequency (3SQ often occurs because a scanning frequency equal to three times the subcarrier frequency, ie a frequency of 10.7 MHz, is used when the analog composite television signal is keyed for digitization.

It should be noted that there? NTSC television signal does not have a specific defined relationship between the horizontal sync pulse occurring in each line and the phase angle of the subcarrier signal. Only the phase of the subcarrier changes by 180 ° from line to line. In other words, the phase angle of the subcarrier signal can change relative to the horizontal sync signal from video source to video source, so that the horizontal sync signal in the device is not suitable for regulation. In the device under discussion here, the subcarrier of the input signal, as it is represented by the color sync signal component, is used as the basic timing reference for the system, with a new signal related to the horizontal sync signal being defined which is Synchronizing signal is used for timing purposes. The new signal related to the horizontal sync pulse is chosen to have a frequency equal to half the nominal horizontal line frequency because it represents an integer number of periods of the subcarrier frequency, ie two complete horizontal lines of the subcarrier frequency or 455 periods. In addition, the signal related to the horizontal sync pulse has a defined relationship to the subcarrier, ie it is synchronized with respect to the phase angle of the subcarrier. In the recording part of the signal system, a sync word is inserted into the video signal in every second television line of the video signal at a point which roughly corresponds to the point of the horizontal sync pulse, with phase coherence in relation to a certain phase angle of the subcarrier generated from the color sync signal component of the video signal is guaranteed. The new horizontal sync pulse signal is at the beginning of each picture and is maintained for the duration of the picture to ensure a horizontal sync pulse signal in the video signal that is precisely related to the phase of the subcarrier of the video signal. For the playback part of the signal system, a signal referred to as H / 2 is generated which is related to the horizontal sync pulse and is coherent with a certain phase angle of the input reference auxiliary carrier, this phase angle being selectable by the phase control in the playback system.

The H / 2 related signal H / 2 serves as the basic reference timing signal for the system in playback operations.

By using the signal related to the horizontal sync pulse as the reference horizontal sync signal for the system is the signal processing for recording, playback and others The system's operations are made easier because there is a fixed time relationship between the subcarrier of the Video signal and the signal related to the horizontal sync pulse is guaranteed.

By using internal reference horizontal and subcarrier signals that are relative to the reference sync signal of the television station are variable in time, a timing control is also possible, due to which the television signal at the right time after the usual propagation delays can arrive at a remote location.

One in the block diagram according to FIG. The encoder 96 of the video signal system shown in FIG. 1 includes circuitry, which in addition to the coding of the digitized data of the 8 video data bit lines, the parity bit and the data track sequence additional functions

executes. One of these additional functions is a parity generator to perform a parity check used to determine that the data is correct on all 8 data bit lines. The parity bit is optional and requires an additional data bit line, which is available in the arrangement described here stands. The encoder 96 also generates and effects a sync word (also referred to as line identification) its insertion. This sync word is in the form of a seven-digit binary number, soft in alternating Television lines are generally introduced where the horizontal sync pulse was previously Has. It should be noted here again that the horizontal sync pulse from the composite Video signal has been disconnected. The sync word is in a range of 16'C'der before by the Horizontal sync pulse occupied position used, the encoder 96 the sync word in each of the 8 video data lines, the parity line and the data lane line starts before the encoding is performed so that the output of the encoder 96 the sync word in each of the ten Contains data strings.

The mode of operation of the encoder 96 is illustrated below with reference to the block diagram according to FIG. 1 and the circuit diagrams according to FIGS. 2A to D described. NRZ-L data from the coding switch 126 are input via an input line 450 and can be removed from an output line 451 after firstly a parity check has been carried out, secondly the sync word has been inserted in every second (odd) line and thirdly an encoding in a format has been carried out , which is suitable for recording and reproducing digital information in connection with one of the disk stacks 75. The input data on each data bit line is applied to one input of a data input AND gate 452 which is connected to a channel encoder 453. This channel coder can be switched between two coding formats, which will be described below. In the circuit diagrams according to FIGS. 2A to D, identical channel coders for two video data bit lines are shown in their entirety. Below these coders, shown in their entirety, further identical channel coders for the other video data lines, the parity data line and the data track line are shown in dashed borders. A synchronous word input AND gate 454 in each of the ten bit lines is used to key the synchronous word into the encoder at the correct time. These AND gates are also used to insert a test signal into the ten bit lines, this test signal being supplied, if necessary, by a suitable test signal source, for example a digital test grid generator, via a line 450a (FIGS. 2A and 2B). A first clock generator 455, which receives input signals 5SC and U1SC from coding switch 126, supplies output signals SC and 2SC in the manner shown. Two of the three SC output signals are fed via lines 472 and 473 to a second clock generator 456, which supplies two 3SC clock signals offset in time on two lines 474 and 475 for clocking the channel encoder 453.The clock signal on line 475 is a Φΐ clock which is offset by half a period of 3SC from the clock signal on line 474, which is a $ 2 clock. During recording operations, these time-shifted clock signals are derived from the 65C and 1 / 25C signals with continuous phase, which are generated by the reference logic circuit t25A and sent to the encoder 96 via the coding switch 126. In the case of other operations, for example when recording the blinking cross delete signal, the reference clock generator 98 supplies these clock signals. These Φ1- and Φ2- 35C clock signals are used to control the channel encoder 453 in the sense that on the

ίο output line 451 a continuous channel-coded Digital signal is generated without phase discontinuities. The clock generator 455 delivers on an output line 471a is an SC clock signal for controlling a divider 457 which divides by 455 and which is generated by a Reset pulse delivered via a line 463 from the coding switch 126 at a frequency of 30 Hz can be reset. This divider 457 sets a flip-flop 458 via a start line 464 and sets this Flip-flop 458 returns via a pulse on a stop line 465. Define the start and stop impulses a window in which a single seven-digit Binary sync word can be inserted into all data bit lines at the same time.

A pulse is given to a monostable multivibrator 460 during the vertical blanking interval. This monostable multivibrator is active for a period of about 10 lines of the vertical blanking interval, with the vertical blanking pulse supplied by the coding switch 126 via a line 466 to an input of a Gate 461 (an OR gate in the present block diagram) is given, the other input of which is fed with the output of the window flip-flop 458. The output of the OR gate 461 is to the other input of the AND gate 454 and via an inverter 462 also to one Input of AND gate 452 given.

During operation of the encoder 96, the data sequence for each bit is to be sent to an input, for example the Input line 450, which represents one of the 8 separate data input lines, wherein these lines to a respective encoder 453 and the associated AND gates 452 and 454 and the Inverter 462 are coupled. A data output line 451 is also provided for each data bit, so that the data sequences can be coded correctly and the synchronous word can be used. Since that Synchronous word used very close to the point of the previously existing horizontal synchronizing pulse should be and since no disturbance should occur with the data of the data sequence, the to the Channel encoder 453 leading data bit lines during the insertion of the sync word in the by the divider 457 and flip-flop 458 generated by the data input gates 452 disabled Specifically The divider 457 yeasts a start pulse to set the flip-flop 458, creating an input to each AND gate 454 is activated, while at the same time each AND gate 452 is blocked, thereby blocking data entry over lines 450. Twelve data bit intervals after the To generate the start pulse, the divider 457 supplies a pulse for the synchronous word generator 459, which then generates a seven-digit binary word that is fed to the top input of all AND gates 454 that have already been activated. These AND gates 454 enter the sync word into the Channel encoder 453 in which it is in the data folder

is coded. The divider 457 delivers a stop pulse 29 data bits after the synchronization word has been generated to reset the flip-flop 458, whereby all AND gates 454 are blocked and all AND gates at the same time 452 can be activated so that the data on lines 450 in the channel encoder be fed in. It should be noted that the data is continuously on lines 450 and that blocking the AND gates 452 merely blocks their continuation. During the insertion of the synchronous word, the information is deleted in a certain sense. Since the sync word, however at the point of the previously existing horizontal sync pulse no active video information is lost.

During the vertical blanking interval, the yeasts monostable multivibrator 460 an output signal for the OR gate 461, which is for an interval of about 10 Lines is present. This will make the data input AND gates 452 locked during an interval of 10 lines of the blanking period, so that the channel encoder received no information during this interval. The only data or logical "1" bits which occur on output lines 451 during the 10 line interval of the vertical blanking interval, are those in the sync words which, as already described above, are in every second line occur and pass through sync word gates 454. This ensures that the decoding and Time base correction circuit 100 does not respond to an arbitrarily occurring sync word bit pattern during playback, but is set to the actual synchronous word. An arbitrarily occurring sync word bit pattern can be present in the active video information during the data flow.

The in the F i g. The channel coders 453 shown in FIGS. 2A to 2D operate according to certain code rules. F i g. 2E FIG. 4 shows a timing diagram to explain the mode of operation of the in a data bit line 450 contained channel encoder 453. If the switch 480 is in the position shown in FIG. 2B, encode the position Channel encoder 453 the data according to the code rules according to DE-OS 27 11 526, while the data in the other position of the switch according to the code rules of US Pat. No. 31 08 261 are coded.

The channel coder is described below in connection with the one shown in FIG. 2B position of the code selection switch shown 480, the channel coding of one of the data bit sequences according to the code rules is coded according to the above DE-OS 27 11 526. An explanation of the differences in how the encoder works when switch 480 is in the other Position is, with a coding of the data bit sequence according to the code rules according to the above US Patent 31 08 261 is given below.

As already stated, it is for data encoded according to the rules according to DE-OS 27 11 526 mentioned required to examine two consecutive data bits to be encoded when counting modulo 2 of previously encoded logical ones is odd. To this end, each channel encoder 453 includes a pair of input flip-flops 481 and 482 connected in series, soft through the positive trailing edge of the $ 2-3SC clock signals (Fig. 2E- (2)) are clocked on line 474a, with the latter line being over an inverter 483 is coupled to line 474. The two input flip-flops cause between the input of flip-flop 481 and the output of flip-flop 482 a delay of 3 bit cells. at every positive trailing edge of the $ 2 clock pulse is the existing data level of the bit sequence at the input of the Flip-flops 481 clocked through to its output (FIG. 2E- (3)), with the one contained in the flip-flop 481 previous data level of the data sequence clocked from the input of the flip-flop 482 to its output becomes (Fig.2E- (2), (3) and (4)). Therefore, the

ίο output signals of the flip-flops 481 and 482 to encoding data bits of two consecutive bit cells.

The outputs of the flip-flops 481 and 482 are to the inputs of three NAND gates 486, 487 and 488 out to forward logical ones and logical zeros in the data bit sequence corresponding pulses separately. NAND gate 486 receives three inputs. This is the output signal of the flip-flop 481, the output signal of the flip-flop 482 and the Φΐ clock pulses (Fig. 2E- (I)) on the Line 475a supplied by an inverter 484 from the output line 475 of the clock generator 456 will. This NAND gate is activated to always generate an output pulse 489 (F i g. 2E- (6)) to be supplied when recording a Φ1 clock signal if the other inputs are at a low level. This is only the case if successively received data bits are logical zeros. That NAND gate 486 thus supplies pulses related to a logic zero, which are encoded by jumps in the Format of the data sequence at the output of the channel encoder 453 are marked. A zero bit that immediately follows a One bit follows, the NAND gate cannot go through because the flip-flop 482 is high, for example if a ΦΙ clock pulse 490 (Fig. 2E- (I)) occurs. Of the Channel encoder 453 thus works according to the code rules according to the above-mentioned US Pat. No. 31 08 261 for successively occurring zero data bits.

On the other hand, the NAND gate 487 has two inputs and is activated for all logical zero data bits when a Φ 1 clock signal is received to deliver an output pulse (FIG. 2E- (5)). Since the output signal of the flip-flop 282 activates the NAND gate 487, a data cell is generated after the data has been clocked into the channel encoder 453 based on the logic zero-related pulses.

The NAND gate 488 has three inputs and is activated when a $ 2 clock signal for all logical one data bits is received by the inverted output signal of the flip-flop 482 to generate an output pulse (FIG. 2E- (7)), if it is not is blocked by a high level bit suppression pulse 491 (Fig.2E- (IO)) on a line 492 coming from a bit suppression NAND gate 493. NAND gate 488 generates logic one related pulses during the interval of the Φ2 clock signal. This is the case before the flip-flop 482 is clocked by the positive trailing edge of the Φ2 clock signal. The pulses related to the logic one are supplied by the NAND gate 488 one data cell after the data has been clocked into the channel encoder 453 via the flip-flop 481
A two input OR gate 494 receives the logic zero related pulses 489 (Fig. 2E- (6)) generated by the NAND gate 486 according to the code rules of US Pat. No. 3,108,261. Continue to take this

OR gates the logic one-related pulses 515 (Fig. 2E- (7)) which are triggered by the NAND gate 488 can be supplied. The output of OR gate 494 appearing on the output line 451 occurs, is therefore a sequence of pulses (Fig. 2E- (H)), which according to the code rules for the Channel coders are generated. NAND gates 486 and 488 serve in conjunction with OR gate 494 that is, to encode the incoming NRZ-L data stored by the flip-flops 481 and 482 in the selected channel code format. The NAND gate 487 operates on one to be described below Bit suppression logic together to selectively suppress the data bit related to the one Control jump in the channel-coded data. By blocking the bit suppression logic 500 due to a changeover of the switch 480 from the position shown in FIG. 2C, the NAND gates 486 code and 488 the data according to the teaching of US Pat. No. 3,108,261.

To encode the data bit sequence according to the teaching of the above-mentioned DE-OS 27 11 526 contains Bit suppression logic 500 two modulo-2 counters 495 and 496 for counting the coded logical ones and Zeros, the bit suppression command on the line in conjunction with gate circuits 492 is generated, the selective one-bit related jumps in those occurring on line 491 channel-coded data suppressed. The modulo 2 counter 495 counts the pulses related to the logic zero which are sent through the NAND gate 487 to his Clock input can be coupled. The ones supplied by the NAND gate 488, related to the logical one Pulses are entered into the clock input of the modulo-2 counter 496 for counting. The counter 495 recognizes the beginning of each sequence by toggling it as a function of pulses related to the logic zero every time a logical zero is encoded, being released every time a on a logical one A related jump is suppressed. As can be seen from the code rules explained above, tilts the counter 495 twice during a sequence of the second type and never during a sequence of the first type so that it is in its enabled state before the start of each sequence. the Bit suppression logic 500 must detect the end of a sequence of the third type. The modulo 2 counter 496 serves to toggle as a function of the logic one when performing this function related pulses every time a logical one is encoded, whereas when a logical one is encoded Nuii ais function of the pulses related to the logic zero is enabled. The signal trains (8) and (9) according to FIG. 2E explain the corresponding operations of modulo-2 counters 495 and 496 when their Outputs are not combined in an OR connection 501. The signal train (13) according to FIG. 2E shows the actual conditions at the OR connection 501. From the explanations above the result is that the counter 495 is in its enabled state when the counter is 496 is not in its shared state. The existing bit to be coded is a logical one and the next bit a logical zero, the bit suppression command being replaced by the NAND gate 493 is provided on line 492 to disable NAND gate 488, the Coding of the existing logical one-bit is suppressed.

In connection with the gate circuits to control the release of the two modulo 2 counters 495 and 496, the set input of counter 496 is coupled to NAND gate 487 so that its output signal is high every time a pulse related to the logic zero is used as an output signal from NAND gate 487 is asserted. The set input of the counter 495 is connected to the output of a NAND gate 497 coupled so that its output is high every time a on the logic one related jump in the channel coding of the data bit sequence is suppressed. As can be seen from the following Explanations still results, is in the output circuits of the modulo-2 counter 495 and the NAND gate 493 Pair of capacitances 498 and 499 switched on to the logic occurring at the OR connection 501 To delay the setting level of the counter 495 and the bit suppression command from the NAND gate 488 to remove.

The bit suppression command is generated by the NAND gate 493, which the first bit of successive data bits to be coded, which is present in inverted form at the output of the flip-flop 482, the next bit of the successive data bits to be coded, which is at the output of the flip-flop 481 is available, and the counter readings of the modulo 2 counters 495 and 4% are examined. If one of the counter outputs on OR connection 501 is high, the NAND gate is blocked. If, however, the beginning of a sequence of the third type occurs, then both counters 495 and 496 are low, so that an effective switching signal arises at the input of the NAND gate 493. If the next two bits to be coded are a logical one followed by a logical zero, the bit suppression command 491 on line 492 is activated when the Φ 2 clock pulse 502 (FIG. 2E- (2)) occurs immediately before the Φΐ clock pulse 490, whereby the formation of the pulse related to the logic one via the NAND gate 483 is effected. If the Φΐ clock pulse 490 (FIG. 2E- (2)) occurs on line 474, whereby NAND gate 488 generates a pulse related to the logic one, then NAND gate 488 is activated by the bit suppression instruction on the Line 492 blocked, so that the pulse related to the logic one is suppressed. This is shown in the signal train (14) according to FIG. 2E indicated by pulses 512 shown in dashed lines. The bit suppression command is terminated when the counter 495 is set.

The set pulse 505 (Fig.2E- (12)) is triggered by the NAND gate 497 as a function of bit suppression command 491 (Fig. 2E- (IO)) on line 510 and the above-mentioned Φΐ-clock pulse 490 generated, which around half a period of the frequency 3SC after the <P2 clock pulse or about 47 nanoseconds later occurs. To ensure that the counter 495 is not set and that the suppress bit command is not removed is until the Φ1 clock pulse 490 is finished, are the Delay capacitances 498 and 499 are provided to cause the counter 495 to return to its high level To delay the set level, thereby holding the NAND gate 493 off, and to allow the return of the NAND gate 493 to its low-lying shutdown level, thereby reducing the duration of the bit suppression command 491 is extended. The effect of this delay is from the course of signal curves 508 and 509 in the signal trains (10) and (13) according to FIG. 2E can be seen.

To disable the Bitunterdrückungslogik 500 ■ the switch 480 is switched ir · the position in which a Signa! with a high level (ground in the channel encoder 453 of this device) on the set line 510 for the counter 495 is generated. As a result, the counter is permanently brought into its set state, as a result of which the input of the NAND gate 493 receives a switch-off signal with a high level from the OR connection. Therefore, bit suppression commands 491 cannot be generated, so that no bits are suppressed either.

Usually self-clocking contain data code formats Data and clock information as specially placed jumps between two signal levels. If such Coded data being transmitted over a transmission channel occurs because of its non-linear characteristic of most transmission channels have a certain timing distortion. This timing distortion falls weight, errors can occur because the decoder has the correct position of the transmitted jumps can not determine. In addition, the timing distortion can occur with large data such as the device in question can lead to unacceptable errors in the transmitted data to lead. This is particularly the case when jumps directed in opposite directions include data and timing information as it occurs in the codes for this device. Change non-linear transmission channels the positive and negative jumps in a non-linear manner with respect to time. Hence, in the end of a transmission channel usually level-sensitive data detectors are used to detect the transmitted Process data in such a way that they have correctly positioned jumps. The positive and negative jumps are positioned differently. The different positioning occurs because a positive one Jump with considerable timing distortion is the one chosen to determine the presence of jumps Level reached at a time after its nominal location. This level is different from the level that is required for a correspondingly distorted negative jump.

To the reliability of the transmission of the coded data, ir. Those directed in opposite directions Each channel encoder 453 encodes the jumps that carry data and clock information Data bit sequence at its input by generating pulses according to the rules of the selected code Jump points of the coded format. In the channel encoder used specifically for this device are logic one related pulses 515 (Fig.2E- (7)) and (14) at the data line boundaries is generated to define logical one related hops which occur in the encoded data. on the logic zero related pulses 589 (Fig.2E- (6)) and (14) are generated in the center of a data cell, to define logical zero related jumps occurring in the encoded data. the Jump-related pulses are generated by the clock generator 456 to produce well-defined edges

ίο obtained with the trailing edge selected. This second clock generator 456 contains two monostable multivibrators 456, which by the antiphase, 35C clock signals supplied by the first clock generator 468 via lines 472 and 473 are clocked.

Since the leading edges of the positive pulses generated by the monostable flip-flops 456 through rapid switching of the flip-flops from their stable state to their quasi-stable state are defined (es if no significant components determining the time constant are involved), every leading edge is identical to all others and occurs at an exact point in time following the occurrence of the positive surge of the clock signal. The two flip-flops 456 therefore provide Φί- and Φ2-Τ8Μπιρυΐ5ίο1-gen, which in the present embodiment have a pulse width of about 17 nanoseconds, wherein the leading edges of the pulse trains with respect to each other and with respect to the pulses of the respective other pulse train are precisely defined. As stated above, the Φ1 clock pulses on the Line 475 clocked as pulses through NAND gate 488, which is based on the encoded data logical ones are related. The <P2 clock pulses supplied on line 474 are referred to as jump-related Pulses clocked by the NAND gate 486, these jump-related pulses being encoded in the Data occurring zeros are related. Since the NAND gates 488 and 486 are effective at times are connected, in which the Φί and Φ2 clock signals for

Transmission as jump-related pulses are received (Fig. 2E- (4), (7) and (14) for one-bit pulses and F i g. 2E- (3), (4), (5), (6) and (14) for zero-bit pulses), their corresponding leading edges are not noticeable through the transmission via the NAND gates

■ »5 influenced. Since the transmission channel over which the Pulses are transmitted, acts the same on identical pulse edges, go to the more precise positions of the jump-related positive pulse edges and thus the data signal jumps themselves due to distortion, which the impulses can suffer through the action of the transmission channel are not lost.

In addition 6 sheets of drawings

Claims (5)

Patent claims: 1. Arrangement for the selective insertion of a digital synchronization word in at least one digitally coded data sequence clocked at a predetermined frequency to an input, which occurs at an output with the synchronization words selectively inserted therein, each data sequence containing a component of the digital form of a composite video signal and wherein the composite video signal comprises a color subcarrier, a horizontal blanking interval associated with each video line, and a vertical blanking interval separating successive video frames, and wherein horizon sync pulses are removed from the horizontal blanking interval, characterized by a generator (459) for generating a multi-bit digital sync word for insertion into each data sequence for the purpose of identifying alternating lines, a switch arrangement (452) which, in a first switching state, blocks the forwarding of the data sequence to the output, but the (450) fed Datenfolgefluß is not stopped in the input, so that the thereby occurring information content of the data sequence is deleted, an arrangement (457, 458, 461, 462) first to the actuation of the switch arrangement (452) for the purpose of erasing the information content of the data sequence in a Time period in at least a part of every second horizontal blanking interval and for the purpose of activating the synchronization word generator (459) in order to insert the synchronization word into the data sequence during the first time period, and an arrangement (460, 461, 462) for actuating the switch arrangement (452) for the purpose of deletion the information content of the data sequence in a second period of time occurring in the vertical blanking interval and extending over a plurality of successively occurring horizontal blanking intervals. 2. Arrangement according to claim 1, characterized in that both the synchronization word generator (459) al «and the input (450) are coupled to the switch arrangement (452) and that the switch arrangement (452) in a first switching state the data sequence from the output (451) blocks and lets through the synchronization word from the generator (459) and, in a second switching state, lets the data sequence through to the output (451) and blocks the synchronization word supplied by the generator (459). 3. Arrangement according to one of claims 1 to 2, characterized in that the second Period of time extends over a number of consecutive horizontal blanking periods, which less than about half the horizontal blanking periods occurring during each vertical blanking interval is. 4. Arrangement according to one of claims 1 to 3 for processing an analog color video information signal for recording on a magnetic medium, characterized by an arrangement (93a ^ for separating the horizontal sync pulses from the analogue color video information signal, an arrangement (95) for sampling the analog color video information signal and transferring it the sample values in said at least a digital data sequence with a specified data sequence frequency, which is equal to a multiple of the chrominance subcarrier frequency, where the synchronization word is synchronized relative to the chrominance subcarrier so that the phase relationship is constant between the sync words and the chrominance subcarrier. 5. Arrangement according to claim 4, characterized in that the synchronization word beginning Arrangement (96) the multi-bit synchronization word in the area of the previously separated Horizontal sync pulse sets in the data sequence.