DE2759867C2 - Arrangement for digitizing an analog information signal in a predetermined phase relationship with a reference signal - Google Patents

Description

55

The present invention relates to an arrangement for digitizing an analog, in a given Phase relationship to a reference signal standing information signal according to the preamble of Claim 1.

Such an arrangement is common in transmission systems and in recording and reproducing devices and especially in devices for recording and reproducing television signals using digital signals Techniques usable.

Ongoing technological advances have resulted in numerous changes in devices that are used in TV broadcasting stations are used. One of the more significant changes is that photographic techniques in favor of magnetic media in many commercial television broadcasting locations were abandoned. For example, films that are broadcast often no longer come from you Film strip but from a magnetic tape. News departments of television broadcasting stations also go mostly to video tape recording systems; for the visible representation of new News, movie cameras are being pushed back more and more in addition, they are often moving Take advantage of transmission stations, which send information either directly from their location or transmitted to a station from which the information is either broadcast live or on video tape recorded, edited and broadcast at a later date. One of the many advantages such a method is easy in handling, flexibility and processing speed insane Compared to a photographic. Watch film. These benefits are with the possibility coupled to being able to use the magnetic tape again if the information recorded on it is not takes longer.

One of the last remaining domains of film in today's commercial television broadcasting stations is Image projection using 35 mm film transparencies. This image projection is used for extraction of still television pictures, which for example for program information, advertisements and news be used. In general, the aforementioned option is used wherever there is a standing picture is necessary. The effort for such Image projections are evident from the fact that a medium-sized commercial television broadcasting station has one Total stock in the order of about 2000 to 5000 slides with 35 mm leads. The maintenance such a GesaEitbesti, .ides requires one a lot of work, including the introduction of new slides, the sorting out of bad slides and the permanent maintenance of an exact listeria-like compilation makes necessary so that slides are easily accessible when needed. Should If program sequences are compiled from such slides, the individual slides must be carried by hand to the projection device, cleaned and inserted manually. Alone during the cleaning process For example, dust particles and scratches can be unsatisfactory even with careful handling Produce results. In addition, after they have been used, the slides must be sent for broadcasting purposes removed and returned to their storage location. The whole process of putting together the use for broadcast purposes and the return of the slides due to the associated associated manual activities require a large amount of work. The projection history is in many modern ones Broadcasting stations are to a large extent outdated and fundamentally with fully automatic station operation incompatible.

Generally speaking, the arrangement in which the invention may be used makes contrary to Projection equipment or the use of opaque graphic material as a source for generation of still video images, recording and playback of still images is possible, with the video information in the form of still images

stored on magnetic media. There are generally computer-controlled standard disk drive units (which, however, have been modified in certain aspects are) usable with magnetic storage media, which means that with the projection of slides related problems are avoided. Since the still images are recorded on magnetic media there are problems of mechanical impairment, for example due to dust particles or by Kratzei not up. As the information recorded Still easily accessible, the same still image can be viewed by operators at different Places can be used practically at the same time.

In this context, the present invention is based on the object of providing an arrangement for Specify digitization of an analog information signal, the digital sample values of which have a predetermined Adhere exactly to the phase relationship between the information signal and a reference signal.

In an arrangement of the type mentioned at the outset, this object is achieved according to the invention by the features of the characterizing part of claim 1 solved

It is generally known (for example from "Der Electronicsiker" 12 (1973), No. 1, pages EL 14 to EL 19), to use phase-locked loops (so-called PLL circuits) for phase-locked synchronization. It remains however still a phase error. This is also special (for example from »PAL color television technology« by F. Möhrung. Prien 1967, in particular pages 73, 124, 125, 129) known for television technology, with however, the residual phase error problem also remains.

In particular, a video information signal with a repetition frequency is generated by means of the arrangement according to the invention keyed, which is a multiple of the subcarrier frequency, so that during each period of the subcarrier a number of samples is obtained. According to a particular embodiment, the keys the video information signal with a repetition frequency, which equal to three times the subcarrier frequency, so that three sample values for each period of the subcarrier, d. there Phases of 0 °. 120 ° and 240 ° can be obtained. Since the phase of the sample values relative to the subcarrier in a color video information signal corresponds to the color value of the Video image determined during playback, the keying leads of the information signal in other than the exact phase positions ultimately leads to poor color reproduction.

The arrangement according to the invention ensures that the sample values can be obtained precisely in the desired phase positions, so that the color in a subsequent Playback is correct. In the arrangement, keying is carried out as close as possible to the preferred phase positions, d. That is, in a range of about 20 ° around the desired key positions of 0 °. 120 ° and 240 ° in the exemplary embodiment a phase-locked loop is used. This effectively corrects all errors, which can occur due to a temperature drift and corresponding effects.

Refinements of the inventive concept are characterized in the subclaims.

The invention is described below with reference to the exemplary embodiments shown in the figures of the drawing explained in more detail. It shows

F i g. 1 is a perspective view of a device with a device's own output device and two disk drive units. from which the overall appearance of the device can be seen;

Fig. 2 is an enlarged perspective view of a representative remote input device used by an operator to control the functions of the Device is usable;

F i g. 3 shows an enlarged plan view of the keyboard field of the device's own input device according to FIG. 1 in particular the various keys and buttons that can be actuated by an operator can be seen are;

F i g. 4 shows a simplified block diagram to explain the general functions of the entire device; F i g. Fig. 5A shows part of a typical television signal for explaining its vertical interval;
F i g. 5B shows part of a color television signal, from which in particular the horizontal sync pulse and the color sync signal can be seen;

F i g. 6 is a block diagram to explain the basic mode of operation of the signal flow path through the device during a recording operation;

F i g. 7 a block diagram for a general explanation the signal flow path through the device during a playback operation;

F i g. 8A and SB are a block diagram of the signaling system for the device including the control connections between the various blocks;

F i g. 8C is a timing diagram to explain the sampling of a television signal and the phase relationships at various points in the signaling system; F i g. 9 is a block diagram of a video input circuit (similar to a reference signal input circuit) which forms part of the signal system according to FIG. 8A forms;

10A is a block diagram of a reference logic circuit, which forms part of the signal system according to FIG. 8A;

Fig. 10B is a timing diagram for a PAL error flag generator in the reference logic circuit according to Fig. 1OA;

FIGS. HA to HD are a circuit diagram of the input circuit of the signal system according to the block diagram of FIG. 9; and

Figures 12A through 12D are a circuit diagram of the reference logic circuit of the signal system according to the block diagram according to Fig. 11th

Generally, Hn includes recording and reproducing devices 70 according to FIGS. 1 to 3 two racks 71 and

72, which contain the associated electrical circuits as well as the display and control hardware. the The latter components are shown in particular in the upper part of the frame 72. The device has furthermore a pair of disk drive units ^ n

73, which are arranged next to the right frame 72, each disk drive unit 73 a Disc stack 75 carries. In addition to the two disk drive units shown specifically in FIG. 1, further disk drive units can be assigned to the device in order to reduce its direct storage capacity to increase. On the other hand, only one can also be used Disc drive unit can be used. However, as can be seen from the following explanations, A single disk drive unit can be used will. Operators can control the operation of the device via several remote input devices, such as a remote input device 76 of FIG. 2 or via a device's own provided in the frame 72 Input device 78 are performed. In the frame 72, a video monitor 79 and a

Vector and an "A" oscilloscope 80 may be provided. Above the device's own input device 78 are Phase control switch 81 is provided.

The device is by an operator either via the device's own input device 78 or a Remote input device 76 controlled, which each digit and function buttons and keys and a display panel 82 for thirty-two characters. With this display field is the reading of information which is necessary to carry out the functional operations in operation, as well as the display of the information possible, which affects the identity of certain addressed still images and other information. The remote input device 76 shown in Figure 2 is representative for all remote input devices, with up to seven remote input devices to control the device 70 can be provided. The in Fig. 1 keyboard field of the device's own, generally designated 83 Input device is in Γ i g. 3 in a vcrgroiJcrtcn Tci! - view shown. This keypad is functionally more extensive than the keypads of the remote input devices, which have fewer function keys. As will be explained in more detail below, contains the keypad has a larger key matrix 84 and a smaller matrix of function keys 85 on the left side of the keypad. Furthermore, a switch 86 actuated by a rotary knob can be provided with which a switchover between normal and extinguishing mode is possible. With that there is a security against the possibility of incorrect or unauthorized deletion of actively used still images possible.

According to the greatly simplified block diagram of FIG. 4, the device receives an input video signal which is processed by a recording signal processing circuit 88 and then fed to a recording .SignakchnitiRteüe 89, which feeds the signal to all disk drive units 73. A gate circuit provided in each specific disk drive unit 73 is activated to record the signal on a predetermined disk drive unit. For recording the signal supplied by the recording signal interface 89, more than one disk drive unit 73 can also be selected at the same time. Instead of the signal interface and the associated gate circuit, switch circuits can also be provided in order to only couple the signal supplied by the recording signal point 89 to a specific disk drive unit with disk stacks 75 on which the signal is recorded. During playback, a signal coming from one of the disk drive units is fed into a playback circuit 90, which couples it to one of several playback channels 91, which each form a video output channel. To control the overall operation of the various components of the device, a computer control system 92 is coupled to the recording signal processing circuit, the recording signal branching circuit and the drive units as well as the remote input devices and the device's own input device Select specific disk on which an image is to be stored, provided that the disk stack is connected, i.e. in other words it is inserted into one of the disk drive units 73. In this connection it should be noted that the device addresses disk stacks and not disk drive units in that the device is used to identify up to 64 separate stacks of discs, only one of which can be placed in a disc drive unit at a time. If the device has two disk drive units, only two disk stacks can be connected at the same time. The operator can use a keypad 83 of an input device to enter, with the assistance of the computer system, the address of a stack of discs on which an image is to be recorded, the disc drive unit in which the selected stack is inserted can perform the recording process on the selected, connected stack of discs . In a corresponding manner, an operator can reproduce an image from the stack of panes in a drive unit and define the reproduction channel through which the image ■ ... (-_ "ιι

1au11.11 axjtt.

The device has four main modes of operation, namely 1. Record / Erase, 2. Play or Playback, 3. Sequence Composition and 4. Sequence Playback. First, the recording and reproducing operations will be described with reference to Figs. 6 and 7, which show simplified block diagrams of the signal flow paths during recording and during playback in cooperation with one of the disk drive units 73. According to the recording signal flow block diagram of FIG. 6, the composite video input signal is fed to an input circuit 93, in which this signal is clamped and the synchronous and subcarrier components are separated. The synchronous and subcarrier signals are also recovered in the input circuit for later use during playback. The recovered synchronous and subcarrier signals are fed into a clock generator 94, which generates reference signals for controlling the following components. The clamped analog video signal with the color synchronous component is fed into an analog-digital converter 95 which ^{generates an output signal with a sampling frequency of 10.7 χ 6} samples per second, each sampling comprising eight information bits. The digital video signal is in an NRZ Codc, ie it is a binary code which is defined by a one as the high level and a zero as the equivalent low level. A signal level voltage occurs between the low and high levels when different digital data bits appear in successive data cell intervals. The digitized video signal appears on eight parallel lines with one bit per line and is fed into a coding and synchronizing word input circuit%, which converts it into a special recording code. This code is referred to below as the Miller code or Miller ² code. This code is particularly suitable for a digital magnetic recording, since the DC voltage content of a data stream is minimal in it. This sync word serves as a reference for the correction of time base and skew errors that occur during playback in the eight parallel data bits that have to be combined to determine the value represented by each keying. The digital video information in the eight parallel lines is then converted into

c a recording amplifier circuit 153 and fed to a head switch circuit 97 which is associated with the selected disk drive unit 73 and switches between two groups of eight recording heads for recording the digitized video signal by the disk drive unit. The disk drive unit is servo-controlled so that its shaft speed is related to the vertical synchronizing signal V, r. the disk speed is 3600 revolutions per minute. By setting the shaft speed to the vertical synchronous signal, the device records one half-image per revolution of the stack of discs and, at the same time, eight data sequences on eight disc surfaces. After a field is completely recorded, the record amplifier circuit 153 and head switch circuit 97 are controlled to activate another set of heads to simultaneously record the second field on another set of eight disk faces so that

Cin ι CrnSCiiLriiu, u. It. ZtVCi VCrSCiiaCiitcitc ι idiuL / iiuci ",

can be recorded by 16 heads at two revolutions of the disk drive unit. Each disk stack on a disk drive unit preferably contains 815 cylinders, each of which has 19 recording areas and therefore can store 815 digital television pictures. A read / write head is provided for each of the 19 disk recording surfaces of a disk stack, with all heads being mounted vertically aligned on a common carrier, the position of which is regulated by a linear motor. It should be noted in this connection that a cylinder is defined in such a way that it encompasses all recording surfaces which are arranged on the same radius of a stack of disks. Instead of the term cylinder, however, the term track is preferably used in the present context, which means that such a track comprises all recording surfaces on the same radius, ie all surfaces of a cylinder. Therefore, the term addressed track for recording or reproducing an image refers to the 19 individual areas on the cylinder present in this radius. Of the 19 areas available for recording, one is used to record address and other identification information and not to record active video information. This area is specifically referred to as the “data track”. Two of the 19 areas are available for recording a parity bit, while 16 areas are available for recording the image of the video data. This fact is explained in more detail below. Likewise, one of the heads, referred to as the servo head, runs on the twentieth disk stacking surface which only contains servo track information prerecorded by the stack maker. The servo tracks are used to perform two functions. First, following a search command, the head track runs through servo stages, which are counted to determine the eye position of the heads. After the end of a search phase, the servo head generates an error signal which is used to regulate the linear motor position in order to keep the head carrier centered on the appropriate servo track. When using such a feedback system, it is possible to achieve a radial packing density of approximately 400 tracks per inch or a total of 815 tracks per stack of discs.

Since the device in question is not analogue due to the frequency limits of stacked disks Records video signals, the video signal is digitized for recording. As this digitized signal is recorded, the signal-to-noise ratio of the system is primarily due to the quantization noise and not determined by the noise of the recording media and the preamplifier, as is the case with conventional ones Video tape recorders. The device in question ensures a signal-to-noise ratio of about 58 dB, with effects such as

ίο For example, moire and residual time base errors are not are present so that the digital statistical error of the memory channels is typically small enough to be to make possible transmission errors virtually invisible.

By recording a digital data sequence with a repetition rate of 10.7 megabits per second Each of the eight disk areas, the linear packing density of the device is roughly equal to 6000 bits per inch, which is around 60% more than the packing density in the case of conventional Schciberiäniriebsciriueiieri in Daicnveraibeiiung lies.

During playback, read according to FIG. 7 the heads extract the digital video information from eight areas per field, the recorded coded digital video information per channel being obtained from two fields representing each image. The reproduced signal is fed to a reproduction amplifier circuit 155 and head switch circuit 97 associated with the selected disk drive unit 73, the data sequences of the digital video information carried through the eight data bit lines being amplified and fed to an equalizer and data detector circuit 99. The equalization part of this circuit compensates for phase and amplitude distortions in the signal due to band limitation effects of the recording and reproduction processes, whereby it is ensured that the zero crossings of the reproduced signal are precisely defined. After equalization, the coded signals on each data bit line of the channel are processed in a manner to be described below for transmission to the playback circuit of the signal system via a twisted pair of lines. The processed coded signals are available per channel in the form of a pulse for each zero crossing or for each change in the signal state of the coded channel signal. The twisted wire pairs for the eight data bits of the digital video information carry the processed coded channel signals to a decoding and time base correction circuit 100 of one or more of the playback channels 91 of the device. The decode and timebase correction circuit 100 converts the received signals back to channel code format, decodes the signal into N RZ digital form, and timesbases the digital signal with respect to a station reference signal in order to correct timing errors between the data bit lines (usually as To eliminate skew errors) and timing distortions in the data sequences carried through the data bit lines. In order to facilitate the processing of the reproduced signals, phase-continuous clock signals are used for the timing of the decoding and time base correction circuit 100 and the following circuits. This per se prevents the time base correction part of the circuit 1! OO from correctly setting the sync word when the picture is displayed alternately. The time base correction part of the circuit 100 is therefore used to correct

door of the eight bits in the sense of a single keying as well as to eliminate time distortions in the individual data bit lines relative to the station reference signal. The so-called incorrect setting of the sync word would lead to a horizontal shift of the picture with alternating displays and to a visible flicker. It should be noted that each playback channel 91 contains an equalizer and data detector circuit 100 and that in each playback channel a sequence of eight data bits passes through a separate equalizer and data detector circuit. The output signal of the circuit 100 is then fed into a comb filter and chroma inverter circuit 101 , which separates the chroma information and selectively inverts and recombines the signal to reconstruct an NTSC frequency with four fields. This reconstructed digital signal is fed into the circuit 127 (see FIG. 8A), which adjusts the incorrect setting of the sync word when the two recorded fields of the video information are reproduced alternately, and then fed into a digital-to-analog converter 102 , which supplies an analog video signal. In order to generate a composite analog video output signal of the playback channel 91, new synchronous and color synchronous signals are then added by a processing amplifier 103.

Compared to the above explanation of the signal flow paths for both recording and playback operations the signal processing system for the composite television signal is far more complex than this is shown by the signal flow circuits according to FIGS. The video signal system is referred to below the block diagrams according to FIGS. 8A and 8B described in more detail. As far as possible, be for yourself corresponding functions the reference symbols already selected above are also used. The block diagrams Figures 8A and 8B also include more lines to represent the flow of video data through the Signal system and other connecting lines, which are used to control the timing and synchronization the circuit given by the various blocks. The corresponding input and output lines for the various blocks in Figs. 8A and 8B relating to the computer control system 92 (see Fig. 4) are marked by an asterisk.

The device is described here in connection with the NTSC system, in which a television picture has 525 lines and the horizontal synchronizing pulses occur with a repetition rate of about 15.734Hz, ie the period between successive horizontal synchronizing pulses is about 63.5 microseconds. Furthermore, the vertical blanking frequency in the NTSC system is 60 Hz, the chrominance information being modulated onto a subcarrier with a frequency of approximately 3.58 MHz. The subcarrier frequency of 3.58 MHz is also referred to simply as SC in the following, which means the simple subcarrier frequency, with other clock frequencies usually required in the device being correspondingly referred to as 1/2 SC, 3 SC and 6 SC . The triple subcarrier frequency (3 SQ often occurs because a sampling frequency equal to three times the subcarrier frequency, i.e. a frequency of 10.7 MHz, is used during the keying of the analog composite television signal for its digitization. The composite video signal of an NTSC system is in the Figures 5A and 5B

Before a detailed description of the block diagram according to FIG. 8A are intended to do some basic Comments on the overall function of the signaling system shown are made. That into the video input circuit 93/4 video input signal is initially an analog signal that is used for further processing is fed into the analog-to-digital converter 95. The output signal of this converter contains the Video information in digital format, the digitized data being further processed and in a digital format Format can be recorded on a stack of discs. The signal from the stack of discs is also sent in this form reproduced, corrected with regard to the time base and a separation of the chroma component carried out, whereby the processing takes place in digital technology. The return to an analog signal is successful: not until the final signal processing steps are carried out, in which case the digital AriäiogkonVcrici ' As well as Sciiäiiüngeii 102, 103 ^ Ui Eniiügung of sync signals and color sync signals, the analog composite video output signal deliver.

In the analog-digital converter 95, the analog composite video signal is sampled three times per subcarrier basic period, ie with a sampling frequency of 3 SC (10.7 MHz), each sampling value being digitally quantized into an 8-bit digital word. A duty cycle at three times the frequency or any odd multiple of the NTSC subcarrier frequency is necessarily an odd multiple of half the horizontal line frequency. If such a key clock signal is phase-steady from line to line, its phase changes at the beginning of successive lines. If such scanning clock signals, which are phase-constant from line to line, are used, the instantaneous amplitude of the analog signal is scanned at different times during successive lines relative to the beginning of the successive lines. For this reason, the quantized sample values are vertically shifted from line to line. A vertical alignment of the sample values from line to line is desirable in order to facilitate the use of a digital comb filter which is used to obtain a separated chrominance component of a television signal by quantizing sample values from three consecutive lines of a television field (only odd or only even fields ) can be combined with each other. These three consecutive lines can be designated with 7 ~ (for the upper edge of the picture), M (for the center of the picture) and 8 (for the lower, picture edge), whereby the following relationships apply:

(Chrominance) C.
(Luminance) Y

M- 1/2 (T + B) M + 1/2 (Τ + B)

Are the samples of the NTSC television signal with an even multiple of the subcarrier frequency carried out, the comb filter technique is ideal, since the phase of the key clock signal does not vary from line to line changes. The digital code words or the quantized sample values then describe the instantaneous amplitudes each line of the analog signal at the same points in time relative to the beginning of each line, with all sample values aligned in successive lines vertically from the upper edge of the image across the center of the image to the lower edge of the image are.

The lack of a vertical alignment of the sample values of successive lines when using a

ncs vow line to line phase-steady tactile clock signal with a frequency of 3 SCkani) using the signal diagram. F i g. 8C (1) by showing several periods of the subcarrier in a television line 1, which are sampled by the positive jump of a sampling clock signal with a frequency of 3 SC (Fig. 8C (3)). The positive jump is indicated by an arrow with an »X« in the touch point. The touch points of the auxiliary carrier for the television / .eil 1 are also marked by the "X" (Fig. 8C (I)). There are three task points in each period of the subcarrier. During a television line 2, ie during the next following line, the subcarrier according to FIG. 8C (2) and accordingly also the key clock signal with the frequency 3 SC opposite phase (FIG. 8C (4)) relative to the phase in line 1 (FIG. 8C (1), 8C (3)), see above that the sample values occur during television line 2 in points marked by X on the subcarrier (FIG. 8C (2)) in the case of positive jumps. The keys marked by X are shifted from line 1 to line 2 in relation to the subcarrier basic frequency by 60 °, which has a detrimental effect on the operation of the comb filter by the instantaneous amplitude of the analog signal according to the equations given above for correct extraction the chrominance information is exploited. It should therefore be noted that all sample values in odd lines and all sample values in even lines are vertically aligned with one another, but the sample values in even lines are shifted relative to the sample values in odd lines by 60 ° with respect to the base carrier frequency.

In order to avoid this by sampling with an odd multiple of the subcarrier frequency, ie with the frequency of 3 SC in the device, the vertical alignment of the sampling values in all lines is achieved by changing the phase of the sampling clock signal in every second line. In the examples shown in FIG. 8A, FIG. 8C (5) the key clock signal with the frequency 3 SC for the television line 2, whose phase compared to the key clock signal for the television line 2 according to FIG. 8C (4) is inverted. By touching for positive jumps in the touch points labeled "0", touch points "0" result on the auxiliary carrier for line 2 according to FIG. 8C (2). The touch points in the auxiliary carrier for television line 1 ("X") are thus aligned vertically to one another relative to the touch points ("0"). This results from the keying with a changed phase of the keying clock signal according to FIG. 8C (5) instead of keying with the Signa! according to FIG. SC (4). This technique is commonly referred to as phase alternate line (PAL) coding. This abbreviation or the term phase inversion or phase inversion is used below.

Comb filter technology with a sampling frequency of 3 SC or 10.7 MHz is used in the device, so that PAL sampling is required. However, the phase reversal is not applicable if a sampling frequency of 4 SC is used. Such a sampling frequency of 4 SC can be provided in the device according to the invention that the frequency characteristics of the recording media, ie the disk stack on the disk drive units, are sufficient for operation at a frequency of 4 SC or 143 MHz Standard disk drive units in data processing usually operate in the range of approximately 6V2 megabits and that the recording with a repetition frequency of 10.7 megabits ensures a sufficient increase in the packing density of the disk stacks themselves.

The use of a phase inversion according to FIG. 8C has another important consideration in the Operation of the device. By changing the phase of the key clock signal occurs in each subsequent line necessarily a phase discontinuity with respect to the subcarrier. However, it is during the channel coding of the signal for the subsequent recording, the digitally quantized sample values are more useful to encode with respect to a continuous phase clock, so that no phase discontinuities of line to line exist. For this reason, the PAL data at the output of the analog-digital converter 95 is clocked out of the channel encoder 96 with a clock that is continuous (i.e., from line to line). has no discontinuities) 3 SC phase. By clocking the encoder with a clock signal which is continuous in phase from line to line, the data but shifted in time by half a period of three times the subcarrier frequency in every second line, which disturbs the keying, which is time-aligned from line to line, due to the keying with a PAL clock. Since the Chroma processing circuit when reproducing d> e sample values of the data in a vertically aligned sequence needed from line to line (that's why a PAL key clock signal in the analog-to-digital converter is used), it is necessary to transfer the data from the continuous phase clock to the PAL clock clock back so that the duty cycle interference is eliminated and the chroma processing comb filter the data can handle without errors. The analog-to-digital converter 95 samples the analog signal using it of a PAL clock with phase discontinuities from line to line. The channel coder encodes the recording 96 the PAL data with a phase clock which is continuous from line to line, which occurs during playback and Post decoding, a back-clocking of the NRZ information into a PAL clock for use in the chroma processing circuit makes necessary. However, this down-cycle is not carried out in transfer mode, when the data stored on a disk memory is played back and ready for recording another disk storage is transferred. in these cases the line-to-line ratio remains continuous Phase clock of the reproduced video data received, with the data without disturbing the data clock be recorded again.

The above explanations are given below with reference to FIG. 8C illustrates where the PAL data for lines 1 and 2 in FIG. 8C (6) and 8C (7) are shown. Bits A 1 to E 1 are successive bit cells which represent the instantaneous sample values of the analog video signal, designated by X in line 1, according to FIG. 8C (1). Each bit cell lasts for a full clock cycle of the 3 SC clock according to FIG. 8C (3). Correspondingly, the bit cells A 2 to E 2 of the row 2 represent data which correspond to the sample values "0" in FIG. 8C (2) using the PAL clock signal that is used for television line 2 in FIG. 8C (5) is shown. For the clocking of the PAL data with a 3 SC phase clock continuous from line to line, the bit cells according to FIG. 8C (6) and 8C (7) the clock points of the phase clock continuous from line to line are represented by arrows, this clock the shifted bit cells according to the relation according to FIG. 8C (8) and 8C (9) are generated. The start of each bit cell is at the clock time, the level of the cell being im

BitzeUenintervall is continuous, so that £ the bit cells keep their identity during the clocking.

In order to clock the data from the phase clock, which is continuous from line to line, back into the PAL clocka so that the bit cells (sample values) are aligned vertically to one another in the intended sense (A 2 is aligned vertically to Ai , B 2 is aligned vertically to B 1, etc. ), the clocking back from the continuous phase clock to the PAL clock must be carried out correctly so that no misalignment of the bit cells occurs. must be clocked in the left part to ensure correct playback when clocking back from continuous phase to PAL. In the case of data clocked continuously in the phase from line to line according to FIG. 8C (9) therefore represent the solid arrows shown the correct complementary timing for the two television lines, the reverse timing of the data in the. PAL cycle with vertically aligned cells Ai and A 2 according to Fig. 8C (10V and Fig. 8C (11)) clocked bit cells, which are clocked back from PAL to continuous phase, are clocked in opposite directions, which can be seen from the consideration of the bit cells ( for example the bit cell Λ 1) with its associated clock arrows according to FIG. 8C (6> and 8C (8)) If the complementary clocking is not carried out, the bit cells are not correctly aligned with one another, as indicated by the dashed arrows according to FIG. 8C ( 8) and Fig. 8C (9) This creates the relationship shown in Figs. 8C (12) and 8C (13) The clocking back either from PAL to continuous phase or from continuous phase to PAL is activated carried out at various points in the system, which will be explained in more detail below.

It should be noted that the NTSC television signal has no special defined relationship between the horizontal sync pulse occurring in each line and the phase angle of the subcarrier signal. Only the phase of the subcarrier changes from line to line by 180 °. In other words, the phase angle of the subcarrier signal can be relative to change the horizontal sync signal from video source to video source so that the horizontal sync signal is not suitable for regulation in the device. In the device in question here, the subcarrier of the Input signal, as it is represented by the color sync signal component, as a basic timing reference used for the system, with a new signal related to the horizontal sync signal is defined, which is used in place of the horizontal sync signal for timing purposes. The new on the The horizontal sync pulse related signal is chosen so that it has a frequency equal to half the nominal horizontal line frequency because it has an integer number of periods of the subcarrier frequency, i.e. H. two represents complete horizontal lines of subcarrier frequency or 455 periods. In addition, owns the signal related to the horizontal sync pulse has a defined relationship to the subcarrier, d. H. it is synchronized with respect to the phase angle of the subcarrier. In the recording part of the signal system a sync word is inserted into the video signal at one point in every second television line of the video signal, which corresponds approximately to the location of the horizontal sync pulse, with a phase coherence in relation to a certain phase angle of the generated from the burst signal component of the video signal The new signal related to the horizontal sync pulse is applied Beginning of each picture and is maintained for the duration of the picture in order to respond to the horizontal sync pulse in the video signal related signal to ensure that exactly the phase of the subcarrier of the image video signal For the playback part of the

ίο signal system is a designated with H / 2 on the Horizontal sync-pulse-related signal is generated that is coherent with a specific phase angle of the Input reference support is where this phase angle! can be selected by the phase control in the playback system

The signal H / 2 related to the horizontal sync pulse serves as the basic reference timing signal for the system during playback operations.

By using the on the horizontal sync pulse related signal as reference horizontal synchronizing signal for the system it becomes signal processing for recording, playback and other operations of the system because there is a fixed time relationship between the subcarrier of the video signal and the signal related to the horizontal sync pulse is guaranteed

By using internal reference horizontal and auxiliary carrier signals that are variable in time relative to the reference synchronous signal of the television station, a timing control is also possible, on the basis of which the television signal can arrive at a distant point at the right time after the usual propagation delays .
According to the block diagrams according to FIGS. 8A and 8B, the analog video input signal is fed to the input of a video input circuit 93A, in which it is subjected to various processing operations before it is fed to the analog-to-digital converter 95. Specifically, in the video input circuit 93/4, the analog video signal is amplified, the DC voltage level is readjusted, the synchronous components contained in the video signal are separated to generate timing signals for the signal system, the peak value of the horizontal synchronizing pulse is determined and the horizontal synchronizing pulse is then limited. In addition, the horizontal sync pulse is separated by a precision sync stage to generate a regenerated sync pulse

so can. The circuit also generates a regenerated Hilo carrier signal. that from the burst signal in the input video signal or in the absence of the color sync signal from the H / 2 reference signal, the eus of the input horizontal sync pulse is generated, is derived.

Note that the video input circuit 93,4 and a reference signal input circuit 93ßim lower left part of the block diagram according to FIG. 8A perform similar functions with the video input circuit primarily for the signal recording part of the signal system and the reference signal input circuit is primarily intended for the playback part of the signaling system. For reasons of convenience, with identical circuits are therefore used for production and maintenance. However, the input circuits take only those input signals which are used to carry out the corresponding functions required are. Although both circuits are

Before generating signals, not all signals are used by every circuit.The reference input signal for the reference signal input circuit is formed by the station reference black signal, which contains all components of a color television signal with the exception of the active video part, which is at black level the reference signal input circuit 93B includes, as well as the input signal to the video input circuit 93A, the burst signal, the horizontal sync signal and corresponding signals. In addition, an H-phase position adjustment circuit is provided in the reference signal input circuit 935, which receives H-position control signals, for example from a dial or the phase control switch 81 to adjust the H-phase position of the regenerated Η synchronous signal for the playback part of the signal system

Some of the output signals of the input circuits 93A and 93ß are fed into reference logic circuits 125/4 and 125ß, which are assigned to the corresponding input circuit. The reference logic circuit 125/4 processes signals from the video input circuit 93/4, from the analog-to-digital converter 95 and from the computer control system 92 during the recording operation and generates a number of recording clock signals with frequencies of 6 SC, 3 SC and via precision circuits with a phase-locked loop 1/2 SC and a PAL error flag signal. A 3 SC-PAL key clock signal is generated from the PAL error identification signal and the 3 SC signal in the reference logic circuit 125/4, the phase of which is set for each line of the video signal by the PAL error identification signal, which has a frequency of H / 2 The PAL error flag signal changes value at this frequency. This change takes place asymmetrically, i. That is, the two values of the PAL fan identification signal have unequal time intervals. The asymmetry is chosen so that the tactile clock phase for the color sync signal part of the video signal is constant with the phase of the subcarrier and that only the part of the television line thereafter has a tactile phase which is changed in successive lines. This PAL clock signal is coupled to the analog-digital converter 95 and represents the key clock signal for generating the key values with a frequency of 3 SC or. Ϊ0.7 MHz.

The reference logic circuit 125b generates a clock reference signal having a frequency of the subcarrier (SC) and various other timing control signals from signals from the reference signal input circuit 935 and the computer control system 92. These signals are used in other operating modes of the device (non-recording of video input signals).

The reference logic circuits continue to generate servo sync signals during record and playback operations for the disk drive units to operate them in the correct phase.

In addition to recording video input signals, a reference clock generator 98 generates various clock signals and additional timing control signals during playback and in other modes, which are required for the various parts of the signal system in these modes. The reference clock generator generates clock signals with frequencies of 6 SC, 3 SC SC and 1/2 SC as well as various other timing control signals from input signals from the reference signal input circuit 93β from the reference logic circuit 125β (playback part of the signal system) and an operator-operated control switch. The reference logic circuits 125A and 1255 and the reference clock generator 98 together form the clock generator 94 according to FIG. 6, which provides the timing control signals for the system

The clamped analog video input signal from which the horizontal sync signal is also separated is fed from the output of the video input circuit to the analog-to-digital converter 95, which it in

ίο a binary coded signal with eight bits in PAL-NRZ format This coded signal is then fed into a coding switch 126. The analog-digital converter 95 is not described in detail as it is of a known type, for example circuit diagrams are contained in a device sold by the applicant with the type designation TBC-800 for the analog-to-digital converter 95, for example, a catalog no. 7896382-02 from October 1975 removable. Such an Anjfog digital converter is special for example the circuit diagram no. 1374256 on page 3-31 / 32 and the circuit diagram no. 1374259 on page 3—37 / 38 of the catalog.

The coding switch 126, which receives the output signal of the analog-digital converter, contains switching circuits, either the digitized eight-bit video data from the converter or from a data transfer circuit 129 record. The data transfer circuit 129 enables the video information to be transferred from one disk drive unit to another disk drive unit. The digitized Information read from the disk drive unit, decode in digital NRZ format, in the Corrected the time base and then on the coding switch?

given which are the sources for the digitized video information for the encoder% can select. Since the recorded on the disk drive units 73 encoded data are clocked with a clock of continuous phase are those of the data transfer circuit 129 recorded NRZ data is also clocked with respect to the clock of continuous phase. Usually the data transfer circuit 129 receives a PAL error flag signal, which is used to clock the digital NRZ data in relation to a PAL clock signal is used, so that the comb filter and chroma inverter switches JOl fed data in the correct PAL format are present. This reverse cycle is not required during transfer operation. The coding switch 126 contains a circuit for interrupting the coupling of the PAL faulty identifier signal to the Data transfer circuit 129, whereby the clocking back of the NRZ data with respect to the PAL clock during data transfer operation is prevented.

The encoder switch 126 is controlled by the computer control system 92 to clock the video data from either the video input or the data transfer path. It also switches between the video and reference timing signals of 6 SC and 1/2 SC since the reference timing signals are used during the data transfer operation and the video timing signals are used during the recording operation. The coding switch is also used to generate a signal that generates a flashing cross in the TV picture, which is a visual indication that the picture location or an address for a picture is free and therefore available for recording. In addition, the coding switch generates signals for performing examination functions. The coding switch 126 couples 8

Yl

Bit digital video data from analog-to-digital converter 95 and the data derived from the input video signal on encoder 96.

The eight bit data from the coding switch 126 are then fed into the encoder 96, which first generates a parity bit and encodes the PAL data in a square Miller channel code format, which is a self-clocking, DC-free NRZ code. If data are fed in, the output signal of the encoder is a 9-bit data sequence (with inserted parity bit) which has a phase continuity with respect to the frequency 3 SC. Continuously phase-clocked data are easier to process, which is particularly true for decoding processes. A DC-free code does not contain any DC voltage components which could occur over a period of time due to the dominance of a logic state, which could interfere with the data in the playback process.

In information channels of limited bandwidth, which do not transmit direct voltage, binary signals experience distortions in the zero crossing which cannot be eliminated by linear compensation networks. These distortions are commonly referred to as base line deviation and reduce the effective signal-to-noise ratio, modifying the zero crossings of the signals and thus adversely affecting the bit accuracy of the decoded signals. A common transmission format or channel data cude used in recording and playback systems ^; -t described in US Pat. No. 3,108,261. In the Miller code, logical ones are represented by signal jumps at a certain point, ie in the middle of the cell, and logical zeros by signal jumps at a certain earlier point, ie in the area of the leading edge of the bit cell. In the Miller code, jumps are represented at the beginning of an interval suppressed for a 1-bit following an interval containing a jump in its center. Asymmetries of the signal generated according to these rules can lead to a DC voltage component in the coded signal, the so-called "square Miller code", also called Miller ² code, which is used in the device according to the present invention effectively eliminates the DC voltage content of the original Miller code without either a large memory or a repetition frequency change in the coding and decoding are required.

The encoder% also generates a unique sync word in the form of a seven-digit binary number and inserts this sync word into every second line at a precise location, which is determined by the clock signals with a frequency of 6 SC and 1/2 SC . In the recording mode, the clock signals generated from the synchronous components of the video input signal by the reference logic circuit 125, 4 are fed through the coding switch 126 into the encoder 96, whereby the synchronous word is created which is inserted at a point which roughly corresponds to the point at which the horizontal The sync pulse of the video signal was present before. In other modes of operation, the 6 SC and 1/2 SC frequency clock signals are generated from the synchronous components of the station reference black video signal by the cooperation of the reference logic circuit 1255 and the reference clock generator 98. The encoder scans the sync word related to the horizontal sync pulse in every second television line into the data sequence at the correct point in time relative to the regenerated subcarrier phase.

Before the recording is also the on di ° data track of the disk drive units 73 encodes the data track information is provided by the computer control system 92.

According to FIG. 8B are the ten data sequences of the encoded digital data appearing at the output of the encoder 36 fed into an electronic data interface circuit 89 soft only a signal separation and represents a buffer circuit. This circuit couples the encoded data to the three disk drive units 73 for recording them on a stack of Dalen 75. Each disk drive unit contains one Data interface circuit 151 for this disk drive unit soft receives the data from the electronic data interface circuit 89 and transmits them a recording amplifier 153 and a head switch 97 for recording on an associated one Disk stack 75 conducts the interface circuit 15 ί continues to take reproduced data through the head switch 97 and a reproducing amplifier 155 and routes it to a data selection switch 128.

In addition, the data interface circuit 151 for the disk drive unit receives a multiplex servo reference signal from the electronic data interface circuit 89 and transmits it to a timing generator of the disk drive control circuit. This signal is taken from either reference logic circuit 125/4 or 125S by computer control system 92. In the timing generator, the multiplex servo reference signal is used for timing the disk drive unit such that recording and playback operations and the speed of the disk tape 75 in the disk drive unit 73 are synchronized with a suitable system timing reference signal. As explained above, standard computer disk drive units are used in the recording and reproducing device 70, but these are slightly modified to adapt them to the operating modes specifically required for the device.
The disk drive control circuit feeds prerecorded timing and data timing signals back to the electronic data interface circuit 89 via the disk drive unit interface circuit 151. In the special embodiment of the device according to the invention under discussion here, only two fields of the NTSC color television signal color code sequence are recorded with four fields, the two fields being recorded in separate revolutions of the disk stack 75. Immediately before the recording of the two fields of the video data, the prerecorded clock signal is generated and fed into the electronic data interface circuit 89. This interface circuit transmits the prerecorded timing signal to encoder 96 to produce an interval representing two field data equivalent to black, this interval being digitally defined by logic zeros. This data is fed back via the interface circuitry to be recorded on the disk stack in a track location which has been selected for the recording of video data and its data track information. The recording of the black data mentioned takes place during two revolutions of the disk sta-

pels 75 immediately before the two turns while which the two fields of the video data are recorded. This is the track position for the following Transfer of video data and data track information prepared Since the transfer from before recorded digital data with new digital data to obscure the previously recorded one Digital data can be performed with a recorded signal of sufficient quality for a Playback with an acceptable signal-to-noise ratio is guaranteed, the pre-recording cycle can be omitted. so that the recording of the two fields of video data and the associated data track information can take place in just two revolutions of the disk stack 75.

The data timing signal] is fed back to the electronic data interface circuit 89 to control the Generation and recording of the data track information in the second or last field of the two To clock fields of video data. The signal is a pulse, which after the vertical sync pulse of the Two fields of video data begins and ends at the end of the second field during this interval the data track information is recorded on the data track of the disk stack 75. The electronic Data interface circuit 89 couples the fed back data timing signal to the computer control system 92 to identify the system's data track recording interval. The computer control system 92 as a result, records the data track information ation-related functions, including it is the data track information of the recording of video data on a specific track of the selected data stack. The encoder 96 records the data track information and processes it in the sense described for transmission the Schcibcnantricbscinhcit 73 as well as for simultaneous recording with the last field of the video data.

The recording and reproducing amplifiers 153 and 155, the head switch 97 and the disk drive control circuit of the apparatus are assigned to one another so that the reproducing amplifier 155 and the head switch 97 are activated for reproducing data from the associated disk stack 75 at all times except when a recording operation is being carried out are. Except during recording reproduced data is always received by de ^r interface circuit 151 for the disk drive unit which the reproduced data in turn to the data selector 128 couples When recording is coupled a Aufzeichnungslbefehl from the disc drive control circuit to the recording and reproducing amplifiers 153 and 155 to to activate the recording amplifier 1153 and to disable the playback amplifier 155. The disk drive control circuit also provides a 30 Hz head switch signal during recording operations, causing the head switch 97 to couple the data sequences to one set of heads during the first field of the two consecutive field data to be recorded and to the second set of heads during the second field. This head switching signal at 30 Hz is continuously available and is used in playback operations to control the head switch 97 in order to switch the playback amplifier 155 between the two code sets for the reproduction of two fields of a desired video data signal.

In playback operations, the reference signal input circuit 93S and the reference logic circuit \ 25B as shown in FIG. 8A shows the regenerated frequency carrier frequency for feeding into the reference clock generator 98, its output signals at frequencies of 6 SC, 1/2 SC, H / 2 and other timing signals which form basic timing signals for playback operations. The clock and timing signals including the H / 2 reference signal are synchronized to the reference color subcarrier to facilitate processing of the reproduced video signals Reference black video signal defined The output signals of the reference clock generator are fed into the decoding and timing correction circuit 100, the data transfer circuit 129, the comb filter and chroma inverter circuit 101 and a blanking and bit blocking circuit 127 , which inserts the output signal, a selective bit blocking and delivers a selected image video signal as an output signal for the signaling systems when the heads, which are assigned to a disk drive unit coupled to the playback channel, are moved between the track positions. The digital information of eight bits is then in the digital to analog converter 102 and the processing amplifier 103 is fed which synchronizing signals and the color burst signal using the above-mentioned incorrect setting of the synchronous word is in the circuit 127 before the digital to analog converter 102 by the insertion of a corrective delay in the signal path corrected with alternating reproductions of the video signals with two fields. The reference clock generator 98 identifies which rendering of the two-field video signal sequence requires the delay by examining the image index signal, a color frame rate signal and the horizontal drive signal (all from reference logic circuit 125B) and the reference color subcarrier signal. The generator 98 generates an image delay switching signal which is coupled to the circuit 127 to control the insertion of the correction delay. During transfer and examination processes, the reference clock generator 98 supplies the basic timing signals for the encoder 96 via the coding switch 126.

During playback, the parallel data sequence with 10 bits, which is played back by a disk stack and which includes video data with 8 bits, the parity bit and data track information, is amplified, rectified and recorded and then fed via the interface circuit 151 for the disk drive unit into the data selection switch 128 , which the Can couple output signals of the three drive units to one or more of three channels. The data selection switch can thus switch the information from the disk drive unit No. 1 to channel A or to two channels, while at the same time a data sequence is switched from another disk drive unit to another channel. While information from two disk drive units cannot be switched simultaneously into a single channel, the reverse is possible. The data selection switch 128 would contain conventional switch circuitry which is not described in detail here.

The captured data sequences with 9 bits of video data and a parity data are then from the data selection switch 128 in nine individual data decoders and

Timebase correction stages fed into circuit 100 which decodes the data and then the nine Corrected data sequences independently of one another in relation to a common H / 2 reference signal in the time base, the latter signal being fixed with respect to the phase of the regenerated reference subcarrier is to eliminate timing errors in the nine data sequences. In this way, all synchronized words become one another aligned so that each parallel 9-bit byte contains the visible 9-bit data. The data track information is passed through the data selection switch only to the decoding part of the circuit 100, the decoded data track information is coupled to a CPU (not shown). The time base correction is performed using a continuous phase cycle. However, the data is processed by the DaicuiräiiSfci circuit 129 in uc <cug on a FAL clock clocked back, d. H. the phase of the signal is changed in each horizontal line by clocking back in such a way that that the data sequence coming from the data transfer circuit is a true PAL signal. The data transfer circuit 129 also performs a parity check on the data coming from the disk drive units by. This is done by covering up individually occurring byte errors by means of substitution by the most similar, previously occurring byte instead of the byte that was identified as an error. at the substituted byte is the third preceding byte, which is equal to the earliest sample value is which phase-related was gained on the subcarrier.

The output signal of the data transfer circuit is used for the case in the comb filter and chroma inverter circuit 101 is fed in when the video information is to be displayed visually. There is no recording to another disk drive unit (transfer). For a transfer, the data are used by dcf Data transfer circuit 129 coupled to coding switch 126. The comb filter and chroma inverter circuit 101 separates the chroma information from the luminance information using a comb filter technique and inverts the chroma information in every other image to form a composite NTSC signal with four fields, which is then fed to the reproduction output circuit 127. In this circuit becomes a reference black level during the blanking period and during the interval Granular level signals are inserted between the playback of successive images. If necessary, this leads Switching also through bit locks. This bit blocking means that all bits or certain bits of an 8 Bit television signal blocked by suppressing the data bit sequence, which in the resulting television signal special visual effects, such as enhanced color tones, ghost images and the like, can be achieved are. The output signal of the circuit 127 is then fed into the digital-to-analog converter 102. This digital-to-analog converter receives clock signals from circuit 127 and converts the data into their analog ones Form, whereby synchronous and color synchronous components of the signal are used at the same time generate a full composite analog television signal.

The video input circuit 93/4 and the reference signal input circuit 93B, shown in FIG. 8A in general are given, have the same structure, whereby they but record different input signals and not use all available output signals will. During recording operations, the composite video input signal to be recorded is converted to the video input circuit 93 / \ fed, which for generating a regenerated subcarrier signal as well as different ones based on the repetition frequency of the vertical and horizontal sync pulse c of related signals is used. These signals are carried out in the device exploited by recording operations. The video input circuit also provides an amplified and filtered video signal for feeding into the analog-digital converter 95. During playback operations, a reference black video signal is fed to the reference signal input circuit 93b, which are similar Supplies signals for the performance of playback operations.

According to the block diagram for the video input circuit according to FIG. 9, the video signal is fed on a line 200 into a video amplifier 201, which amplifies the signal and regenerates the equal voltage component via a clamping stage 202. The clamping stage 202 samples the output signal of the amplifier on a line 203 and generates a DC voltage component on a line 204, which is fed back to the amplifier 201. The clamped video signal on line 203 is then passed through a low-pass filter 205, the output signal of which is fed on line 206 into a video control amplifier 207. This amplifier 207 is coupled to a further video amplifier 208, a second clamping stage 209 ensuring that the blanking level of the signal has reference potential (ground level). This is done by feeding a DC voltage control signal into the video amplifier 208 via a line 210. The output signal from the video amplifier 208 is fed into the key input of the clamping stage 209 via a line 211 and a line 218. The line 21J also leads to a keyed sync signal limiter stage 212 and to a precision sync signal separator stage 213 to regulate from another place. The output signal of a synchronous peak detector 214, which may still contain a ripple, is fed into an input of the precision synchronous signal separating stage 213, the other input of which is coupled via the line 218 to the output of the video amplifier 208. The two input signal? the precision * sync signal separator 213 can also have a VsINg ^- speed, the feed being carried out in such a way that the separator generates a ripple-free synchronous signal on a line 220 which is fed to various synchronous stages 221 and an input of a horizontal synchronous phase detector 222. The line 218 is also carried from the output of the video amplifier 208 to a less precise synchronizing signal separating stage 219, which supplies a less precise synchronizing signal. This signal is fed into a pulse generator 223, the output of which is coupled via a line 224 to both the clamping stages 202 and 209 and the synchronous peak detector 214. If a horizontal synchronous signal is detected and cut off, then the key pulse generator 223 delivers a key signal which closes the Kiemmsiufen and the synchronous mushroom detector at the correct time during the horizontal blanking interval.

The clamping step 209 is during the color syn-

Chronsignal-Zeit not in an arbitrary period, but closed for an integer number of periods, so that the blanking level of the video signal can be obtained precisely by an integral ion technique. This function is described in more detail below. The color synchronizing signal occurs on a line 225 which is carried to a color synchronizing signal limiter stage 226. This stage 226 is in turn coupled · χ \ {to an amplifier 227 which delivers komplemencäre output signals from the limited input color burst signal. The output of the limiter stage 226 is coupled to a color sync signal detector 228, one output of which is coupled via a line 229 to a precision key generator 230 and another output is coupled via a line 260 to a phase detector 231. If the presence of a color sync signal is detected, the precision key generator 230 supplies a precision color sync key signal which effectively switches the amplifier 227. whereby the middle three periods of the burst signal are coupled to the phase detector 231 . The phase detector 231 consequently supplies an error signal for a voltage-controlled oscillator 232, which is a measure of the phase difference between the output signal of this oscillator and the phase of the color sync signal periods supplied by the amplifier 227. The phase detector thus controls the oscillator 232 in order to correct long-lasting changes in the phase of the three periods of the color sync signal, which are used in each line as a subcarrier reference. The output signal of the oscillator 232 is coupled to a line 233 via a buffer 234. The output signal of the oscillator is a continuously regenerated subcarrier signal of frequency SC (3.58 MHz), the phase of which is related to the existing color subcarrier signal. However, if the color sync signal detector 228 does not detect a color sync signal, the phase detector 231 compares the phase of an H / 2 signal with the regenerated subcarrier output signal of the oscillator 232, the H / 2 signal being generated by a synchronous generator 235 by an oscillator 236 which is driven by the horizontal synchronous phase detector 222.

A horizontal phase position control, generally designated 237, is provided in the reference signal input circuit 93B, which is used to adjust the horizontal position of the regenerated synchronous signal. For example, an 8-bit binary number is loaded into holding stages 238 via a dial assigned to the reference clock generator 98 and operated by an operator in order to preset a counter 239 which is clocked at 400 Hz by a clock signal coming from the oscillator 236. When the counter reaches its end value, it triggers a sawtooth generator 240 with an output 241, which is fed to a second input of the horizontal synchronous phase detector 222. By adjusting the hold levels, up to plus or minus 20 microseconds can be set in the feedback loop on line 241 , and the phase of the regenerated sync signal can be adjusted for horizontal adjustment of the image during playback. Since a delay in the feedback loop means that the regenerated sync signal is advanced, the horizontal position control can advance the image accordingly to compensate for transmission delays of a signal over cables in a television station. This horizontal phase position control works together with a subcarrier phase control, whereby the delay can be controlled in small increments. In the case of the embodiment of the device according to the invention in question, values of approximately ± 0.8 nanoseconds are involved. The output signal of the oscillator 236 controls the synchronous generator 235, which is conventionally designed for television signal processing, in the sense of generating various signals related to the vertical and the horizontal synchronous signal repetition frequency according to FIG. 9. These signals, which are related to the synchronizing signal repetition frequency, are generated by the phase detector 222 with respect to the phase of the precisely regenerated horizontal synchronizing signal, so that they are always related to the phase of the input signal.

An important aspect of the circuit of FIG. 9 is that the horizontal sync signal of the video signal is limited to exactly half its value and the value of the blanking signal is clamped precisely to the reference potential (ground). The regenerated subcarrier is related to the phase of the color sync signal, a precision horizontal sync signal being obtained by the precision sync signal separator. This signal is used in the synchronous generator 235 to generate a reset pulse (picture index pulse at 30 Hz) to reset a line identification or synchronous word insertion circuit. Since the clamping stage 209 determines a mean zero level of the video signal during the color sync signal time using a clamping pulse which lasts exactly for an integer number of periods of the color sync signal, no low-pass filtering of the video signal and switching off of the color sync signal is necessary before the clamping process. This arises from the fact that the resulting integration of the burst signal is zero and that no H / 2 ripple is generated by the integration of a signal which does not contain complete periods of the burst signal.

The block diagram according to FIG. 9 describes the functional mode of operation of the input circuits. Specific Circuits for performing these functions are shown in FIGS. 1IA to 11D shown, which total present a complete schematic of the video input circuits.

With regard to the mode of operation of the clamping stage 209 (see FIG. 11 C), the voltage at the output of the amplifier 208 is on the lines 211 and 218, the latter of which is led to the base of an emitter follower transistor 244 , at which a voltage drops. Under equilibrium conditions, the blanking level of the video signal on line 218 is at reference potential (ground). This signal is shifted negative by 0.7 volts due to the voltage drop at the emitter follower 244. A matching emitter-follower transistor 245, the emitter of which is coupled to the inverting input of a differential amplifier 246 via a line 247 , shifts the comparison level (ground) into the negative, as does the transistor 244. The emitter of transistor 244 is coupled to the non-inverting input of differential amplifier 246 when a transmission gate or Schaher 248 is closed during an integer number of periods of the burst signal by a signal on line 224 represented by the signal shown in FIG . Key pulse generator 223 shown in FIG. 11D is generated. During the color sync signal time, switch 248 is closed.

sen, whereby a capacitor 249 is charged to the mean value of the burst signal. The desk is closed for an integer number of periods of the subcarrier. This eliminates the need for a Low-pass filtering of the video signal in order to turn off the burst signal before the clamping process, what in a known manner to eliminate the H / 2 modulation the Klemro level takes place. The charging of the capacitor 249 reproduces exactly the mean value of the burst signal, whereby the output signal of the differential amplifier 246 represents an error signal which is transmitted via a line 251, a transistor 252 and the Line 210, which is coupled to the emitter of transistor 252, is coupled to video amplifier 208 will. The blanking level of the signal on line 211 is therefore held approximately at reference potential (ground) due to the high DC voltage gain of the differential amplifier 246. How the in Kiemmstufe 202 shown in Figs. IiA and ÜB corresponds to the mode of operation of clamping step 209.

According to FIG. HC, when the switch 248 is closed, the color sync signal is sampled into the capacitor 249 and fed into the line 225, which leads from the left part of the circuit according to FIG. 1 IC to the circuit according to FIG is coupled so that the color sync signal is fed from its collector via a line 255 to the color sync signal limiter 226. If the color sync signal is present, the precision key generator 230 supplies a limited color sync signal on the line 229, which clocks the precision key generator 230. This key generator is designed as a counter which counts periods of the limited color sync signal and generates a precision color sync signal key signal during the middle three periods of 9 to 11 periods of the color sync signal interval, which is coupled to the amplifier 227 via a line 256 to this to switch effectively. Apart from the three middle periods of the color burst signal, the amplifier 227 is blocked by the output signal of the color burst signal detector 228. If the color sync signal is present, a diode detector 257 and a subsequent hold circuit 258 of the detector 228 deliver a more negative value on a line 260 which leads to a switching transistor 259 (FIG. HB) of the phase detector 231. When the color sync signal is present, the switching transistor 259 is blocked and a further switching transistor 261 of the detector 23i is switched through. When the transistor 261 is switched through, the three periods of the color sync signal from the amplifier 227 are coupled via a driver stage 277 to a transformer 262 of the detector 231.The driver stage is coupled to a phase comparison stage 231a to match the phase of the color sync signal with the phase of the output signal of the oscillator 232 of 3.58 MHz (SC) , the latter signal being on the line 233. If the detector 228 does not detect a color sync signal, the transistor 259 is switched through, whereby the H / 2 signal is coupled to the other input of the driver stage 277 which is also connected to the transformer 262, in which case the phase of the oscillator output signal on line 233 is compared with the phase of the H / 2 signal.

The Schaitungsleii for the separation of the horizontal sync signal HC includes the decrease of the sync signal from amplifier 208 on the line 218 through a low-pass filter 264, the output signal of which is coupled to the base of a transistor 265. The emitter of this transistor 265 is coupled to a transmission gate or switch 266, the is closed via the control line 224 while the synchronization signal is present. The value of the Synchronization signal is determined by the charging of a capacitor 267 (Fig. 11 D), which on a Amplifier 26 ″ is coupled to gain 1, with half the DC voltage level of the peak of the

ίο sync signal together with the full value of the im Signal existing ripple coupled via the line 215 to an input of the synchronous separation stage 213 whose other input is fed via a line 269 coming from the emitter follower transistor 265.

The output signal on line 220 is therefore a separated synchronous signal, the timing of which is determined by dir Ripple on the video signal is not influenced, since this ripple at both inputs of the comparison stage 213 auiiriü and because of the Gicichiäkibeträebs am Exit no longer appears. The sync signal generated on line 220 is a precision sync signal represents that in other parts of the signal system for generating horizontal lines Serves synchronizing signals, which are fixed with respect to a specific phase of the subcarrier signal. These signals serve as timing reference signals in the signal system for processing the video signals. That in the system The synchronous signal used related to the horizontal lines has a repetition frequency of 1/2 H, as for two horizontal lines (227.5 χ 2 = 455) an integer number of subcarrier periods is available.

A less accurate split sync signal is also generated by the sync signal from the low-pass filter 264 via a line 270 to the less precise synchronizing signal separating stage 219 is, whose output signal is fed via a line 271 to the Tastirnpulsgerierator 223, which a contains as a synchronous detector 276 acting monostable multivibrator. A generally designated 272 The upper part of the circuit generates a key signal for the switch 266 to switch it off while it is present of the sync signal while a circle 273 generates a porch button signal and a Circle 274 redefined a color sync key signal with respect to the SC phase. Regarding the detector 223 it should be noted that the synchronous detector 276 in the absence of a synchronous signal, that then also does not that occurs from the less accurate synchronizing signal detector 21S line 271, both the Switch 248 in the clamping stage 209 via the circuit 274 as well as a corresponding switch 275 in the Clamp stage 202 closes so that all clamp stages are on a DC voltage feedback loop and not work on an open loop. If the synchronous signal is not present, the level is on line 224 high until the sync reoccurs and is detected. In the event that the precision probe generator 230 does not receive the necessary number of burst signal periods to activate it after its counting cycle has been triggered to touch its final value is provided as a safety measure that the detector 276 over the Circuit 274 is switched through in order to couple the color synchronous key signal to the precision key generator 230, whereby the counting cycle is ended and the precision color synchronous tactile saw! is delivered. This ensures that the precision key generator 230 always responds correctly to every input color sync signal appeals to

Uiv: to ensure a picture index signal in the coding switch 126, which is precisely related in phase to the vertical sync signal of the input video signal, become the output of the precision sync separator 213 and an output of a vertical sync detector 278 (Fig. HB) coupled to a NOR gate 279 (Fig. 11D) which is the desired Image index signal supplies.

The reference logic circuits 125/4 and 125ß according to the block diagram of FIG. 8A receive various Signals from the input circuits 93Λ or 93S, which respond to the horizontal and Ventikal synchronous signals, the regenerated subcarrier and other corresponding signals are related, and generate a Number of clock and timing control signals for the device according to the invention. Furthermore, the computer re ^ els ^ tem 92 Re ^ elsi ^ nale both for the lo ^ ic circuit 125/4 as well as for the logic circuit 1255, which are used to generate servo sync signals. These signals regulate the functional phases of the disc drive units in the various operating modes, for example during recording, playback, transfer and others carried out by the device Operations. The reference logic circuits are duplicated, so that such a circuit for the Video input circuit 93/4 and another for the reference signal input circuit 93ß, the function of the reference logic circuits during said various operations of the device works a little differently. Since the logic circuits 125/4 and 125β have different functions execute, they receive different input signals, whereby all available output signals are not used will.

The mode of operation of the reference logic circuits is illustrated below with the aid of a block diagram Fig. 10A explained in more detail. A dashed line running horizontally approximately through the middle of this block diagram Line separates different functions. The upper part of the circuit is only used when recording exploited while the lower part of the circuit in recording, playback and other operations of the signaling system is used. The upper part of the circuit is used to generate various phase-locked devices Clock signals for recording processes using the regenerated subcarrier, which is in the the sense described above is generated by the video input circuit 93/4 from the burst signal. the Circuitry also produces an unbalanced PAL mis-tag signal with a frequency of H / 2, which for the reasons mentioned above for the phase reversal of the duty cycle signal in the analog-digital converter in successive Horizontal lines is used. This PAL error!: Identification signal is also available as Output signal of the reference logic circuit 125β available to be used in other parts of the signal system, primarily to be used in the parts used for processing the playback signals. The circuit also generates a driver synchronization signal to control the servo control of the disk drive motors, which is a set of three pulses with a repetition rate of 15 Hz that together is used several times with the horizontal synchronous signal to control the servo control. Further timing control signals are generated by the reference logic circuit in a manner to be described in greater detail below 125ß generated

In the upper part of the circuit according to FIG. 10A, the phase-controlled precision clock pulse generator cas Subcarrier signal (SQ either from the video input circuit 93> 4 for the reference logic circuit 125/4 or from the reference signal input circuit 93ß for the reference logic circuit 125β, which is fed on a line 300 and to a phase comparison stage 302 is performed, the output signal of which is fed on a line 303 into a summation node 304 whose second input signal is via a line

ίο 305 is supplied by an integrator 306. A digital precision color synchronous phase decoder 307 receives the digitized video data from the output of the analog-digital converter 95 via a line 308 and determines whether the sample values are obtained with the correct phase of the color synchronous signal. This decoder generates a plus or minus error signal for the integrator 306 on a line 309, whereby the phase of the key clock signal is adjusted so that the video signal is always keyed correctly. The output signal of the summation node 304 is fed via a line 3ii to a loop amplifier and filter stage 311, which is coupled to a voltage-controlled oscillator 312 via a line 313. The line 313 is also carried to one of two driver stages 314 for fault indicator lamps. The output of oscillator 312 occurs on line 315 at a frequency of 6 SC and is fed to a divide-by-6 counter 316 and a divide-by-2 counter 317, a PAL clock output signal being generated on line 318 at a frequency of 3 SC will. The counter dividing by 6 yeasts on a line 319 an output signal with a frequency SC, which is fed into a counter 320 dividing by 2 and into the other input of the phase comparison stage 302.

The output of the divide by 2 counter 320 is a signal having the frequency 1/2 SC on a line 321 which is carried to a pulse shaper 322 to set and reset the divide by 2 counter 317 in every other line. Control takes place via a line 323 with a frequency of H / 2, this signal being supplied by a PAL error code generator 324, which will be explained in more detail below.

The operation of the upper part of the attitude serves to generate a signal with the frequency 6 SC at the output of the voltage-controlled oscillator 312, which is so precisely regulated that the keying carried out in the analog-digital converter 95 at all times with exactly the same phase of the color sync signal takes place. This is important considering the fact that the phase of the sampled video signal ultimately determines the color produced by the device. The phase comparator 312, one input of which is supplied with the divided output signal of the voltage-controlled oscillator 312 via the line 319, forms a phase-locked loop which sets the phase of the output signal relatively precisely to the phase of the video or reference synchronous signal on the line 300 , which is fed into the other input of the phase comparison stage 302. The divided output signal of the voltage-controlled oscillator 312 generates a signal with the frequency SC via the phase-locked loop, which is generally within about 10 °. The digitized video output signal from the analog / digital converter 95 is, however, also fed via the line 308 into the digital precision color synchronous phase detector 307, which is triggered by the precision color synchronous key signal on a line 307

is activated to generate an error signal which arises during the color sync interval of the video signal. This error signal is integrated by the integrator 306 in order to generate a mean value to be fed into the summation node 304. The voltage value at the output of the loop amplifier and filter stage 311, which controls the voltage-controlled oscillator 312, is adjusted so that changes in the sampling times of the video signal, which are represented by the color synchronous sampling values supplied by the decoder 307, are corrected. The color synchronous sampling values represent the same values for all lines if there is no change in the sampling times. By monitoring the sampled data occurring at the output of the analog-digital converter 95, it can be determined precisely whether the sampling values have been obtained in the correct phase. In this way the Alisgangssigna! of the voltage controlled oscillator on line 315, which is fed into the divide by 2 counter 317, a PAL clock signal! of frequency 3 SC on line 318 which controls analog-to-digital converter 95 to keep the keying in phase. The digital precision color synchronous phase decoder 307 corrects errors which arise due to a temperature drift and the like and are of the order of magnitude of 5 ° to 10 °. In this regard, the phase of the video (or reference) subcarrier sync signal on line 300 is the basic setting for voltage controlled oscillator 312, with the precision correction on line 305 in reference logic circuit 125S increasing the phase by a few degrees “Changes up to about 20 °

In the lower part of the block diagram according to FIG. 10A, the PAL error code generator 324 generates a PAL error code signal! with the frequency H / 2 for switching a switch 325, which feeds pulses with the frequency 1/2 SC into the set or reset input of the counter 317 dividing by 2, which supplies the PAL T ^ ktsignal on de · - line 318 The PAL -Error flag signal changes its state in each line, as will be explained below with reference to FIG. 10B. The PAL error flag signal is unbalanced so that the phase of the PAL clock signal of frequency 3 SC is never reversed during the sync interval of the video signal, while it is reversed every other line during the active video signal phase. In essence,! it results from the fact that only the part of the line after the color sync signal is scanned with a clock signal, the phase of which is reversed in every second line, ie it is an asymmetrical signal. As shown in Fig. 10A, the PAL error flag generator 324 receives input signals from the video input circuit 93A or the reference signal input circuit 93S, which are an H drive signal on line 326, a picture index pulse on line 327 and a color sync error flag signal a line 328 acts. The synchro-error flag signal prevents the PAL error flag generator from generating a PAL error flag signal on line 323 until the color sync signal has occurred, since the key phase of the color sync signal for the function of the color sync phase detector 307 in the upper part of FIG. 1OA does not need to be changed. The PAL error flag generator also generates a transfer reset pulse on line 324a at the frequency H / 1/2 for the coding switch 126, which at Datentransferope rations is used to generate a signal that is in Encoder 96 is used to reset the sync word-A set circuit

The H drive signal and the picture index signal become is fed into a driver servo synchronous generator 330 whose output via a line 332 to eini Driver synchronous switch 331 is coupled. This driver synchronous switch 331 provides the basic information Driver sync signals on line 334 for di (disk drive units 73, whereby it is via a control derivation 333 is controlled by the computer control system 92.

The sync signals are necessary for all operations

agile, in which the information is transferred between a disk stack 75 and the signal system The computer control system 92 determines whether a record or playback operation is desired The synchronized information is applied to the de »See:

benantriebsemheiten leading lines 334 in Forn 6Ui £ 5 nrtältipicX-SynCiirGnSigiiaiS VGf, Gä5 ciilcil SätZ VOi three consecutive wide pulses with a rate of 15 Hz to index the first recorded or reproduced field so like horizontal sync pulses (with H-repetition fre quenz) and is used to regulate the spindle servomotor. To regulate the servo drive and to Generation of control signals during playback operations by the reference clock generator are continued Color image-related synchronous signals generated These signals are generated by a color image generator 301! which picks up the image index pulse with a frequency of 30 H: via a line 327 and uses it to generate divides by 2 of a color image signal at 15 Hz. These Color signal via a line 329 to the Schei ^ cnsntnebseinheiten 73 and Zürn Referenztsict ^<r ene ator 98 sent

A special circuit for performing the ope rations of the block diagram according to FIG. 1OA is in dei 12A through 12D which together show a schematic of the reference logic circuits. Since dii Mode of operation of the circuit shown in these figures generally runs in the manner as it was in the foregoing standing was explained with reference to Fig. 12A, win this circuit is not described in detail. With regard to the shown in the upper part of Fig. I2A) digital precision color synchronous phase detector 30; it should be noted, however, that the digitized auxiliary line ger or color sync signal in the form of 8 bits of Output of the analog-digital converter 95 via line gen 308 is entered, which are coupled to arithmetic logic stages 335, which in turn with Schie register 336 are coupled. These shift registers 336 are designated generally by 337 Logic clocked, which by the precision color system chron button signal on line 307/4 are activated and together with the arithmetic logic stages 33i that determine the sign of the phase of the digi talized color sync signal on line 309 not perform agile arithmetic steps. De Errors in sample values are detected by examining the quadrature component of the sample values which is equal to zero if the sample values are in the correct phase of the subcarrier color sync signal:

were won. Specifically, the quadrature component is proportional to the function X 1 - 1/2 (X 2 + X 3} in which sample values Xi, X 2 and X 3 are 120 ° apart. The logic 337 executes the sequence which wel

31

before the arithmetic stages 335 and shift registers are effective for performing the arithmetic calculation switch, which generates either a plus or a minus signal on line 309, causing an error in the phase of the actual sampling values is displayed.

The circuit of Figure 12A also includes one Circuit 324 for generating the PAL error flag signal on line 323, the H driver signal inverted by an inverter 342 and fed into the clock input of a flip-flop 339 via a line 338 which generates a signal divided by 2 on an output line 340. This signal is in the Input of a second flip-flop 341 fed by the color sync error flag signal the line 328 is clocked. The line 340 as well the output line 344 of the flip-flop 341 lead to a NAND gate 343. The operation of the PAL error code generator 324 is explained below with reference to the signal diagrams according to FIG. 10B FIG. 10B (1) shows the H driver signal (line 326), FIG. 10B (2) shows the signal on line 340, F i g. 1 OB (3) the signal on line 344. F i g. 10B (4) the color sync error flag signal on the line 328 and 10B (5) show the output of the NAND gate on line 345. The PAL error flag signal on line 323, due to the action of inverter 346, the inverted signal is on Line 345. The PAL error flag signal occurs at a frequency of H / 2, FIG. 10B (5) showing that this is an unbalanced signal, because the output signal des appearing on line 344 and fed into NAND gate 343 Flip-flop 341 is delayed with respect to the signal of the first flip-flop 339. This is because the flip-flop 341 is not clocked by the H driver signal but by the color sync error flag signal will.

The reference clock generator 98 generates the basic Timing signals for the device during playback, data transfer, examination and other operations. during which video input signals are not recorded and used as an input time reference the regenerated SC signal (338 MHz) generated by the Input circuit 935 generated and by the reference logic circuit 125S is sent. A phase shift option is provided in the reference clock generator, to shift the phase of the entire system, being a phase-locked loop as well as associated Counters and logic circuits are provided to track the timing signals with the desired system phase. It also generates control signals for the decoder and time base correction circuit 100 as well as the »

Comb filter and chroma inverter circuit 101. Next- "'

the reference clock generator 98 identifies alternate renditions of the recorded image two fields and provides a frame delay switching signal for circuit 127 to avoid one Citicrns of the displayed output video signal, which is otherwise due to the use of a subcarrier signal with the reference color synchronized timing signal related to the horizontal sync signal Control of the processing of the reproduced video information would occur.

In addition 17 sheets of drawings

Claims (4)

Patent claims: 1. Arrangement for digitizing an analog, Information signal in a predetermined phase relationship to a reference signal, in particular a color television signal as a function of its color sync signal, with a sampling circuit (95) delivering digital samples of the information signal in time with a clock signal and a clock signal generator (312, 316, 317, 325) that generates the clock signal, thereby in that the clock signal phase of the clock signal generator (312, 316, 317, 325) dependent on two error signals is controlled such that a first error signal-generating, the phases of the clock signal and the reference signal comparative phase-locked loop (302, 311.319), the clock signal phase in a substantially phase-locked relationship to the reference signal, and that a phase adjustment circuit (305, 307), which generates the second Fch'.crsignal depending on the deviation of the phase positions of the sample values supplied by the sampling circuit (95) from predetermined target phase positions of the reference signal, generates the clock signal phase changes so that the second error signal is approximately zero and the samples are obtained in the predetermined target phase positions. 2. Arrangement according to claim 1, characterized in that a summing circuit (304) sums the first and the 'wide error signal and outputs a voltage corresponding to the sum to an oscillator (312) of the clock signal generator (312, 316, 317, 325) whose Frequency can be controlled depending on the voltage. 3. Arrangement according to claim 1 or Z _1, characterized in that the phase adjustment circuit (306, 307) generating the second error signal has a phase decoder (307) which, depending on whether the phase positions of the samples lead or lag the predetermined target phase positions, is positive or a negative error sign signal is generated and that the phase decoder (307) is followed by an integration circuit (306) which integrates the error sign signal over time and which supplies the second error signal. 4. Arrangement according to claim 3, characterized in that that the phase decoder (307) detects the quadrature component of the sampled values and if present Quadrature component generates the error sign signal or in the absence of a quadrature component no error sign signal generated.