DE2613873A1 - Programme store in telephone exchange - has N:conductive channel FET with thin insulator between flange and part of drain - Google Patents

Abstract

A first part of the channel of the FET is fully or nearly separated, it is connected by only a narrow section of the remaining channel part, to the drain (D). An insulator (Is2) is inserted between a lobe (L) and the part of drain (D1) which is covered by the lobe on the other side of the channel. It is thinner than the insulator between the storage gate (G1) and the drain end of the first part of the channel.

Description

n-channel memory FET

The invention relates to a further development of the present claim 6 of the main application P 25 13 207.4-33 (VPA 75 P 6039 BRD) specified n-channel memory FET and the developments of the specified in this claim 6 of the main application n-channel memory FET. The main registration is an addition to the registration P 24 45 137.4-33. Both the essential content but the main application is already in the Luxembourg patent 72,605 corresponding to both applications.

*) of the last-mentioned application as well as the invention goes so from claim 6 of the main application, so from a channel memory FET with at least one gate, namely with one surrounded on all sides by an insulator, floating memory gate, in which the electron injecting device is used to recharge the memory gate Channel injection - that means reloading through strongly accelerated in your own conductive channel and thereby heated electrons, which because of their heating by acting effective effective electric field the energy threshold to the conductivity band of the isolator and thereby get to the storage gate - is exploited, whereby the channel injection is used for programming, i.e. charging the memory gate so that the memory gate after this charging by means of its negative charge By influencing the source-drain current, the source-drain path is inhibited acts, with an additional, a connection having controllable control gate is provided, which acts capacitively on the memory gate, wherein the memory gate with regard to the channel length only one extending over the entire width of the channel covers the first part of the channel which contains the channel point from which by means of channel injection during programming the heated electrons to the memory gate get, or which one at least adjoins this Eanalstelle, the control gate, but not the memory gate, the rest being electrical covered part of the channel lying in series and with its memory gate laterally a conductive connection from the channel, isolated from the substrate by a thick oxide layer having a conductive tab attached outside the channel, which has a Part of the source or drain covered by a thin oxide layer.

In the invention, the erasure takes place towards the drain. The rag L serves, as described in the main application, in particular for deletion, thus for discharging the memory gate G1. The rag L, which is covered by a thick oxide layer from the substrate isolated connection is connected to the memory gate, allowed namely the programmed memory gate that is negatively charged by means of channel injection to extinguish, i.e. to discharge, e.g. by at the pn-junction under the tab, i.e. on the pn junction between drain and substrate, an avalanche breakdown is generated, whereby There holes heated by the avalanche effect through the insulator to the rag and thereby discharge the storage gate. These and other deletion methods is already indicated in the main application, page 15, line 22 to page 16, line 37.

In the main application it is also described that the remaining part of the canal can be divided into two sections, between which the first part of the Canal lies.

This particular n-channel memory? ET has the advantage of having low To be able to program operating voltages, and beyond can even be excessively erased using the cloth, since the memory gate is charged positively is harmless to the operation of this FET. This is already in the main application described. This memory FET is therefore particularly reliable and also with programmable for low operating voltages.

By Japan J.Appl.Phys.13 (1974) No. 2, 367/368 are experimental tested formulas, with regard to an ordinary MOS-PET, for the dependence of the Avalanche breakdown voltage at a source-substrate-pn junction of the insulator thickness known. After that, the avalanche breakdown voltage decreases the thinner the insulator between the gate and the pn junction.

Through a lecture manuscript by Kikuchi, Ohya, Kamaya, Koike and Yamamoto on the occasion of the First European Solid State Circuits Conference, September 2-5, 1975, Canterbury, England, particularly Figures 1 and 2, is an erased conductive n-channel SAMOS memory FET with then positively charged memory gate known, its Discharge memory gate when programming with heated electrons and when "erasing" is positively charged with heated holes. The heating is in each case by means of of the avalanche effect, namely when programming ", namely discharging, between Drain and substrate and when "erasing", namely charging, between source and substrate, see also the initial state according to FIG. 9 there, to improve the efficiency when "programming" with heated electrons, the insulator thickness is in the channel area, namely at the pn junction drain / substrate in at least part of the channel width comprehensive section of this transition, between memory gate and Drain, smaller than in the other places of the memory gate, namely especially between Memory gate and substrate. - However, the invention is not based on an n-channel SAMOS Spelcher-? ET, but from a programmable, i.e. rechargeable, n-channel memory PET by means of channel injection the end. In the case of the invention, the memory gate is not positive with holes, but negatively charged with electrons. In addition, the invention takes place Deletion not in the canal area, but over the flap. The deletion takes place as well as the programming in the invention different than in this known one n-channel SAM0S memory FET. The latter also has a different structure than that Invention, e.g. because it does not have a flap on the side of the canal.

In the main application it is explained on the basis of line F3 in FIG. 2 there, that the insulator, e.g. SiO2, has a minimum thickness between the memory gate O1 and the channel, e.g. 450 A, so that when programming the n-channel memory FET no unwanted partial deletions ("neighboring word disturbances") in neighboring, namely already programmed further such n-channel memory PETs connected at their drains appear.

The invention solves the problem of being as reliable as possible and to provide low voltage operable n-channel memory FET, namely one by means of duct injection with operating voltages that are as constant as possible, which therefore remain largely the same from charge to charge, programmable and then an n-channel memory FET having a negatively charged floating memory gate, reliably over the flap on the side of the actual canal, e.g. by means of the avalanche effect or especially by means of the Fowler-Nordheim tunnel effect according to the main application, is completely or even excessively erasable.

The programming and the deletion should be accordingly in each case take place via different, specific places in the isolator, namely the programming in the canal area and the deletion always via the flap located away from the canal, whereby the rapid poisoning of the isolator is avoided and to avoid it the avalanche breakdown voltage in the area of the drain does not affect neighboring word interference should be humiliated.

The invention is also intended to have a lower avalanche breakdown voltage in the area of the flap ensure that the deletion lasts for as many as possible Reloading cycles to avoid poisoning reliably over instead ofÄ {m # 5ibi; # lC # d ## alancheeffekt ' the lobes take place, especially with the avalanche effect, at the drain-substrate transition takes place in the canal area.

The definition of drain and source corresponds to the channel electron current direction while programming.

As already indicated above, the invention is based on the above-cited, in claim 6 of the main application specified n-channel memory FET. The memory FET is characterized by the fact that the first part of the canal is completely - or almost i.e. only through a narrow section of the remaining part of Channel separated - adjacent to the drain and that the insulator between lobes on the one hand and, on the other hand, the part of the drain which is covered by the flap and which is remote from the canal is thinner than the insulator between the memory gate and the drain-side end of the first part of the canal.

The first part of the channel should be completely - or almost, i.e.

only through a particularly narrow section of the remaining part of the channel separated - adjoin the drain, because then when the channel electrons are heated particularly low programming operating voltages can be achieved in the vicinity of the drain especially if there is a channel inhomogeneity as an acceleration path as close as possible to the drain, E.g. a channel constriction to heat the anal electrons.

The compared to the drain-side end of the first part of the channel reduced thickness of the insulator between the tabs on the one hand and the drain on the other serves in the invention in particular to lower the avalanche breakdown voltage in the area under the flap and / or to reduce the avalanche effect caused by this or by other effects, e.g.

Fowler-Nordheim tunnel effect, given minimum lobe drain voltage, which is necessary for extinguishing via the flap to the drain. This minimum voltage should be small when erasing in comparison to the memory gate-drain voltage that is used for Deletion by means of the avalanche effect at the end of the channel on the drain side, i.e. by means of an avalanche breakthrough between the drain and the first part of the canal is necessary were. By making the insulator thicker at this drain-side end of the first channel part is than in the area of the flap, the sr deletion may be necessary Lobe drain tension be made sufficiently lower than the voltage that leads to an extinction over the end of the channel on the drain side would be necessary.

Poisoning of the insulator, especially in the canal area, will occur the invention avoided because the programming via an isolator point in the channel area, but the deletion reliably via another, away from the channel in the area of the Insulator site lying on the flap takes place.

The invention is based on the clarity shown in the figures further explained for simplified exemplary embodiments, FIG. 1 being the top view of an exemplary embodiment, FIG. 2 shows a cross section through that shown in FIG Exemplary embodiment and FIG. 3 shows another exemplary embodiment according to the invention demonstrate.

The embodiment shown in Figure 3 is in terms of several details - apart from the special measure according to the invention - very similar to those in 3 and 4 of the main application examples described, which is why the explanations 3 may be briefly summarized here accordingly. Can be seen in this The top view of the n-channel memory FET shown in FIG Drain D and Source S.

In between is the first part K1 of the canal, which is made by means of canal injection at the Kanalstel7e V programmable memory gate G1 and controlled by the control gate G2 is, as well as the remaining part K2 of the channel, which is only controlled by the control gate G2 will. The channel is from the storage gate and control gate only so I; e rt isolated by thin oxide. The cloth L is only removed from the drain by thin oxide D separated. The drain does not border on the remaining part K2, but only on the first part K1 of the channel.

The tab L is isolated from the substrate by the conductive, thick oxide Connection LK to the storage gate G1 *) via the tab L, e.g. by means of a Avalanche breakthrough at the pn junction covered by the lobes L, can be deleted.

For this purpose, a comparison is made with the voltage at the relevant connection area, here e.g. + 30V on the drain D, negative voltage on the control gate G2, e.g. OV on G2, as well as the avalanche breakdown voltage at the pn junction between the drain, here + 30V to D, and substrate HT, e.g. OV or -5V to HT. *)tied together, so that the memory gate S1 e.g.

Are several n-channel storage # ETs'drainside and source side, with each other connected, their control gates not connected to each other and therefore separated are controllable, then even a bit-by-bit deletion can be achieved.

For example, a concrete example was used to refer to the associated Drains + 30V, possibly -5V to the substrate. To the control gate of the to be deleted n-channel memory FETs were placed at the control gates of the n-channel memory FETs that were not to be erased a strongly positive voltage, e.g. + 25V. Only that would then be deleted n-channel memory FET with comparatively low control gate voltage, here OV, since only with this FET the voltage of the charged memory gate is initially around -10V, with the remaining wBTs in the charged state, however, it was approx + 12V each - only with the one The FET to be erased was therefore dependent on the voltage of the floating memory gate Drain / substrate breakdown voltage or the threshold voltage for the Fowler-Nordheim tunnel effect Be exceeded in the flap area.

Used in addition to the avalanche effect or instead of the avalanche effect other effect, e.g. the Fowler-Nordheim tunnel effect specified in the main application used for extinguishing, then the inventive dilution of the isolator is below the flap L - compared to the insulator thickness at the drain-side channel end V - often also cheap. This dimensioning according to the invention namely also the minimum voltage is reduced at which the Fowler-Nordheim tunnel effect causes extinction leads over the flap to the drain covered by the flap.

Because of the division of the channel into a first part, K7 and a remaining part K2 even an excessive erasure without malfunction permissible and programming can also be done with low operating voltages can be achieved because of the use of channel injection, as stated in the main application has been received.

Fig. 1 shows the top view of a similar embodiment. Even here the channel is in a first part K1 and the remaining part K2 between drain D and Source S split. The first part K1 of the channel also points here on the drain side a constriction by the memory gate G1 - as well as the control gate G2 - although normal in the canal area by thin oxide, but in the two areas Do as well as in the Areas you are isolated from the substrate by thick oxide, see also Fig. 1 of the main application.

The tab L is connected to the memory gate G1 via the connection SK. As is often the case with memory matrices, the control gate G2 has performed in a similar manner - about the Form one through all memory cells of the matrix row continuous rail. It is also assumed here that all memory cells of the same matrix row are each connected at their source S, which is why the source S is expanded accordingly and each has a connection line for all sources the same line forms. The connecting lines to neighboring memory cells can also run differently according to the application P 25 25 062.8 = 75 P 6105.

FIG. 2 shows a section through plane II shown in FIG - II. This clearly shows that the source S and the drain D contain p-doped substrate is separated from the compound BK by thick oxide Du. The cloth L is only separated from drain D by thin oxide. That through several storage cells outgoing control gate G2 has a capacitive and indirect effect on the Is3 # thin oxide Storage gate G1 via the connection LK formed here over the largest possible area as also directly to the memory gate G7 in the area of the first channel part K1 - thereby the capacity between control gate G2 and memory gate O1 is considerably greater than if only in the area of the ground channel part Ki there is a capacitive action from the control gate G2 would be provided on the memory gate G1. This increased capacity can also the operating voltage at the control gate G2 can be lowered.

According to the invention, in the areas Be, see FIGS Area of the pn junction between drain D and substrate covered by tab X. considerably thinner insulator, e.g. only 650A thick insulator Is2, provided - im Comparison with the e.g. 1200 A thick insulator at the drain-side end of the channel, that is, at the drain-side end of the memory gate G1. By such Sizing the isolator can both reduce the risk of laughable word interference as well as avoiding the risk of isolator poisoning, which will be discussed below will be. According to the invention, the insulator 1s2 is between the tabs S and the part of the drain D covered by the rag is thinner than the insulator between the drain-side Memory gate end and the drain. As the rag covers part of the drain, it becomes in the invention by the relative thinness of the insulator under the lobe - im Compared to the relatively thick insulator between memory gate and drain - ensured that the recharging is reliable during a relatively large number of, e.g. 30, recharging cycles can be done without poisoning.

To avoid neighboring word interference, the isolator must be on the drain side End of the channel between memory gate and drain have a certain minimum thickness, so that no unwanted partial deletions due to the avalanche effect during programming or another effect leading to unloading, e.g. Fowler-Nordheim tunnel effect, occur in already programmed further such n-channel memory FETs; see. the explanations for F3 in Figure 2 of the main application. This minimum thickness must be there the rag covers the drain, for the same reason also the insulator between the tab and the drain, since this is where the memory gate and the tab are attached to the Adjacent drain. If the insulator is thinner under the rag than under the drain side The end of the memory gate is, as provided in the invention, must in order to avoid a neighboring word disturbance to avoid putting the insulator between the rag and drain at least the one because of F3 Required minimum thickness, e.g. 650 A, and the insulator between Storage gate and drain have an even greater thickness than this, e.g. 1200 Å. Through this it is also ensured that the deletion takes place via the cloth instead of via the pn-Ub # takes place at the drain-side end of the channel. If due to manufacturing tolerances there would really still be a slight neighboring word disturbance, then this would be vmrde Partial deletion can also be done using the cloth. Because at the drain-side end of the channel If the insulator is thicker than in the area of the flap, this is done on the drain side of the canal certainly not a partial erasure, but at most via the flap, whereby poisoning is avoided even with a neighboring word disorder.

In this specific example it was shown that both the avalanche effect can use under the rag to erase, as well as one of the others shown Effects, e.g. the Fowler-Nordheim tunnel effect; the avalanche effect was used primarily to delete, then in this specific example the Control gate e.g. 0T, to the drain + 30V and to the substrate -5V. One used above all the Fowler-Nordheim tunnel effect, then one put on the control gate OV and the drain about + 30V, while the substrate was floating. Mainly the gate surface effect was used off, then you put steep pulses (100 ns leading edge) in short intervals (100es) with amplitudes of approx. + 30V with a floating substrate potential. Often overlay the different effects in practice more or less simultaneously.

The low programming and erasing operating voltages required for the invention because of their relatively low amplitude, they can easily be removed from the edge electronics Memory module are supplied, which is also a step forward in terms of operational reliability of the n-channel memory FET.

The division of the canal into a first and a remaining part even allows excessive erasure of the memory gate in which the memory gate is positively charged instead of just being discharged. In this respect, too, is operational reliability of the invention very big.

The n-channel memory FET according to the invention is thus both in programming as well as when deleting particularly reliable and especially with particularly low Operating voltages can be operated.

To produce the examples shown in the figures, conventional Use integration methods. E.g. one can first put HT on the p-doped substrate Let the insulation layer 1s1 grow on. Following a free etching in the area From source S, drain D and lobes L or Be to the substrate, there is an oxidation with the thickness # representing a difference formed by the intended one Oxide thickness x in the channel area on the drain side under the memory gate G1 (with respect to x compare the main application, Fig.1) 'reduced by the intended oxide thickness 1s2 under the rag. This oxide layer of thickness a is used in the area Be a mask that covers the rest of the skin. After a subsequent Growing an oxide layer of thickness s2 \ st (oxidation) y both in the canal area as well as under the rag, see Fig. 2, is made of polysilicon Memory gate G1, including the connection LK and the tab L, applied. After an insulating layer 1s3 is grown, it becomes made of polysilicon Control gate G2 established. The source and drain regions are preliminarily etched the n $ + doping of the source S, the drain D and at the same time the control gate G2. This is followed by the production of the protective oxide layer Is4.

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Claims (5)

Claims 1.n-channel memory FET according to claim 6 of the application P 25 13 207.4-33, especially for the program memory of a telephone switching system, characterized in that the first part (K1) of the channel completely - or almost, that is, only through a narrow section of the remaining part (K2) of the channel separated - adjacent to the drain (D) and that the insulator (IsZ) between lobes (L) on the one hand and the part covered by the flap (L) away from the canal of the drain (D), on the other hand, is thinner than the insulator between the memory gate (G1) and the drain-side end of the first part (K1) of the channel. 2. n-channel memory FET according to claim 1, characterized with one Operating mode that when deleting, i.e. discharging the memory gate (ci), an opposite the control gate (0 X at G2) positive voltage to the drain covered by the tab (L) (+30 V to D) is applied. 3. n-channel memory FET according to claim 2, with one characterized thereby Operating mode that the potential of the substrate is floating. 4. n-channel memory FET according to claim 2, characterized with one Operating mode that the avalanche breakdown voltage on the covered by the lobes (L) pn junction placed between the drain (+30 V at D) and the substrate (-5 V at HT) will. 5. n-channel memory FET according to one of the preceding claims, with an operating mode characterized in that -during the deletion of a drain side further n-channel memory FET 'connected in parallel to himself at his control gate to delete a comparatively low voltage (0 V) is - with an operating voltage suitable for erasing the further n-channel memory FET at the drain (+30 V at D) and / or at the substrate (-5 V at HT) and with a strongly positive, the drain voltage at least similar to itself applied voltage at the control gate (+30 V at G2) there is no deletion itself, but only at lower, voltages supplied to it would occur at the control gate (0 V at G2).