DE2613895A1 - FET data storage element with low driving voltages - uses overlapped gate electrodes and depends on avalanche effects in telephone exchanges - Google Patents

Abstract

A field effect n-channel storage element is typically for use in storage units in telephone exchanges, it depends on avalanche or alternatively tunnelling effects and requires only low writing and erasing voltages. A source (S) and drain (D) both of N type semiconductor are grown in a P type substrate (P) and two gate electrodes (G1, G2) and an auxiliary layer (LK) divided into two parts (K1, K2) and separated by oxide layers of various thicknesses, are deposited on this. The device depends for its storage operation on avalanche or alternatively on Fowler Nordheim type tunnelling across the oxide layers between the slightly overlapped (L) electrodes.

Description

n-channel safe FET

The invention relates to an advantageous development of the current Claim 6 of the main application P 25 13 907.4-33 = VPA 75 P 6039 BRD specified n-channel memory FET. The invention also relates to the same advantageous further development of pus formations of the n-channel memory FET specified in this claim 6 of the parent application. the The main application itself is an addition to application P 24 45 137.4-33. Both the essential content of the last-mentioned application and the essential one The content of the main registration is already in the corresponding to both registrations Luxembourg patent 72,605.

The invention is based on claim 6 of the main application, so from an n-channel memory FET with at least one gate, namely with one on all sides surrounded by an insulator, floating memory gate, in which the Storage gate the electron injecting Rana injection - i.e. charge reversal by im own conductive channel strongly accelerated and thereby heated electrons, due to their heating by an electrical one acting in the source-drain direction Field to overcome the energy threshold to the conductivity band of the insulator and thereby get to the memory gate - is exploited, whereby the channel injection for programming, thus charging the storage gate, is exploited, so the storage gate after this Charging by means of its negative charge by influencing the source-drain current acts inhibitory manner on the source-drain path, with an additional, a Connection having controllable control gate is provided, which is capacitive the memory gate acts, the memory gate being equal to only one channel length extending over the entire width of the channel first part of the Canal covered, which contains the canal site from which by means of canal incection When programming the heated electrons get to the memory gate, or which one at least adjoins this channel point, although the control gate, but I do Memory gate, covering the remaining, electrically in series part of the channel and its memory gate laterally from the channel a conductive one from the substrate through a thick oxide layer insulated connection with one attached outside the duct, having conductive tabs covering part of the source or drain over a thin oxide layer covered.

If the rag covers the source, the erasure to the source occurs there. The flap L serves, as described in the main application, in particular for erasing, i.e. for discharging the memory gate G1. The lobe L, which passes over the through a thick oxide layer isolated from the substrate connection is connected to the memory gate is, namely, allowed, the programmed, i.e. negatively charged by means of sewer incision To delete the storage gate, i.e. to discharge it, e.g. by placing at the pn junction under the tab, thus an avalanche breakdown is produced at the pn junction between source and substrate is, whereby there heated holes by means of the avalanche through the insulator get to the cloth and thereby discharge the storage gate. On this and others Deletion methods is already in the main application, page 15, line 22 to page 16, Line 37 pointed out.

In the main application it is also described that the remaining part of the canal can be divided into two sections, between which the first part of the Canal lies.

The n-channel spelcher FET described in claim 6 of the parent application has the advantage of being able to be programmed with low operating voltages, and in addition to being able to be erased excessively over the cloth, there a positive storage gate charge is harmless to the operation of this FET.

This is already described in the main application. This Soeicher FET is therefore particularly reliable and also with low Operating voltages programmable.

By Japan J. Appl. Phys. 13 (1974) here. 2, 367/368 are experimental tested formulas, regarding a common MOS-FET, for the dependency of the Avalanche breakdown voltage at a source-substrate pn junction of the insulator thickness known. D2-after, the avalanche breakdown voltage decreases the thinner the insulator between the gate and the pn junction.

Through a lecture raanuscript by Kikuchi, Chya, Kamaya, Koike and Yamamoto at the First Europa Solid State Circuits Conference, September 2-5 1975, Canterbury, England, in particular Figures 1 and 2, is in the "erased" state leading n-channel SAiS memory FET with then positive gelandem memory te known, discharge its memory gate during "programming" with heated electrons and is positively charged when "erasing" with heated holes. The heating will each effected by means of the avalanche effect, namely during "programming", namely Discharging, between drain and substrate and when "erasing", namely charging, between Source and substrate, see also the initial state according to FIG Improvement of the efficiency with 1? Programming ?? with heated electrons is the insulator thickness in the channel area, namely at the drain / substrate pn junction in a section of this transition comprising at least part of the channel width, between memory gate and drain smaller than at the other places in the channel area, namely especially between the memory gate and the substrate. - The invention works, however not from an n-channel SAMOS memory FET, but from one via channel injection programmable, i.e.

n-channel rechargeable memory FET. In the case of the invention, the rest the memory gate is not charged positively with holes, but negatively with electrons. In addition, in the case of the invention, the deletion does not take place in the channel area, but over the rag. The deletion takes place in the same way as the programming for the Invention different from this known n-channel SAMOS memory FET, the latter also has a different structure as the invention, e.g. because it does not have a flap on the side of the canal.

In the main application is based on the intersection of the line F1 and the line F3 of FIG. 2 there explains that the Isclator, e.g. SiO2, between the memory gate G1 and the channel must have a minimum thickness, e.g. 450 A, so that when programming the n-channel memory FET there are no undesired partial erasures (Neighboring word disturbances ") in neighboring, namely connected at their drains, already programmed further such n-channel memory FETs occur.

The invention solves the problem of being as reliable as possible and to provide low voltage operable n-channel Spelcher FETs, namely one by means of channel inspection with operating voltages that are as constant as possible, which therefore remain largely the same from charge to charge, programmable and then a negatively charged floating memory gate n-channel memory FET, reliably over the flap on the side of the actual canal, e.g. by means of the avalanche effect or especially by means of the Fcwler-Nordheim tunnel effect according to the main application, is completely or even excessively erasable.

The programming and the deletion should be accordingly in each case take place via different, specific places in the isolator, namely the programming in the canal area and the extinguishing always over the rag, whereby the rapid poisoning of the isolator is avoided and whereby'to avoid neighboring word interference, the Avalanche breakdown voltage or the threshold voltage of others suitable for lashing Effects' in the actual channel should not be lowered. In addition, the invention a decrease in the avalanche breakdown voltage between substrate and source in the area of the lobe and / or a decrease in the source control gate operating voltage when deleting - in comparison with the case where the insulator is under the tab is of the same thickness as under the drain-side end of the memory gate, without doing so by lowering the avalanche breakdown voltage on the drain side End of channel increasing the risk of neighboring word disorders.

The definition of drain and source corresponds to the direction of the channel electron current while programming.

As already indicated above, the invention is based on the above-cited, in claim 6 of the parent application specified n-channel memory FET. The task the invention is achieved in that the first part of the channel completely - or almost, i.e. only through a narrow section of the remainder of the canal separated - adjacent to the drain and that the insulator between lobes on the one hand and the source covered by the tab, on the other hand, is thinner than the insulator between the memory gate and the drain-side end of the first part of the channel.

The first part of the canal should be completely - or almost, i.e. only through a particularly narrow section of the remainder of the canal adjoin the drain, because then when the channel electrons are heated, particularly in the vicinity of the drain low programming operating voltages can be achieved, especially if possible near the drain a channel inhomogeneity as an acceleration path, e.g. a channel narrowing, to heat the channel electron is attached.

The compared to the drain-side end of the first part of the channel reduced thickness of the insulator between tabs on the one hand and source on the other is used in the invention to lower the avalanche breakdown voltage in the range under the flap and / or to reduce the avalanche effect caused by this or by other effects, e.g. Fowler-Nordheim tunnel effect, given lobe-source minimum span, which is necessary for deletion via the tab to the source. This minimum voltage should be small when erasing in comparison to the memory gate - drain voltage,, the to the Deletion by means of the avalanche effect at the end of the channel on the drain side, i.e. by means of an avalanche breakthrough between Drein and the first part of the Channel, would be necessary. By the insulator at this drain-side end of the first channel part is thicker than in the area of the lobe, the lobe-source voltage required for deletion can be be made sufficiently lower than the voltage that leads to an extinction over the end of the channel on the drain side would be necessary.

Poisoning of the isolator, especially in the canal area, is caused by the invention avoided because the programming via an isolator point in the channel area, but the deletion reliably via another, away from the channel in the area of the Insulator site lying on the flap takes place.

The invention is based on the shown in the figures, the uMerichtlichkeit explained in more detail because of simplified exemplary embodiments, FIG. 1 being the top view of an exemplary embodiment, FIG. 2 shows a cross section through that shown in FIG Embodiment, FIG. 3 shows another embodiment according to the invention, which corresponds to FIGS. 3 and 4 of the main application, and FIG. 4 shows an angled one Show cross-section through the embodiment shown in FIG.

The embodiment shown in Fig. 3 is essentially apart of the special measure according to the invention - already in the main application described, which is why the explanations can be kept briefly here. In this top view of the n-channel memory FET, the connection areas can be seen, So drain D and source S. In between is the first part K1 of the channel, which is from by means of canal injection at sewer point V programmable memory gate G1 and is controlled by the control gate G2, as well as the remaining part K2 of the channel, which is only controlled by control gate G2. The channel is from the memory gate and Control gate only isolated by thin oxide. The lobe L is only through thin oxide of the source S is separated, the source not at the first, but only at the remaining part of K2 of the channel is adjacent.

The tab L is isolated from the substrate by the conductive, thick oxide Connection LK connected to the memory gate G1, so that the memory gate G1 via the flap L e.g. by means of an avalanche opening on the flap L covered pn junction or another effect suitable for deletion can be deleted. For this purpose, a comparison with the voltage at the source, here e.g.

+15 V on source S, negative voltage on control gate G2, e.g. 0V at G2 and, if applicable, the avalanche breakdown voltage at the pn junction between the source, here +15 V at S, and substrate HT, e.g. 0V or -5V at HT place.

To lower the voltage required for erasure between the Source S covered by the tab and control gate G2 is the insulator in the area Be of the pn junction covered by the tab, between the source S and substrate HT, considerably thinner than in the area V of the constriction at the end of the channel on the drain side, between Memory gate G1 and the drain D. As a result, by means of the avalanche effect in the area Be caused the creation of holes with lower operating voltages at source 5, here e.g.

+15 V than without the measure according to the invention, i.e. with the same Thickness of the insulator both in the area Be and at the drain-side channel end V, can be achieved. The memory gate G1, which is negatively charged in the programmed state can therefore be deleted with the invention with pleasantly low operating voltages.

Used in addition to the avalanche effect or instead of the avalanche effect another effect, e.g. the Fowler-Nordheim tunnel effect specified in the main application, for Delete used, then the inventive dilution of the isolator is below the flap - in comparison to the insulator thickness at the drain-side channel end V - also cheap. This dimensioning according to the invention also results in the minimum voltage reduced, in which the Fowler-Nordheim tunnel effect for extinguishing leads over the flap to the Source S covered by the flap.

Because of the division of the channel into a first part, K1 and a remaining part K2 even an excessive deletion without operational disruption permissible and programming can also be done with low operating voltages because of the use of the channel injection can be achieved what is already in the main application has been received.

Fig. 1 shows the top view of a similar embodiment.

kuch here is the channel in a first part k1 and a remaining part Part K2 divided between drain D and source S. The first part K1 of the channel has look for a constriction af here on the drain side, in which the memory gate G1 and the control gate G2 - normal in the canal area due to thin oxide, but in both areas Do as well as in the areas you through Dickoxyd with z. B. 10,000 A thickness of the substrate is isolated, see also Fig. 1 of the main application.

The tab L is connected to the memory gate G1 via the connection LK. The control gate G2 has here - as is often the case with memory matrices in a similar way carried out - approximately the shape of a through all memory cells of the matrix line Rail. It is also assumed here that all memory cells have the same matrix row Sp are connected together at their source S, which is why this connection area S is expanded accordingly and a connecting line Sp of all sources is the same Line forms.

FIG. 2 shows a section through the plane shown in FIG. 1 II - II. This makes it clear that the source S containing, p-doped Substrate is separated from the connection LK by Dickoxyd Du. The lobes L is separated from the source S only by thin oxide. The one going through several memory cells Control gate G2 has a capacitive and indirect effect on the memory gate via thin oxide Is3 G1 via the connection LK as well as directly to the memory gate Gl in the area of the first channel partly K1 - this is the capacity between the control gate G2 and memory gate G1 are considerably larger than if only in the area of the first channel part K1 a capacitive action is provided from the control gate G2 on the memory gate G1 were. This increased capacity can also reduce the operating voltage at the control gate G2 be lowered.

According to the invention, in the areas Be, see FIGS in the area of the pn junction between source S and substrate covered by the lobe L, a considerably thinner insulator, e.g. only 300 I thick insulator Is1, is provided - in comparison with the isolator II in the canal area, especially with the one according to the main application optimal e.g. 600 A thick insulator at the drain-side end of the channel, i.e. at the drain-side End of the memory gate G1. This is also due to the angled one shown in FIG Cross-section through the embodiment shown in Fig. 1 explained by namely there, too, the insulator in the area Be is thinner than in the area of the first part AI of the channel. Such a dimensioning of the insulator 1s1 and 11, cf. 4, as already explained with reference to FIG. 3, the operating voltages can be used when erasing be degraded - and without the danger of neighboring word disturbances and the danger to increase insulator poisoning.

To avoid neighboring word interference, the isolator, at the end of the channel on the drain side, between the memory gate and drain only a certain one Have a minimum thickness so that there are no undesired partial deletions during programming due to the avalanche effect or the Fowler-Nordheim tunnel effect in already programmed further such n-channel memory FETs occur, cf.

the explanations for F3 in FIG. 2 of the main application.

Since the rag has a particularly thin insulator part of the The source is covered by the inventive dimensioning of the insulator thickness so the avalanche breakdown voltage under the tab is lower than on the drain side End of the memory gate, whereby the voltage is reduced by means of the avalanche effect when erased can choose between source and substrate particularly low.

In order to avoid neighboring word disorders, it is assumed that that the minimum thickness required in the main patent, e.g.

500 A, the insulator between the memory gate and drain is maintained. It turned out that the invention also required the erasure The voltage between the source and control gate can be selected to be significantly lower, as if the insulator is under the tab and under the drain-side memory gate end would be the same thickness, both if the avalanche effect under the cloth to erase, as well as using one of the other suitable effects, e.g. the Fowler-Nordheim tunnel effect. Above all, the avalanche effect was used to delete, then for a specific example, the Control gate e.g. +, to the source +15 V and to the substrate -5 V. This was used before mainly the Fowler-Nordheim tunnel effect, then one put O V on the control gate and +15 V to the source while the substrate was floating. One in the operating state of one Memory with inventive n-channel Speicker FETs is floating substrate HT especially applicable if the substrate of each of these FETs is itself a Island-shaped semiconductor layer on sapphire, spinel or another insulator body forms - such a structure is in itself called a so-called

ESFI-FET and SOS-FET known. Especially if you used the one in the main application specified gate surface effect, then you put steep pulses (100 ns leading edge) at short intervals (100 ps) with amplitudes of approx. +15 V to the source at constant at the un control gate and with floating substrate potential. Often overlap in in practice the different effects more or less simultaneously.

The invention even allows the avalanche breakdown voltage to fall below the lobe covering the source are so severely harmed that, at O V, between Control gate G2 and source S, the programmed, e.g. then to -10 V compared to the Source charged storage gate by the avalanche effect or another of the Effects not yet partially or completely erased when between source and substrate the usual bias voltage for normal operation, e.g. O V at source S and -5 V at Substrate2 is applied This means, for example, that in this case the source / substrate breakdown voltage only must still be a little more than 5 V, and that above all the Fowler-Nordheim tunnel effect Triggering voltage, when discharging via the tab to the source which is at O V only needs to be a little over 10V. A Sio isolator under the rag is allowed therefore e.g. about 250 Å thick, a partial erasure by the - in this case Particularly important -Fowler-Nordheim tunnel effect in the context of this during normal operation to effect applied operating voltages.

In this dimensioning case, at the control gate G2 and -5 V on substrate HT, only an erase voltage of a little over +10 V, e.g. +15 V the source S is necessary to completely discharge the memory gate G1, in particular then, if the effectively effective capacitance between control gate G2 on the one hand and Storage gate 1 plus connection LK plus tab L on the other hand is much larger, E.g. 5 times greater than the internal capacity between storage gate G1 plus connection LK plus tab T on the one hand and source o plus drain D plus substrate HT on the other is if the actual channel is not conductive. - Would be instead of the inventive The dimensions of the Sio2 isolator are the same under the tabs covering the source as large as the Sio2 insulator thickness at the end of the storage gate on the drain side, namely approx. 600 Å, cf. the main application, then experience has shown that an erasure voltage would be of approx. + 30V at the source with 0 V at the control gate and -5 V at the substrate. By the invention could reduce the extinguishing voltage by approx.

15 V - without the risk of disturbance to the neighboring area when programming in other such n-channel memory FETs that have already been programmed to be favored as long as the required minimum insulator thickness between drain and memory gate was adhered to.

The low programming and erasing operating voltages required for the invention can easily be removed from the edge electronics of a memory chip due to their low amplitude which is also a step forward in terms of the operational safety of the represents n-channel memory FET.

The division of the canal into a first and ei part makes it easy an excessive deletion of the Spe @@ de @te in which the storage gate is positively charged will be loading instead of @@@. In this respect, too, the operationally reliable invention very large.

The n-channel memory FET according to the invention is therefore as well as programming as well as when deleting particularly operational @@@@ especially with particularly low Operating voltage can be driven Conventional for the production of the examples shown in the figures Use integration methods. For example, the insulator layer can be placed on the p-doped substrate RT the thickness that is between lobes and see. Then you can local oxidation at the end of the channel increases the thickness of the insulator q Thickness I1 provided at the end of the channel, see Fig. 4, finally through local oxidation die Dickoxydschi Do and Du, outside the Be and des area Let the channels wake up. After applying the memory gate binding LK and the cloth L the thin insulator @@@ and then the control gate G2 can be attached, and, the drain and source areas releasing etchings as @@@ HT, the n ++ doping from Drain D and Source 5 Finally, one can use an in not shown insulator protective layer grow la 6 patent claims *) with e.g. 500 Å 4 figures

Claims (6)

P a t e n t a n s p r ü c h e n-channel memory FET according to claim 6 of the application P 25 13 207.4-33, in particular for the program memory of a telephone switching system, d a d u r c h g e -k e n n n z e i c h n e t that the first part (K1) of the channel completely - or almost, i.e. only through a narrow section of the remaining part (K2) of the channel separated - adjacent to the drain (D) and that the insulator (Is1) between the tab (L) on the one hand and the source (S) covered by the tab (L) on the other is thinner than the insulator (I1) between the memory gate (G1) and the drain-side End of the first part (K1) of the channel. 2. n-channel memory FET according to claim 1, d a d u r c h g - -k e n It is not noted that the self-capacitance between the storage gate (G1) plus connection (LK) plus tab (L) on the one hand and control gate (G2) on the other hand, considerably larger (5 times larger) than between memory gate (G1), connection (LK) and tab (L) on the one hand and source (S), drain (D) and substrate (HT) on the other hand. 3. n-channel memory FET according to claim 1 or 2, d a d u r c h g e It is not indicated that the channel has a constriction (V) on the drain side. 4. n-channel memory FET according to claim 1, 2 or 3, with ad a D u r c h e k e n n n n z e i c h n e t e n Operating mode that when deleting, ie Discharge of the storage gate (G1), one positive compared to the control gate (OV at G2) Voltage is applied to the source covered by the tab (L) (+15 V at S). 5. n-channel memory FET according to claim 4, with a d a d u r c h not in e n g e n g e s operating mode (by means of the Fowler-Nordheim tunnel effect), that the potential of the substrate is floating (SOS-FET). 6. n-channel memory FET according to claim 4, with ad a -d u r c h not in e n g e n g e s Operating mode (by means of the avalanche effect) that the Breakdown voltage at the pn junction between source covered by the lobe (L) (+15 V to 5) and substrate (-5 V to HT).