DE2547870A1 - Speed independent instantaneous direction indicator - uses memory flip flop, reset flip flop and two NAND gates - Google Patents

Abstract

The instantaneous direction indicator detects direction of motion without delay and independently of speed. The clock inputs of a memory flip flop each have a 2-input NAND-gate connected to it. The inputs of the NAND-gates receive signals denoting a change in state (direction), the one input signal to each gate being direct and the other input delayed. The gates comprising the memory flip flop each have a further input to block the outputs connected to a reset flip flop. The reset flip flop is set by an input (eg supply'on'). The outputs of the whole circuit can therefore be forced to block at H.

Description

DESCRIPTION

Circuit arrangement for the instantaneous detection of a direction of movement There are numerous applications where the direction of movement of a medium is convenient should be recognized without delay, regardless of the speed and reliably. Previously known methods are based either on two answering stations and a simple one Jump coding or from an inquiry station and a coding with different long pulses.

However, these circuits are relatively complex and expensive, and so will be always go through both answering points, or all pulse sequences are queried, which always leads to a more or less long recognition time.

The following invention avoids these disadvantages.

It is also used here by two interrogation points (light barriers) and a simple jump coding (light-dark) assumed.

The direction of movement is recognized at the moment where the code marking passes one of the two answering stations.

If then after some time (from the speed of the medium and depending on the distance between the interrogation points) also the switching status at the second sensor changes, this is irrelevant for the direction recognition.

The effort for this movement locator is - if one of the usual Signal processing refrains from - just a quadruple-2-input-nand-gate, 2 capacitors and 2 resistors in their values can be selected within wide limits.

Circuit description Gates I and II are designed so that each one input at the same time via a low resistance to the free input of the other gate and leads to the circuit input.

A capacitor at each of these inputs (A 'and B') is used to delay the signal. The delay time must be at least a gate delay time (about 40 nanoSekO) be.

At the top, this delay time is only due to the pulse train in the case of recurring code pulses, as is the case with the detection of a direction of rotation occurs, limited.

The following table should clearly show how the circuit works: A, B = inputs C, D = outputs AA '(BB' CDEB 1 HHHHHHLL 2 LHHHLHHL 2 + t LHHLLHHH 3 LHLLLHHH 3 + t LLLLLHHH 4 HLLLLHHH 4 + t HLLHLHHH 5 HLHHLHHH 5 + t HHHHHHLL Tab. 1 It was assumed that the code at input A arrives first. The table clearly shows that the direction at the exit is fixed at the same time the code arrives. The further change of the state at the input does not change the output information until the neutral position. If necessary, another memory can be added to the output, e.g.

a polarized relay save the last stamped state Xz.B. even in the event of a power failure).

Fig. 1 shows the input voltage curve for the table was taken as a basis.

By moving the interrogation points spatially, the code signals removed out of phase. t gives the signal delay time in the table the two R-C links on; T is the maximum possible delay time. To the interference immunity In order not to worsen the circuit, the resistor R should be selected to be low-resistance (47 ohms). With a C of 0.1 61F, around 50 times the gate delay time is achieved, the upper limit frequency of the pulse trains will still be around 50 kHz.

2 finally shows the overall circuit.

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Claims (4)

P A T E N T A N S P R Ü C H E 1.) Circuit arrangement for recognition and storing a change of state at an output of the circuit as a function thereof at which input this change of state occurs first, characterized that the clock inputs of a memory? lip-flop äe are preceded by a 2-input NAND gate whose inputs experience the change of state, namely å e an input directly and å an input delayed. 2.) Circuit arrangement according to claim 1, characterized in that Another memory flip-flop is located at the output. 3.) Circuit arrangement according to claim 1, characterized in that a polarized relay is switched on at the output. 4.) Circuit arrangement according to claims 1-3, characterized in that that the gates forming the memory flip-flop ae a further input for blocking of the outputs that lead to a reset? lip-Fiop, which from an input is set off (e.g. power on) and thus the outputs of the overall circuit inevitably blocked to H, and which of two other inputs by the incoming one Information pulse L is reset.