DE1957278C3

DE1957278C3 - Electronic group locking device for carrier frequency systems

Info

Publication number: DE1957278C3
Application number: DE19691957278
Authority: DE
Inventors: Joel Dr.-Ing. 7150 Backnang Korn
Original assignee: Telefunken Patentverwertungs GmbH
Current assignee: Telefunken Patentverwertungs GmbH
Filing date: 1969-11-14
Publication date: 1977-05-26

Description

Standes und einer Zenderdiode Basisspannung erhalten. Die Zenerdioden wirken als Schwellenglieder und ihre Toleranzen beeinflussen direkt die Verzögerungszeiten.Stand and a Zender diode base voltage. The Zener diodes act as threshold elements and their tolerances directly influence the delay times.

Aufgabe der vorliegenden Erfindung ist es, den Aufwand und die Toleranzen der einzelnen Verzöge- > rungszeiten zu verkleinern. Als Lösung werden erfindungsgemäß die Verzögerungsschaltungen RC-Glieder verwendet, denen Emitterfolgerstufen mit npn-Transistoren nachgeschaltet sind, wobei als Schwellglied eine Zenerdiode in der gemeinsamen ι ο Zuleitung zu den Emittervorwiderständen der Emitterfolgerstufen angeordnet istThe object of the present invention is to reduce the effort and the tolerances of the individual delay times. As a solution, the delay circuits RC elements are used according to the invention, which are followed by emitter follower stages with npn transistors, a Zener diode being arranged as a threshold element in the common lead to the emitter series resistors of the emitter follower stages

Ein Ausführungsbeispiel der Anordnung nach der Erfindung zeigt die Figur. Die Transistoren 7s 1, Ts 2, 7s3 und Ts4 sind die Transistorschalter, die die is Gruppen über die Ausgänge Gl, G 2, G 3 und G 4 sperren. Der Transistorschalter TsI wird leitend gemacht, indem sein Emitter über den bperrkontakt K an — UB angelegt wird; seinen Basisstrom erhält er dann über einen Basisvorwiderstand Rb aus der :o Betriebsspannung. Die zur Verzögerung dienenden RC-Glieder Rvl/Cl, Rv2IC2, Rv3/C3 sind an die Kollektoren der Transistoren Ts 1, Ts 2, 7s 3 über Entkoppeldioden Dl, D 2, D 3 angeschlossen, die nur dann leitend sind, wenn die zugehörigen Transistoren :? leitend sind. Wenn die Transistoren Ts 1, 7s 2 und Ts 3 gesperrt sind, sind auch die Dioden Di, D2 und D3 gesperrt und verhindern, daß über die RC-Glieder an die Basisanschlüsse der den RC-Gliedern nachfolgenden Emitterfolgerstufen Tsh 1, Tsh 2 und Tsh 3 mit den yo Emittervorwiderständen ReI, Re 2 und Re 3 zu große Sperrspannungen gelangen. In der gemeinsamen Zuleitung zu letzteren Emittervorwiderständen liegt eine Zenerdiode D 4, die als Schwellenglieddiode wirkt.The figure shows an embodiment of the arrangement according to the invention. The transistors 7s 1, Ts 2, 7s3 and Ts 4 are the transistor switches that block the is groups via the outputs Gl, G 2, G 3 and G 4. The transistor switch TsI is made conductive by applying its emitter to - UB via the blocking contact K ; it then receives its base current from the: o operating voltage via a base series resistor Rb. The RC elements Rvl / Cl, Rv2IC2, Rv3 / C3 used for delay are connected to the collectors of the transistors Ts 1, Ts 2, 7s 3 via decoupling diodes Dl, D 2, D 3, which are only conductive when the associated Transistors:? are conductive. When the transistors Ts 1, 7s 2 and Ts 3 are blocked, the diodes Di, D2 and D3 are also blocked and prevent the emitter follower stages Tsh 1, Tsh 2 and Tsh 3 with the yo emitter series resistors ReI, Re 2 and Re 3 lead to high blocking voltages. In the common lead to the latter emitter series resistors there is a Zener diode D 4, which acts as a threshold element diode.

Die Kondensatoren Cl, C2 und C3 werden über die i> Vorwiderstände RvI, Rv2 und Rv3 verzögert aufgeladen und über die Emitterwiderstände Rl. R 2 und R 3 verzögert entladen. Die entsprechenden maximalen Aufladespannungen betragenThe capacitors Cl, C2 and C3 are charged with a delay via the i> series resistors RvI, Rv 2 and Rv3 and via the emitter resistors Rl. R 2 and R 3 discharge delayed. The corresponding maximum charging voltages are

ηφπηφπ

RlRl

bzw.or.

bzw. Rl + RvI or Rl + RvI

RlRl

Rl + Rv 2Rl + Rv 2

R3R3

R3 + Ri 3R3 + Ri 3

UBUB

und sind wesentlich größer als die Zenerspannung der Schwellenglieddiode DA. Die Verzögerungszeit für das Sperren ist gegeben durch die Aufladezeit, in der die Spannungen an den Kondensatoren die Durchbruchspannung der Zenerdiode D 4 erreichen. Die Verzögerungszeit für das Entsperren ist gegeben durch die Zeil, in der die Kondensatoren sich von ihrer maximalen Aufladeipannung auf die Durchbruchspannung der Zenerdiode D 4 entladen. Durch passende Wahl der Spannungsteiler Rv l/R 1, Rν 2/R 2 und Rν 3/R 3 sowie der Zenerdiode D 4 können die gewünschten Verzögerungszeiten erreicht werden.and are significantly greater than the Zener voltage of the threshold element diode DA. The delay time for blocking is given by the charging time in which the voltages on the capacitors reach the breakdown voltage of the Zener diode D 4. The delay time for unlocking is given by the time in which the capacitors discharge from their maximum charging voltage to the breakdown voltage of the Zener diode D 4. The desired delay times can be achieved by suitable selection of the voltage dividers Rv 1 / R 1, Rν 2 / R 2 and Rν 3 / R 3 as well as the Zener diode D 4.

Da die maximalen Aufladespannungen der Kondensatoren wesentlich kleiner als die Betriebsspannung UB sind, können räumlich kleinere und damit billigere Kondensatoren eingesetzt werden.Since the maximum charging voltages of the capacitors are significantly smaller than the operating voltage UB , spatially smaller and therefore cheaper capacitors can be used.

Da die Schwellenglieddiode £>4 für alle Verzögerungsglieder gemeinsam ist, beeinflußt die Toleranz ihrer Durchbruchspannung alle Verzögerungszeiten im gleichen Maße und die Verzögerungszeiten werden weniger unterschiedlich.Since the threshold element diode £> 4 for all delay elements common, the tolerance of their breakdown voltage affects all delay times in the same dimensions and the delay times become less different.

Hierzu 1 Blatt Zeichnungen1 sheet of drawings

Claims

Patent claims:

1. Electronic group locking device for carrier frequency systems, which, in the event of a failure of a primary group consisting of twelve telephone channels, locks and unlocks this group in four groups of three against occupancy for the duration of the disturbance, in such a way that within a certain ι ο time segment (from z. B. . 1 see) no more than three channels are blocked and unblocked at the same time, whereby the beginning and the end of a fault are indicated by a blocking signal receiver by closing or opening a blocking contact and a central alarm is given from the beginning of the blocking to the end of the unblocking via a central alarm contact , with four transistor switches each assigned to a group of three being provided, and the first transistor switch from the locking signal receiver directly, the second transistor switch via a first delay circuit from the first transistor switch, the third transistor switch via a second delay circuit from the two the third transistor switch, the fourth transistor switch via a third delay circuit from the third transistor switch and a fifth transistor switch, which represents the central alarm contact, are controlled both by the blocking signal receiver directly and by the fourth transistor switch and the first transistor switch is conductive when the blocking contact of the blocking signal receiver is closed, the second transistor switch When the first transistor switch is conductive, it is delayed conductive and when the first transistor switch is blocked is blocked with a delay, the third transistor switch is delayed conductive when the second transistor switch is conductive and blocked with a delay when the second transistor switch is blocked, the fourth transistor switch is delayed conductive when the third transistor switch is conductive and blocked with a delay when the third transistor switch is blocked and the fifth transistor switch is conductive when either the blocking contact is closed or the viene transistor switch le Itend is, according to patent 1S 09 702, characterized in that FLC elements (RvMCX, RvIICl, Rv3 / C3) are used as delay circuits, followed by emitter follower stages with npn transistors (Tsh \, Tsh?., Tsh3) , with a Zener diode (D4) is arranged as a threshold element in the common lead to the emitter series resistors (ReX, Re 2, Re) of the emitter follower stages.

2. Electronic group locking device according to claim 1, characterized in that the RC-GWe of series resistors (Rv X, Rv2, Rv 3), capacitors (C 1, C2. C3) and discharge resistors (R 1, R 2, R 3) which are connected in parallel to the capacitors consist.

3. Electronic group locking device according to claim 1 and 2, characterized in that the ÄC elements are connected to the collectors of the transistor switches (TsI, Ts 2, Ts3) via decoupling diodes (DX, Dl, D 3) , these diodes only are conductive when the associated transistor switches are also conductive.

4. Electronic group locking device according to claim 1 and 2, characterized in that the series resistors (RvX, Rv2, Rv3) and the discharge resistors (RX, RX A3) of the i? C-member are chosen so that the maximum charging voltages of the capacitors (Cl , C2, C3) are significantly greater than the breakdown voltage of the Zener diode (D 4).

5. Electronic group locking device according to claim 1, 2 and 4, characterized in that the delay time for locking is given by the charging time in which the capacitors (Cl, Cl, C3) reach the breakdown voltage of the Zener diode (D 4), and that the delay time for unlocking is given by the time in which the capacitors have discharged from their maximum charging voltage to the breakdown voltage of the Zener diode (D 4).

The main patent relates to an electronic group lock; device for carrier frequency systems, the failure of a primary group consisting of twelve telephone channels caused by disturbance these Group locks and unlocks against occupancy in four groups of three for the duration of the disturbance, in such a way that no more than three channels blocked at the same time within a certain period of time (e.g. 1 see) and unlocked, the beginning and the end of an interference from a locking signal receiver through Closing or opening of a blocking contact specified and from the beginning of the blocking to the end of the Unlocking via a central alarm contact, a central alarm is given, with four each one Group of three assigned transistor switches are provided and the first transistor switch from Lock signal receiver directly, the second transistor switch via a first delay circuit from first transistor switch, the third transistor switch via a second delay circuit from the second Transistor switch, the fourth transistor switch via a third delay circuit from the third transistor switch and a fifth transistor switch, which represents the central alarm contact, both from the blocking signal receiver are controlled directly, as well as by the fourth transistor switch, and the first transistor switch at closed blocking contact of the blocking signal receiver is conductive, the second transistor switch at conductive first transistor switch delayed conductive and delayed when the first transistor switch is blocked is blocked, the third transistor switch with a conductive second transistor switch is delayed conductive and is blocked with a delay when the second transistor switch is blocked, the fourth transistor switch when it is conductive third transistor switch conductive delayed and blocked with blocked third transistor switch delayed and the fifth transistor switch is conductive when either the blocking contact is closed or the fourth transistor switch is conductive.

According to claims 4 and 5 and the embodiment of the main patent application as delay circuits Miller integrators used each one npn transistor, one capacitor between its base and its collector and contain a collector resistor, the base terminals of the second, third and fourth transistor switch from the upstream Miller integrators each via the series connection of a basic pre-resistance