DE1809702A1 - Electronic group locking device for carrier frequency systems - Google Patents

Description

Electronic group locking device for carrier frequency systems The invention relates to an electronic group locking device for carrier frequency systems.

It is known that group pilot blocking devices are used in multichannel carrier frequency systems used, which have the task in case of failure of a primary group against this group Block assignment, A primary group has twelve channels. and he is made up of different Reasons required that when locking or unlocking a primary group not all iianals of this group are operated simultaneously, but that within one In a certain time period of e.g. 1 sec, no more than three channels at the same time locked or unlocked. The blocking is usually done in such a way that that at the electrical center of the output transformer of the individual channels ground potential is applied, Another requirement is that during the entire time of the fault, i.e. from the beginning of the closure of the first canal to the end of the closure of the last channel, a central alarm contact emits ground potential to the central alarm device.

The blocking of the group is initiated when a blocking signal receiver evaluates a fault and sends ground potential to the locking device via a locking contact applies.

There are electromechanical locking devices known, which in the manner of a Counting relays are operated by current pulses. When locking, the locking device closes one after the other twelve contact tracks. When unlocking, the contact paths are sequentially opened again. These locking devices are expensive and relatively large in terms of space.

The object of the invention is to create an electronic locking device, which is cheaper and smaller than the well-known electromechanical locking g @ @e.

The electronic group locking device solving this task, which the locks and releases twelve channels of a primary group in four graves according to the invention characterized in that four are each assigned to a group of three Transistor switch provided and that the first transistor switch from the locking signal receiver directly, the second transistor switch via a first delay circuit from first transistor switch, the third transistor switch via a second verb delay circuit from the second transistor switch, the fourth transistor switch via a third delay circuit from the third transistor switch and a five-port transistor switch.

which represents the central alarm contact, as well as from the blocking signal receiver are controlled directly as well as by the fourth transistor switch, the first transistor switch When the blocking contact of the blocking signal receiver is closed, the second is conductive Transistor switch when the first transistor switch is conductive delayed conductive and is blocked with a delay when the first transistor switch is blocked, the third transistor switch with a conductive second transistor switch conductive with a delay and when the second transistor switch is blocked, the fourth transistor switch is blocked When the third transistor switch is conductive, it is conductive with a delay and when the third transistor switch is blocked The transistor switch is blocked with a delay and the fifth transistor switch is released is when either the blocking contact is closed or the fourth transistor switch is conductive.

An embodiment of the circuit of the locking device according to the invention is shown in the figure, the PNP transistors operated in a single circuit Ts1, Ts2, Ts3, Ts4 and Ts5 represent the five transistor switches, of which the Transistors Ts1, Ts2, T53, Ts4 for blocking and unblocking the groups of three G1, G2, G3, G4 are used and the transistor Ts5 is the contact for triggering the central alarm ZA represents. The locking contact K is from the locking signal receiver, not shown closed at the beginning of the lock and opened at the beginning of the unlock. The transistors T5t and Ts5 receive a base bias via the base resistors Rb1 and Rb5 in such a way that they become conductive as soon as the contact iL is closed and theirs Emitter are connected to positive potential. The emitter of the central alarm transistor Ts5 is also connected to the collector of the fourth transistor switch via a diode Dt Ts4 connected.

So when the transistor T54 is conductive, the Trans tor Ts5 conductive.

Via a voltage divider R1 / R2 a known per se and as First Miller integrator acting on a delay switch, consisting of an NPN transistor Tsml, a capacitor C1 and connected between its base and collector a collector resistor R3 controlled by the transistor T51 so that when conducting Transistor Tsl the transistor Tsm1 delayed conducting and with the transistor blocked Tel the transistor Tsml is also blocked with a delay.

via the series connection of a base series resistor Rb2 and a Zener diode D2 becomes the transistor switch T52 from the first Miller integrator in this way controlled that when the breakdown voltage of the Zener diode D2 and the threshold voltage the emitter-base line of the transistor Ts2 from that of the capacitor 3 of the Miller integrator voltage dropping is exceeded or undershot, the transistor TeZ is conductive or blocked.

The transistor Ts controls a second, consisting of the transistor Tsm2, the capacitor C2 and the collector resistor k6 Miller integrator, which in turn uses the series connection of a base pre-resistor Standes Rb3 and a Zener diode D3 controls the third transistor switch Ts3. This in turn controls a third one from the voltage divider R7 / R8 Transistor Tsm3, the capacitor C3 and the collector resistor R9 existing Miller integrator, which in turn via the series connection a base resistor Rb4 and a Zener diode D4 controls the fourth transistor switch Ts4. This one will also controlled directly by the locking signal receiver via the locking contact K1 The Zener diodes D2, D3 and D4 increase and control the response thresholds of the transistor switches Ts2, Ts3 and Ts4.

The mode of operation of the circuit is as follows: when the locking signal receiver evaluates a fault in the primary group and closes the blocking contact K, the Transistor T81 immediately conductive and the first group of three G1 blocked immediately.

The transistor Ts5 is also immediately conductive and the central alarm contact closed. At certain time intervals that are determined by the dimensioning of the Miller integrators are given, the transistor switches T5p, Ts3 and Ts4 then become conductive one after the other and the associated groups of three G2, G3 and G4 locked close to one another.

hen the blocking signal receiver ends the disturbance of the primary groups evaluates and the blocking contact K opens again, the transistor Tsi is blocked immediately and the first group of three Gl immediately unlocked. At certain time intervals that The transistor switches are given by the dimensioning of the Miller integrators Ts2, Ts3 and Ts4 blocked one after the other and the associated groups of three G2 and G4 unlocked. The central alarm transistor T55 remains conductive until also the fourth transistor switch Ts4 blocked and the last group of three G4 unblocked is.

Claims (6)

P a t e n t a n s p r ü c h e 1) Electronic group locking device for carrier frequency systems, the in the event of failure of one of twelve telephone channels caused by interference existing primary group divides this group into four groups of three for the duration of the disorder locks and unlocks against occupancy in such a way that within a certain period of time (of e.g. 1 sec) no more than three channels locked and unlocked at the same time are the beginning and end of a disturbance by a locking signal receiver through Closing or opening of a 5err contact indicated and from the beginning of the blocking Basically, a central alarm is given at the end of the unlocking via a central alarm contact is, characterized in that four transistor switches each assigned to a group of three (Ts1 to Ts4) are provided that the first transistor switch (Ts1) from the locking signal receiver directly, the second transistor switch (Ts2) via a first delay circuit from the first transistor switch (Ts1), the third transistor switch (Ts3) via a second delay circuit from the second transistor switch (Ts2), the fourth transistor switch (Ts4) via a third delay circuit from the third transistor switch (Ts3 ) and a five-port transistor switch (Ts5) which represents the central alarm contact, both from the locking signal receiver directly and from the fourth transistor switch (Ts4) are controlled, the first transistor switch (Tei) when the Blocking contact (K) of the blocking signal receiver is conductive, the second Transistor switch (Ts2) delayed when the first transistor switch (Ts1) is conductive conductive and when the first transistor switch (Ts1) is blocked, conductive and delayed when the first transistor switch (Ts1) is locked, the third is locked with a delay Transistor switch (T53) delayed when the second transistor switch (Ts2) is conductive conductive and blocked with a delay when the second transistor switch (Ts2) is blocked, the fourth transistor switch (Ts4) when the third transistor switch (Ts3) is conductive delayed conducting and delayed when the third transistor switch (Ts3) is blocked is blocked and the fifth transistor switch (Ts5) is conductive if either the blocking contact (K) is closed or the fourth transistor switch (Ts4) is conductive is, 2) Electronic group locking device according to claim 1, characterized in that then the f ;; nf transistor switches (Ts1 to Ts5) contain PNP transistors. 3) Electronic group locking device according to claims 1 and 2, thereby characterized in that the first and the fifth Trans gate switch (Ts1 and Ts5) over Base series resistors (Rb1 and Rb5) a base bias and across the blocking contact (K) Plus potential applied to their emitters in such a way that when they are closed they: Blocking contact become conductive. 4) Electronic group locking device according to claim 1 and 2, characterized characterized in that the delay circuits between the second, third and fourth transistor switches are designed as Miller integrators, each having an NPN transistor (Tsm1, Tsm2 and Tsm3), a capacitor (C1, C2 and C3) between its base and its collector and a collector resistor (R3, R6 and R9) contain, 5) Electronic group locking device according to claim 1, 2 and 4, characterized in that the base connections of the second, third and fourth transistor switch from the Miler integrators connected upstream the series connection of a base series resistor (Rb2, Rb3 and Rb4) and a Zener diode (D2, D3 and D4) base voltage obtained. 6) Electronic group locking device according to claim t, 2 and 3, characterized characterized in that the emitter of the fifth transistor switch (Ts5) by a Diode (3i) is connected to the collector of the fourth transistor switch (Ts4).