DE1957278B2 - Blocking system for carrier frequency systems - uses delay lines with RC circuits, emitter followers and Zener diode - Google Patents

Abstract

The blocking system, for carrier frequency systems blocks and unblocks a primary group consisting of twelve into four groups of three such that, within any given time, e.g. 1 sec., not more than three channels are blocked and unblocked simultaneously. To reduce the tolerance on the separate delay times of the delay circuit and to reduce their overall cost, these delay circuits are constructed as RC circuits (Rvl/Cl etc.) with npn emitter followere output stages (Tshl, Tsh2 etc.). A zener diode (D4) is used as threshold trigger in the common line to the emitter resistors (Rel etc.).

Description

The main patent relates to an electronic group lock / device for carrier frequency systems, one out of twelve in the event of a failure caused by interference Primary group consisting of telephone channels divides this group into four groups of three for the duration of the disturbance locks and unlocks against occupancy in such a way that within a certain period of time (e.g. from 1 see) no more than three channels can be locked and unlocked at the same time, with the beginning and the end a fault indicated by a blocking signal receiver by closing or opening a blocking contact and from the beginning of the locking to the end of the unlocking via a central alarm contact Central alarm is given, with four transistor switches each assigned to a group of three being provided and the first transistor switch from the locking signal receiver directly, the second transistor switch via a first delay circuit from the first transistor switch, the third transistor switch via a second delay circuit from the second transistor switch, the fourth transistor switch via a third delay circuit of the third transistor switch and a fifth transistor switch that the Central alarm contact represents, both from the locking signal receiver directly, as well as from the fourth transistor switch are controlled, and the first transistor switch when the locking contact of the locking signal receiver is closed is conductive, the second transistor switch is conductive with a delay when the first transistor switch is conductive and is blocked with a delay when the first transistor switch is blocked, the third transistor switch when it is conductive second transistor switch delayed conducting and delayed when the second transistor switch is blocked is blocked, the fourth transistor switch with conductive third transistor switch delayed conductive and with blocked third transistor switch is blocked with a delay and the fifth transistor switch is conductive, when either the blocking contact is closed or the fourth transistor switch is conductive.

According to claims 4 and 5 and the embodiment of the main patent application as delay circuits Miller integrators used each one npn transistor, one capacitor between its base and its collector and contain a collector resistor, the base terminals of the second, third and fourth transistor switch from the upstream Miller integrators each via the series connection of a basic pre-resistance

Stand and a Zender diode base voltage. The zener diodes act as threshold members and theirs Tolerances directly influence the delay times.

The object of the present invention is to reduce the effort and the tolerances of the individual delay times. As a solution, the delay circuits RC elements are used according to the invention, which are followed by emitter follower stages with npn transistors, a Zener diode being arranged as a swell member in the common lead to the emitter series resistors of the emitter follower stages.

The figure shows an embodiment of the arrangement according to the invention. The transistors TsI, Ts 2, Ts 3 and Ts 4 are the transistor switches that block the groups via the outputs Gl, G 2, G 3 and G 4. The transistor switch Ts 1 is made conductive by applying its emitter to - UB via the blocking contact K ; It then receives its base current from the operating voltage via a base resistor Rb. The delayed KC elements RvMCX, Rv2IC2, Rv3IC3 are connected to the collectors of the transistors TsI, Ts2, Ts3 via decoupling diodes Dl, Dl, D3 , which are only conductive when the associated transistors are conductive. When the transistors TsI, Ts 2 and Is3 are blocked, the diodes Dl, D2 and D3 are also blocked and prevent the /? C elements from being connected to the base connections of the emitter follower stages Tsh 1, Tsh 2 and Tsh 3 with the emitter series resistors Re 1, Re 2 and Re 3 lead to high blocking voltages. A Zener diode D 4, which acts as a threshold element diode, is located in the common supply line to the latter emulsion resistors.

The capacitors Cl, C2 and C3 are charged with a delay via the series resistors Rv I ₁ Rv2 and Rv3 and discharged with a delay via the emitter resistors R 1, R 2 and R 3 . The corresponding maximum charging voltages are

Rl

R] + RvI

R2 R2 + RvI

UB

UB

R 3

R 3 + Rv3

■ UB

and are significantly greater than the Zener voltage of the threshold element diode D4. The delay time for blocking is given by the charging time in which the voltages on the capacitors reach the breakdown voltage of the Zener diode D 4. The delay time for unlocking is given by the time in which the capacitors discharge from their maximum charging voltage to the breakdown voltage of the Zener diode D4. The desired delay times can be achieved by suitable selection of the voltage dividers RvX / Ri, Rv 2 / R 2 and Rv3 / R3 as well as the Zener diode D 4.

Since the maximum charging voltages of the capacitors are significantly smaller than the operating voltage UB , spatially smaller and therefore cheaper capacitors can be used.

Since the threshold element diode D 4 is common to all delay elements, this affects the tolerance of their breakdown voltage, all delay times and the delay times are equal less different.

1 sheet of drawings

Claims (5)

Patent claims: 1.Electronic group locking device for carrier frequency systems, which, in the event of a failure of a primary group consisting of twelve telephone channels, locks and unlocks this group in four groups of three against occupancy for the duration of the disturbance, in such a way that within a certain period of time (e.g. from 1 see) no more than three channels are blocked and unblocked at the same time, whereby the beginning and the end of a fault are indicated by a blocking signal receiver by closing or opening a blocking contact and a central alarm is given from the beginning of the blocking to the end of the unblocking via a central alarm contact, whereby four transistor switches each assigned to a group of three are provided, and the first transistor switch from the blocking signal receiver directly, the second transistor switch via a first delay circuit from the first transistor switch, the third transistor switch via a second delay circuit from the second Transistor switch, the fourth transistor switch via a third delay circuit from the third transistor switch and a fifth transistor switch, which represents the central alarm contact, are controlled both directly by the blocking signal receiver and by the fourth transistor switch and the first transistor switch is conductive when the blocking contact of the blocking signal receiver is closed, the second transistor switch at conductive first transistor switch is delayed conductive and blocked with a blocked first transistor switch, the third transistor switch is delayed conductive when the second transistor switch is conductive and blocked with a delay when a second transistor switch is blocked, the fourth transistor switch is delayed conductive when the third transistor switch is conductive and blocked with a delay when the third transistor switch is blocked and the fifth transistor switch is conductive when either the blocking contact is closed or the fourth transistor switch is lei tend is, according to patent 18 09 702, characterized in that the delay circuits /? C elements (RvMCX, Rv2 / C2, Rv3 / C3) are used, which are followed by emitter follower stages with npn transistors (7ΪΛ1, Tsh2, Tsh3) , a Zener diode (D4) being arranged as a threshold element in the common lead to the emitter series resistors (ReI, Re2, Re) of the emitter follower tubes. 2. Electronic group locking device according to claim 1, characterized in that the RC-CWe of series resistors (Rv 1, Rv2, Rv3), capacitors (C 1, C2, C3) and discharge resistors (R 1, R2, A3), the parallel connected to the capacitors exist. 3. Electronic group locking device according to claim 1 and 2, characterized in that the / fC elements are connected via decoupling diodes (D 1, D 2, D 3) to the collectors of the transistor switches (TsI, Ts2, Ts 3) , these diodes are only conductive if the associated transistor switches are also conductive. 4. Electronic group locking device according to An-SDruch 1 and 2, characterized in that the series resistors (RvI, Rv2, Rv3) and the discharge resistors (Al. Ä2, R3) of the ÄC members are chosen so that the maximum charging voltages of the capacitors ( Cl, C2, C3) are much greater than the breakdown voltage of the Zener diode (D 4). 5. Electronic group locking device according to claim 1, 2 and 4, characterized in that the The delay time for blocking is given by the charging time in which the capacitors (Cl, C2, C3) reach the breakdown voltage of the Zener diode (D4), and that the delay time for the Unlocking is given by the time in which the capacitors are from their maximum charging voltage have discharged to the breakdown voltage of the zener diode (D4).