DE2547303A1 - SEMICONDUCTOR COMPONENT - Google Patents

Description

TER MEER - MÜLLER - STEINMEISTER

D-8OOO Munich 22 D-48OO Bielefeld

-Triftstrasse 4 Siekerwall 7

S75P11 2 Oct 2, 1375

SONY CORPORATION Tokyo / Japan

Semiconductor component addendum to patent (patent application P 23 64 753.2)

The invention relates to a semiconductor component with two semiconductor areas adjoining one another via a first pn junction of different conductivity types, with one on the one first pn junction opposite side to the second area adjoining third area, with a fourth area from Conductivity type of the second region, which has a second Forms pn junction to the first area, as well as means that a bias of the first pn junction and the transport of Allow majority carriers from the first to the third area, whereby according to patent (patent application P 23 64 753.2)

holds that the diffusion length of the minority charge carriers im

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first area is greater than its strength.

It is known and common practice to manufacture bipolar transistors in a double diffusion process in which a Emitter-base transition is generated, for the overall rule that the doping concentration of the emitter is higher than in the base. If this difference becomes larger, the emitter efficiency also becomes higher and approaches it more and more Worth one. With a high level of doping, however, the lattice effects and dislocations in the semiconductor substrate also increase. As a result of the high doping, the diffusion length increases Minority carriers in the doped area. A humiliation however, the doping in the previously known transistors leads to a decrease in the degree of amplification.

In US-PS 2 8 22 310, among other things, a transistor is described, whose emitter has a high specific resistance, which means that the diffusion length is greater than its thickness or width and also a floating area is of the opposite conductivity type provided, which forms a pn junction to the emitter. The cited patent states that the number of minority charge carriers should remain below the equilibrium concentration both in the emitter and in the area kept floating and that both minority charge carriers should compensate each other via the pn junctions. It is also stated that the strength of the area kept floating should be greater than the diffusion length occurring therein, so that consequently the minority charge carrier current can be brought to a minimum in the emitter that the gradient of the minority charge carrier concentration is minimized in the floating area. And finally, the US-PS states that the pn junction is in the forward direction should be biased, otherwise the minority carrier current would increase in each of the areas.

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Furthermore, a transistor is described in the journal "Solid State Electronics", Volume 13 (1970), page 1025 where there is an additional area of the opposite conductivity type at a distance in the emitter, which lies within the diffusion length of the minority charge carriers in the emitter. The input signal is between the emitter and fed to the additional area while the base is kept floating.

However, with these known measures in the emitter area no significant improvement in the gain factor can be achieved with low noise parameters and stable operating conditions.

The invention is therefore based on the object of providing a semiconductor component, in particular to decisively improve a transistor with regard to a high gain factor. Simultaneously should improve the noise parameters, achieve a significantly higher breakdown voltage and a thermally induced Deviations in the characteristic values can be avoided. Another aim is to be able to incorporate such a semiconductor component in an integrated circuit together with conventional transistors, in particular also in connection with complementary transistor pairs.

In the case of a semiconductor component of the type mentioned at the outset, the invention is characterized according to the invention in that the minority charge carrier diffusion length in the fourth region mentioned is also greater than its strength or width. Other forms of embodiment of the inventive concept are characterized in further patent claims.

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The invention thus primarily relates to a bipolar transistor or a thyristor with an emitter region for which the minority charge carrier diffusion length Lp is greater than its strength and that there is an additional region immediately adjacent to the emitter region, for which the following applies that the minority carrier diffusion length Ln ^{1 is} greater than the strength of the additional area. The surface recombination velocity in the additional area is less than Dn '/ Ln'#, Dn ¹ denoting the minority charge carrier diffusion constant. Surface recombination is usually defined in terms of the rate of recombination, that is, the effective rate at which all minority charge carriers appear to be swept to the surface, where they are lost through surface trap levels or thermal accumulation.

The minority carrier diffusion length in the emitter is assumed to be on the order of 1 to 2 microns for conventional transistors. In contrast, the subject matter of the invention results in minority charge carrier diffusion lengths of 50 to 100 microns. The current amplification factor for conventional transistors is around 500, while current amplification factors (for example h _p for common emitter circuit) of 10,000 and more can easily be achieved for transistors according to the invention, with extremely low noise values.

The invention and advantageous details are explained below in exemplary embodiments with reference to the drawing. Show it;

Fig. 1 is a schematic partial sectional view of an npn transistor, at the features according to the invention are realized;

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2 shows a graphic model representation to illustrate the minority charge carrier concentration in the emitter area and in the additional area;

3 shows the schematic sectional illustration of an integrated circuit chip which has an npn transistor according to the invention Type and additionally contains a pnp transistor of conventional construction, with both transistors being a complementary one Pair up;

FIGS. 4, 5 and 6 are schematic sectional views similar to FIG. 1 other embodiments of semiconductor components with features according to the invention and

7 shows a circuit model to illustrate how a bias voltage and an input signal to the semiconductor device according to FIG. 1 can be applied.

Corresponding areas are identified in the figures with the same references.

The semiconductor component according to FIG. 1 consists essentially of a substrate heavily doped with n-type impurities or more specifically from a silicon substrate heavily doped with antimony. The doping concentration is preferably around

1 Q

4x10 atoms / cm ³ . This gives a resistivity of about 0.01 µm. It was determined that the doping can fluctuate so that values between 0.008 and 0.012 __Q.cm result. The thickness of the substrate is preferably 250 microns.

An n-type silicon epitaxial layer 2 is formed on the substrate 1, which together with the η substrate 1 serves as a collector. This epitaxial layer 2 is hereinafter referred to as the "third area" designated; it is doped relatively low with antimony, and

14 in a doping concentration of 7x10 atoms / cm ³ .

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The result is a specific resistance of about 8 to 10 Jicm. This epitaxial layer preferably has a thickness of 20 microns.

A p-type base region 3, which is hereinafter referred to as the “second region”, is then formed as an active base for the transistor by diffusion or ion implantation on the η layer 2. Boron can be used as the doping material, specifically in an amount that results in a doping concentration of 1 × 10 atoms / cm ³ .

The emitter forms an n-type silicon epitaxial layer 4, the is located above the η layer 2 and is referred to below as the "first region". Layer 4 is easy with Antimony doped, so that there is a doping concentration of

1 5
about 5.5 χ 10 atoms / cm ³ results. The specific resistance is around 1 JT.cm. The thickness of layer 4 is about 2 to 5 microns.

An η -type diffusion layer in the η -layer 4, which is hereinafter referred to as the “fifth region”, serves as the emitter contact region. This layer 5 is doped with phosphorus in a surface impurity concentration of 5 × 10 atoms / cm ³ ; it has a depth of about 1.0 microns.

The collector region is surrounded by a heavily doped diffusion region 6 which penetrates into the η collector layer 2. Phosphorus serves as the impurity material and the doping concentration is b <
area concentration.

1 9 concentration is around 3 χ 10 atoms / cm ³ as the upper

A p-type diffusion region 7 penetrates the n-emitter layer and extends as far as the ρ-base layer 3, so that the emitter 4 delimits and is framed. The dopant is boron and es

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19 results in a surface concentration of 7 10 atoms / cm ³ . A ρ-type diffusion area 8 is formed in the area 7 and serves as a base contact area. The diffusion region 8 is heavily doped with boron, specifically in an upper

1 row

surface concentration of about 5x10 atoms / cm ³ , the penetration depth of the area 8 being about 1.8 microns.

The top surface of the device is covered with a silicon dioxide layer 206 for passivation.

A collector electrode 9, in particular made of aluminum, is provided on the η substrate 1. A base electrode 10 made of aluminum is located on the base contact area 8. An emitter electrode 11 made of aluminum is provided on the emitter contact area 5.

A p-type area 200, sometimes hereinafter referred to as "additional Area "and sometimes referred to as" floating area "is diffused into the η emitter 4 so that a pn junction results between this region 200 and the emitter 4. The region 200 is doped with boron and becomes at the same time as the creation of the base contact area 3

1 8 generated. The doping concentration is 5x10 atoms / cm ³ , while the depth of the layer 200 is about 1.8 microns.

From the description given so far it can be seen that the n ~ layer 2 and the p region 3 have a collector-base junction 12 form. The p region 3 and the n ~ layer 4 form an emitter-base junction 13, while the n ~ layer 4 and the additional p-region 200 - as mentioned - form a further pn-junction 14. The distance between the emitter-base junction 13 and the additional pn junction 14 is preferably 2 to 5 microns.

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An emitter arrangement formed in a lightly doped epitaxial layer is disclosed in US Pat. No. 3,591,430 and in US Pat FR-PS 2 130 399 described.

3 illustrates a second embodiment of the invention, in which an npn transistor described with reference to FIG. 1 together with other semiconductor components, for example a pnp transistor, is part of an integrated circuit. This integrated circuit contains - like shown - two different transistor types, for example a complementary transistor pair, namely an npn transistor 21 and a pnp transistor 22. These two transistors are formed in a p-type silicon substrate 20. As already Explained with reference to FIG. 1, the npn transistor 21 contains a heavily doped collector region 1, a lightly doped one Collector region 2, a lightly doped base region 3, a lightly doped emitter region 4, a heavily doped one Emitter contact area 5, a collector supply area 6, a collector contact area 15, a base supply area 7, a base contact area 8, an additional area 200, a collector electrode 9, a base electrode 10 and one Emitter electrode 11.

The pnp transistor 22 has a p-type collector 33, a n-type base 34, a p-type emitter 38, a p-type collector lead region 37, a p-type collector contact area 48, an n-type base contact region 35, a collector electrode 39, a base electrode 40, and an emitter electrode 41.

The transistors 21 and 22 are electrically isolated from one another by pn junctions. A p-type isolation region 50 is included connected to p-substrate 20 and surrounds both npn and pnp transistors 21 and 22, respectively. Three n-type regions 31, 32 and 36 form a cup-like isolation region which surrounds only the pnp transistor 22. In making this so far

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In the integrated circuit described, a plurality of pairs or trios are produced at the same time, for example the n ⁺ regions 1 and 31 are produced by selective diffusion into the p substrate 20. The η regions 2 and 32 are generated by n-type epitaxial growth. The p ~ region 3 of the npn transistor 21 and the ρ region 33 of the pnp transistor 22 are produced either by epitaxial growth or by selective diffusion. The n ~ region 4 of the npn transistor 21 and the η region 34 of the pnp transistor 32 are produced by epitaxial growth. The η regions 6 and 36 are generated by n-type diffusion. The p-regions 7 and 37 are made by p-type diffusion. The ρ region 8 of the npn transistor 21, the additional region 200 of the transistor 21 and the ρ region 38 of the pnp transistor 22 are produced by p-type diffusion. The η regions 5, 15 and 35 are produced by diffusion.

Fig. 4 illustrates a third embodiment of the invention, in which an additional area 201 is connected to the base connection area 7 and the base 3. The base electrode 10 can be arranged on the additional area 201, limited to a relatively narrow area.

Fig. 5 shows a fourth embodiment of the invention, in which an MIS structure (metal isolation semiconductor arrangement) is provided on the surface of the lightly doped emitter 4. A gate electrode 42 made of aluminum and a silicon dioxide layer 41 together with the emitter 4 form the MIS arrangement. When applying a certain voltage to the Gate electrode 4 2, a barrier or boundary layer 202 occurs under the insulation layer 41. This is a reversal or Barrier layer, a depletion layer, or an enrichment layer.

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Fig. 6 illustrates a fifth embodiment of the invention, in which a Schottky barrier layer 203 on a surface of the lightly doped emitter 4 is formed. A suitable metal 51 is, for example, platinum on the η emitter 4 deposited to create the Schottky barrier layer.

Fig. 2 clarifies in a schematic graphic representation the minority carrier concentration in the emitter of the device according to FIG. 1. The upper part of the figure shows the Arrangement of the emitter 4 and the p-region 200. The graph shows the injected minority charge carrier concentration im Emitter or in the p-region 200. The due to the emitter-base junction 13 and the additional junction 14 in the Components emanating from the emitter 4 injected holes are illustrated by the gradient lines 101 and 102, respectively. The one from the additional The component caused by electron injection into the p-type region 14 is illustrated by the gradient line 103. The resulting gradient line 104 is essentially constant, that is to say shows a largely horizontal line Course, even if the gradient line 103 is essentially flat. This can be seen from a consideration of the equation

^I p2 ^{= X} p1 ^I n1

recognize where I ₂ denotes the hole re-injection from area 200 to emitter 4, I ₁ denotes the hole injection from emitter 4 to additional area 2 and I ₁ denotes electron injection from emitter 4 into additional area 200.

Since I. is very small, it can be neglected. This means that I 2 ⁼ I -t / from which it again follows that the curve profile 104 is essentially flat.

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In order to explain this in more detail, it should be noted / that the minority charge carriers (the holes) injected through the emitter-base junction 13 reach the additional junction 14 and penetrate into the additional area 200. The additional junction 14 is forward biased and the p-region 200 also injects holes into the n-type emitter 4. These holes pass the emitter and reach the emitter-base junction 13, since the strength or width of the emitter (W) is smaller than the diffusion length in the η -type emitter 4. The additional Holes injected into junction 14 decrease in number from junction 14 to junction 13. The one from the base-emitter junction injected holes also decrease from junction 13 to junction 14. The hole concentration over the emitter corresponds thus the sum of the minority carrier concentration gradient lines 101 and 102. Is the hole injection from the p-region 200 large enough, the sum of the gradient lines 101 and 102 results in an essentially constant charge carrier concentration via the emitter, which is illustrated in the graphic representation of FIG. 2 by the line 104. This lowers the hole current from base 3 to emitter 4.

The structure of a semiconductor component, in particular a transistor, explained above with reference to FIG. 1, results in very high h "characteristics with low noise. In order to explain this result further, it should be noted that the current gain factor for emitter circuit (h _FE ) is one of the essential parameters of a transistor. This value is generally given as

^h FE

1 - o (

where with ^. the current amplification factor for a basic circuit is designated. This current gain factor ^ C is again given to

0 (= oC * * ß * Y (2)

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where with o (* a collector multiplication ratio, with ß a base transport factor and γ denotes the emitter efficiency. For an npn transistor, for example the emitter efficiency given too

Jn 1
Y ⁼ Jn + Jp ⁼ 1 + Jp / Jn ⁽³⁾ /

where with Jn the electron current density due to the through the Emitter-base transition from the emitter to the base and injected electrons with Jp the hole current density of the holes injected in the reverse direction are designated at the same transition from the base to the emitter.

The electron current density Jn is given by

q · Dn · np cjv
^{Jn =} - ^ * (e ^kT -1)

Dp · Pn

^kT

Lp (e ^kT -1)

where with Ln the electron diffusion length in the p-type basis, with Lp the hole diffusion length in the n-type emitter, with Dn the Electron diffusion constant, with Dp the hole diffusion constant, with np the minority electron concentration in the p-type basis in equilibrium, with Pn the minority hole concentration in the n-type emitter in equilibrium, where ν is the voltage acting on the emitter-base transition, with T the temperature, with q the electron charge and with k the Boltzmann constant.

The charge carrier diffusion constants Dn and Dp are functions of the charge carrier mobility and the temperature and can therefore can be set as constant.

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With reference to the invention, the minority charge carrier diffusion length Ln ¹ in the additional area is selected to be greater than its strength or width Wp and, moreover, the surface recombination ^{velocity in the additional area is selected to be smaller than Dn '/ Ln 1} . ^{Dn 1} denotes the electron diffusion constant in the additional area. Ln ¹ depends on the impurity concentration and can be greater than 10 microns. In this case, the minority charge carrier current injected into the additional area is smaller than in the case where Wp is greater than Ln ¹ , since a multiplication with the term Wp / Ln ¹ takes place. Since the loss in the additional area is very small, the hole current injected into the emitter from the additional area corresponds to that injected from the emitter-base junction. The minority charge carrier concentration in the emitter is far above equilibrium.

For the subject matter of the invention, the expression Jp is supplemented as follows:

_{Jp =} . _{ ß _ _υ

The reduction of Jp therefore brings the value ** "after Equation (3) close to one; the value oi. is according to Equation (2) is very high and the same applies to the value of hp according to equation (1).

The low noise parameters can be explained as follows: The lattice effects or displacements decrease because the emitter-base junction 13 is formed by the lightly doped emitter 4 and the likewise lightly doped base 3. The impurity concentration in the lightly doped emitter 4 should be set to a value taking into account the noise characteristics, the lifetime X and the minority carrier diffusion length Lp

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1 Q

be limited, which is below or at most 10 atoms / cm ³ ■.

Another factor that causes a low noise level, it can be seen that the emitter current in the lightly doped emitter 4 and in the lightly doped base 3 is largely in Vertical direction flows.

According to this invention, an LH junction is formed by the lightly doped region 4 and the heavily doped region 5. The distance between the LH junction and the emitter-base junction is smaller than the minority carrier diffusion length Lp. The difference in impurity concentrations between the fifth and first ranges is chosen so that an energy barrier is created which is higher than the energy level of the injected minority charge carriers, which enter the first area from the second area and reach the LH junction. The LH junction therefore becomes creates a so-called "built-in field" which acts in such a direction that the hole current from the emitter-base junction 13 is reflected against this transition 13. Is that built in Field large enough so the diffusion flow of the holes is against the layer 5 effectively lowered.

Fig. 7 shows a schematic representation of an example of a circuit suitable for biasing and feeding an input signal into the transistor of FIG. The arrangement relates to the emitter circuit. Of course, a basic circuit can be implemented in a similar manner.

Although the invention has been described in particular in connection with FIG. 1 on the basis of an npn transistor, it is for the It will be apparent to those skilled in the art that pnp transistors with a similar structure and similar characteristic values can also be used in the same way.

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real let. It should also be emphasized that the invention can be applied well to semiconductor thyristors of the npnp type.

In summary, it can be stated that the invention creates a semiconductor component, in particular a transistor which is characterized by a high degree of emitter amplification with outstanding noise properties. This semiconductor device has an emitter region for which the minority charge carrier diffusion length is greater than his strength. For an additional area adjoining the emitter area, the minority charge carrier diffusion length applies is also greater than its strength. The surface recombination rate is for the additional Area very small. The minority carrier current injected into the emitter from the additional area is the same as that Current injected from the base into the emitter.

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Claims (8)

SONY CORPORATION S75P11 claims 1.j semiconductor component with two via a first pn junction adjoining semiconductor areas of different Conductivity type, with a side opposite the first pn junction to the second area adjoining third region, with a fourth region of the conductivity type of the second region having a second Forms pn junction to the first area, as well as means that a bias of the first pn junction and the transport of majority carriers from the first to the third area, whereby according to patent .... (patent application P 23 64 753.2), the diffusion length of the minority charge carriers in the first area is greater than its strength, characterized in that the minority carrier diffusion length is also in the fourth region is greater than its strength. 2. A semiconductor component according to claim 1, characterized in that the fourth area is marked with the second is connected. 3. Semiconductor component according to claim 1 or 2, characterized marked that the surface recombination velocity at the fourth region is less than D / L, where D is the minority carrier diffusion constant and L denotes the minority carrier diffusion length in the fourth region. 60981 9/0845 4. Semiconductor component, in particular according to one of the preceding claims, characterized by a first semiconductor region (4) of a first conductivity type, a second semiconductor region (3) of a second conductivity type, which together with the first Area forms a first pn junction, a third semiconductor area of the first conductivity type, which with the second area forms a second pn-junction, which is separated from the first pn-junction by the second area, a fourth semiconductor region of the second conductivity type, which has a third pn junction with the first region forms, which is separated from the first pn junction by the first region and by means of the first pn junction forward biasing to result in majority carrier transport from the first to the third area cause, it being the case that the minority charge carrier current injected by the third junction in the first region is essentially equal to the minority carrier current injected from the first junction and it is also true that the distance between the first and third transition is smaller than that Diffusion length of the minority charge carriers in the first area. 5. Semiconductor component, in particular according to one of the preceding Claims, characterized by a semiconductor substrate (1) with a main surface, a first semiconductor region of a first conductivity type in the main surface of the substrate and adjoining this, a second semiconductor region of a second conductivity type adjoining the first region, of which at least one section lies below the main surface, a third semiconductor region adjoining the second region of the first conductivity type, that of the first Area opposite side of the second area is arranged; Means to the transportation of majority carriers effect in the first to the third area, being a section 609819/0845 2b47303 of the second area is at least partially between the said main surface and the first region and wherein it applies that the minority charge carrier diffusion length in the first area is greater than its strength. 6. Semiconductor component according to claim 5, characterized in that that the minority carrier diffusion length is greater in the portion of the second region than whose strength is. 7. Semiconductor component according to claim 6, characterized in that that the surface recombination velocity is smaller in the portion of the second region is as D / L, where D is the minority carrier constant and L is the minority carrier diffusion length in this section. 8. Semiconductor component, in particular according to one of the preceding Claims, characterized by a first semiconductor region (4) of a first conductivity type, a second semiconductor region of a second conductivity type which, together with the first region a first pn junction forms, a third semiconductor region of the first conductivity type, which with the second Area forms a second pn junction, which is separated from the first pn junction by the second area, a Device for supplying a voltage which causes a majority charge carrier transport in the first to the third area causes, it being the case that the thickness of the first region is smaller than the diffusion length of those occurring therein Minority charge carrier, and by a control electrode arrangement formed by and on the first region. 60981 9/0845 2b47303 Semiconductor component, in particular according to one of the preceding claims, characterized by a first semiconductor region (4) of a first conductivity type, a second semiconductor region (3) of a second Conductivity type, which is one with the first area pn-junction forms, a third semiconductor region of the first Lextbarkeittyp, which with the second region a forms the second pn junction, which is separated from the first pn junction by the second region, a device for feeding a voltage to effect the transport of majority charge carriers in the first to the third area, where it applies that the strength of the first region is smaller than the diffusion length of the minority charge carriers occurring therein and wherein the first region is adjoined by a Schottky barrier layer. 609819/0845