DE2539026A1 - FIELD EFFECT TRANSISTOR - Google Patents

Description

PATENT LAWYERS F.W. HEMMERICH GERD MÖLLER D. GROSSE F. POL I MEIER September 1, 1975 g.ke 72 355

TOKYO SHIBAURA ELECTRIC COMPANY LIMITED,

72 Horikawa-cho, Saiwai-ku / Kawasaki-shi, Kanagawa-ken, Japan

Field effect transistor

The invention relates to a junction field effect transistor with a base body of a semiconductor material of one conductivity type with a drainage area and a source area of the same conductivity type and a gate area of the alternative conductivity type. Such field effect transistors, hereinafter referred to as FET for short, draw are characterized by the fact that they practically do not take up any current at the control electrode. Recently, junction FETs are the Vertical design developed that have such a triode behavior. They get special attention because they as elements for controlling or regulating relatively large electrical Benefits can be used. A disadvantage of conventional designs is that the resistance the control electrode itself is undesirably large, and the control capacitance turns out to be high, so that the the resulting time constant becomes large and the running times are relatively long, so that the upper limit frequency, up to which such FET can be used is undesirably low.

The invention is based on the object of creating an FET whose capacities, in particular those of the control or gate electrode to the source electrode, and the transit times are short, and its control electrode has a low resistance so that the FET can be used up to high frequencies. Another object of the invention is to provide a structure which ensures relatively narrow tolerances of the characteristic values of the FET.

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PATENT LAWYERS F.W. HEMMERICH GERD MÖLLER D. GROSSE F. POLLMEiEHt

This object is achieved by a generically designed FET according to the invention, the source area as well the gate area has arranged on a main surface of the body, and in the source area a plurality of individual ones Has districts that are enclosed by closed meshes that are formed by areas of the goal area are that they are directly adjacent to these. In this way, relatively narrow, effective channels are achieved, and If there is no direct overlap of the electrodes at a short distance, their capacitance is considerably reduced.

The goal area is useful as a closed mesh Lattice formed, which extends over the length of each mesh from the main surface of the body in this extends, the source districts each extending into a mesh from the main surface of the body.

Favorable characteristics of the FET are achieved when the gate areas extend deeper into them from the surface of the body extend as the source districts. However, it is also possible to make the arrangement so that the gate areas extend from the surface of the body essentially as deep into it as the source regions.

The resistance of the gate electrode can be effectively reduced if the provided along the circumference of the network Areas extend deeper into the body than the remaining, preferably inner areas.

A particularly favorable design results when the drainage area is arranged to the side of the goal area in the body and extends into it from its main surface.

The body advantageously consists on its side adjoining the main surface of semiconductor material with lower conductivity

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PATENT LAWYERS F.W. HEMMERICH GERD MÖLLER D. GROSSE F. POLLMEIER

ability to do so on its side facing away from the "main surface." has a layer of higher conductivity; the drainage area extends from the main surface through the Layer of low conductivity up to the layer of higher conductivity in contact with it.

Versatile use and simple assembly results when the connection electrodes of the drain, gate and the source area are arranged on the same main surface of the body.

The features of the invention are described below with reference to exemplary embodiments and these explanatory drawings written. It shows here:

a section through a vertical version of a FET,

different field images of a channel of the FET of FIG. 1,

Current characteristics of the FET of Fig. 1,

schematic phases of the production of an FET designed according to the invention,

5 current characteristics of the FET according to FIGS. 4,

Figs. 6 to 8 explain manufacturing phases of three further exemplary embodiments of the FET,

Figs. 9 and 10 manufacturing phases of another FET,

FIGS. 11 to 13 show the production phases of the 6th to 8th exemplary embodiment.

Fig. 1 shows the laterally broken, enlarged section through a known multi-channel FET, which is used for integrated

Fig. 1 Figs. 2 Fig. 3 Figs. 4th

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Circuits or integrated circuits is very useful. The body 1 of this field effect transistor FET is made for example from an N -conductive region with an N -conductive layer arranged underneath. In the upper one

_ 4.

In the area of this N -conductive region, several P -conductive control electrode regions 3 are incorporated as a network connected to one another. A shallow N -type emitter area h is machined in such a way that it is located over most of the control electrode areas. A plurality of channel regions are present in the high resistance N region and are arranged between the various control electrode regions 3 in such a way that the current flowing through the channel regions between the emitter and collector is controlled and regulated. D is a collector terminal which is led out 5 from a collector electrode 5. The collector electrode 5 is formed by vacuum evaporation of aluminum or the like on the bottom surface of the body 1, G and S are respectively a control electrode terminal and an emitter electrode terminal which are led out from a control electrode 6 and an emitter electrode 7 which are produced at the same time.

A vertical field effect transistor FET of the aforementioned Construction is designed in such a way that as far as possible use is made of the advantages of the bipolar Switching element and the electrical field effect transistor. In the same vertical field effect transistor FET, there is an epitaxial structure in which the control electrode regions are embedded in the interior of the transistor body by using the gas phase wax process.

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By the method described below, the aforementioned field effect transistor FET has the vertical type a double diffusion structure, so that the process of its manufacture is greatly simplified.

This means that the body 1 of the transistor, which consists of an N ~ -conducting region and the N -conducting layer, which then becomes the collector zone, is produced. An oxide film is placed on the upper surface of the N ~ -conducting area and a photoresist layer is placed on this layer, which is selectively etched, with holes being machined into the oxide layer to produce the control electrode areas. A template in the form of a round or square network is used, the network covering the parts in which the emitter areas are to be incorporated. The width of the mesh that forms the control electrode zones is approximately 5 microns. From here, for example, boron is introduced as a P-type impurity into the N-type area. After the production of these P-conductive control electrode areas, these control electrode areas are covered with an oxide layer, whereupon a large window covering the entire control electrode areas is worked into the oxide film. Through this window, an N-type impurity, for example phosphorus or the like, is flatly diffused in a high concentration, an N-type emitter region k being produced in such a way that from it, such as. This can be seen from Fig.l, essentially all control electrode areas is covered.

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The PN junction areas are in this field effect transistor not exposed on the surface of the body, and the barrier capacitance is less than at. the previously known AUstiWBHVngon von Feldeffökttfaneistoren FET, in addition, the dielectric strength is improved because the gate or control electrode zones and Emitter zones consist of N-P transitions, shows the flowing between gate or control electrode and emitter Current triode behavior, also the characteristic of the saturation current, that flows through the channel areas is improved.

FIG. 2 now shows the states of a barrier layer in a channel region. This is intended to illustrate the working principle of a field effect transistor of the vertical design. 2a shows the state of the depletion barrier layer in the vicinity of the control electrode or gate zones in the event that no negative control voltage V is applied to the control electrode. If no negative control voltage is applied, this depletion barrier layer is generated by the internal electric field that is present at the PN junction between gate / control electrode and emitter Channel area a collector current Ι «to flow ,, The V_-I _{n characteristic} curves are shown with Fig.3. However, if a negative control voltage is then applied to the gate or the control electrode, as shown in FIG the gate / control electrode areas, so that the collector current I _{n is} less +

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can flow easily. The V-L characteristics change in the manner shown in FIG. 3 and in a form which increases the resistance of the channel. If an even greater negative control voltage is applied, as shown in FIG. 2c, then "the depletion barrier layer from the gate / control electrode areas constricts the channel area". However, this means that even when the collector voltage V has been applied, the channel is blocked by the depletion junction and a collector current I_ does not flow. If, of course, a higher collector voltage V is applied, the depletion barrier layer collapses and the current can be made to flow ”,“ 2d now shows the state of the depletion barrier layer immediately before this depletion barrier layer collapses. The collector voltage V causes conversion to occur on the collector region side. Thus, if, as can be seen from FIG. 3, the control voltage V becomes even more negative, the collector voltage V _n , which is necessary for the onset of the flow of the collector current L., is greater, and approximately the properties and are possible to achieve the behavior of a triode.

If a vertical field effect transistor FET, which has these properties and exhibits this behavior, is now considered, it can be seen from FIG N layer as the emitter region h under the emitter electrode or the emitter terminal 7. The gate / control electrode regions 3 are thus continuously in

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Mesh shape and connected to each other in a plane, over the gate / control electrode areas where a gate electrode 6 is not provided, they are covered by the aforementioned N-layer so that they are not exposed on the surface of the main body 1 ₀ For this reason near the surface the gate / control electrode areas are kept in a form in which they are separated by the (second) diffusion of an N -layer, but with this the ^ Gatt-Z control electrode series resistance r becomes large. The expansion of the depletion barrier

the canals cannot easily be constricted in the canal areas. In addition, the junction layer of the gate regions 3 and the emitter regions 4 is formed so as to extend over the entire upper surface of the gate / control electrode regions 3, and the junction capacitance CL, c becomes large. For this reason, the time constant CL also becomes ₁₀ . r_ large, so that the collector current I ^ is not controlled and regulated during high-frequency operation? can.

This invention takes the above points into account so that a vertical junction field effect transistor or a vertical junction semiconductor device which works satisfactorily and excels in high frequency characteristics having.

The exemplary embodiments of this invention, which essentially relate to an N-channel field effect transistor FET, are illustrated and described below with reference to the drawing. According to Fig. H , the body of the semiconductor device is first of all, this has a layer structure consisting of an N -diffusion layer 11 and an N-region 12, as is used for the production of a transistor of the triple diffusion _. Execution is used, prepared and manufactured. The same structure is achieved by placing an N * "layer drawn in the gas phase as a layer on the surface of a heavily seeded underlayer. Then a boron-doped SiO glass layer Ik. F, hereinafter also BSG -Layer

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is called) is placed on the upper surface of the N-area, namely by drawing in the low-temperature gas phase, which contains the boron oxide. Using the photo-etching process, the part of the BSG layer 14 in which the gate / control electrode areas 13 are produced by diffusion is used are to be formed by removing excess parts by etching with a fluorate. In this case, the BSG layer is used as a diffusion impurity source by performing diffusion of boron. If, in this case, photo-etching is used during the subsequent diffusion and production of the emitter region 15, so that selective diffusion is carried out, this results in a reduction in the output, as can be seen in the previously known technology. For this reason, the boron diffusion is carried out in a weak oxidizing atmosphere in such a way that the silicon oxide layer 16 is formed by the heat treatment of the Gatt diffusion on the surface of the area in which the emitter is to be produced and in such a way that the layer 16 is not becomes too fat. To produce the BSG layer 14, the temperature of the semiconductor body is kept at 450 ^ as a condition, the heat treatment being carried out for a period of 5 minutes in a mixed gas atmosphere in such a way that the flow rate of nitrogen gas is 35 liters / min, the flow rate of diborane gas with a concentration of 50 ppm 0.5 liters / min, and the flow rate of oxygen gas 0.3 liter / min _e In this case, the BSG layer 300 p thick, while on the surface of 'a 3000 a thick layer of pure silicon dioxide under the aforementioned conditions, but with the diburan gas stopped. The diffusion of the Gatt area takes place under the conditions of a heat treatment of 40 hours at a temperature of 1030 ° C. in a mixed gas atmosphere in which the flow rate of the oxygen gas is 0.1 liters / min. and the flow rate of nitrogen gas is 3 liters / min. By means of this heat treatment, a gate / control electrode area 13 with a surface concentration of 3 × 10 ^

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and a transition depth of 2.6 / U is achieved. Under these In some circumstances, the silicon dioxide layer 16 grown on the surface of the N ~ layer becomes 300 Å thick. Under Applying the fluorate etching liquid will only remove this silicon dioxide layer etched and removed while the remaining BSG layer acts as a makse or stencil when carrying out the selective diffusion of the emitter layer 15 is used. During this diffusion process the technique used to make the emitter layer of planar transistors was used This means, however, that the heat treatment was carried out under the conditions listed below carried out: temperature 1000 C, dwell time in a phosphorus-containing oxychloride vapor with a vapor pressure of 0 and in a mixed gas atmosphere of oxygen gas and nitrogen gas. At the same time it became extremely thin Layer of phosphor glass is made on the surface of the emitter region 15, whereby the impurity concentration a value in the surface of the emitter area

2O * ■ $
of 10 atoms / cm, and the diffusion depth would be 1 / U. However, so that it can act uniformly over the entire emitter area and its area, a resistor part 17 for low resistance is arranged in one of the parts. This part is produced with a comparatively large width, and part of the BSG layer I ^ of this part is etched away in the photo-etching process. In the Gatt area where such removal by etching has taken place

Boron so diffused that by using a commonly used method, the additional and very strong boron doped layer 17 'is formed around said target reduction meet to be able to, and to ensure that the contact resistance with the electrode metal layer 18 _f which is formed later, will be a non-rectifying contact, this diffusion layer should have a surface concentration of not less than 10 atoms / cm3. This layer can be very flat. To achieve the same purpose, the heavily doped additional layer 17 can be produced in advance, ie before the gate areas 13 are produced and before the gate and emitter areas are diffused in. The glass layers drawn in the heat treatment to form the heavily doped additional layer 17, but also the emitter area 15, are then removed by applying the fluorate etching liquid, whereupon the Gatt electrode 18 and the emitter electrode 19 are applied to the corresponding surfaces will. The collector electrode is ^{filled out of the N +} layer 11
transistor is complete »

N ⁺ layer 11 led out and the vertical Fekdeffekt-

The vertical field effect transistor FET is made of the N layer 11, which occupies the largest part of the collector area ^ </ ie gate areas in P design, ie the gate areas 13, and the emitter areas 15 in N design and the N ~ area 12, in which the channel areas are incorporated in the vicinity of these contact parts. If, for example, the specific resistance of the N ~~ area is 30 ohm cm, it has a thickness of 20 / u.jj, the emitters and gate areas are manufactured using the above-described processes in such a way that the area - ■ '.. ··.

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of an emitter region 6 χ 50 / u and the total emitter

p /

range is 0.26 mm, then the static Voltage-z ^ current characteristics of the semiconductor device with Fig. 5 "reproduced characteristic curves, moreover a typical »triode behavior achieved ·

The vertical field effect transistor produced in the aforementioned FET is better in its characteristics than that using known methods such as this is shown with Fig. 1. The structure is such that the emitter areas are directly surrounded from the gate areas, so that the PN junctions between the emitterbexen and the gate areas are only at the edges of the regions 15 is present, which in turn has the consequence that the capacitance at these PN junctions is small. Also the upper parts of the genre areas that have been left have a relatively high concentration and are not limited for the purpose of making the emitter regions, as is the case with FIG. 1. From this Basically, the specific resistance of the Gatt can also be small

being held. Because the aforementioned capacity C__ ^! GS

is small and because the series resistance r_ of the gate area is small, shows this vertical field effect transistor a very pronounced high frequency behavior, also in the manufacture of the main body for the field effect transistor FET only needs to produce the mask or stencil for the photo-etching process once, i.e. if the ESR layer is selectively removed, with the remaining part of the ESR layer after removal as a mask or stencil for the production of the emitter areas is used. For this reason, there can be no error in the manufacture of the mask or stencil are made »The parts of the emitter and gate areas,

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which overlap each other are extremely small, and the attenuation in the dielectric strength is also very small. This enables FET,

J- *

which have several channels, a uniform operating behavior be delivered. They also apply durofe Mask or stencil defects and photo-etching practically no defects introduced, so that the percentage of usable semiconductor devices manufactured is very big. The mass production of this semiconductor has also been improved.

A second embodiment of this invention will now be illustrated and described below with reference to FIG. In this exemplary embodiment, the gate regions and the emitter regions are produced separately from one another from doped oxide. For this reason, the description relates to an N-channel field effect transistor FET. First of all, the body is made from a layer structure - this consists of an N diffusion layer 21 and an N layer 22. Using the method described in connection with FIG. H , the gate regions Zh are formed by diffusion from the BSG layer, whereupon the silicon dioxide layer on the surface of the N ~ layer 22 between the BSG layers 23 is then applied using a fluorate etching liquid is removed when the gate is diffused in. Then a layer 25 of silicon dioxide, to which phosphorus atoms have been added - this layer is produced by drawing in a low-temperature _{gas phase, (phosphorus-doped SiO 2} GIaS, which will be referred to as PSG in the further course of this patent application), over the entire surface of the N "" -Area arranged, included therein

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also the surfaces of the BSG layers 23. This PSG layer

25 is etched away so that only the parts that are required for the production of the emitter regions 26 remain. These are, for example, the parts between the gate regions Zh Diffusion of the phosphor atoms carried out, whereby the emitter regions 26 are produced. As far as diffusion is concerned at this point in time, the heat treatment is carried out in a weakly oxidizing atmosphere. After the diffusion process has been carried out, an oxidation process can also be carried out. The parts of the transitions of the gate areas 2h which are exposed on the surface are produced and protected by a new silicon oxide layer 27. On the emitter areas

26, an emitter electrode is attached, specifically in the sections in which the PSG layers 25 have been removed by the etching liquid. In a similar manner, a gate electrode 29 is applied to the parts of the gate areas 2h where the PSG layer 25 and the BSG layer 23 have been removed by processing with the etching liquid. A collector electrode is led out of the N layer 21, whereupon the vertical field effect transistor FET with triode behavior is finished.

In this way it is possible to produce the gate and emitter areas using the BSG and PSG layers. P-channel field effect transistors can also can be made in a similar manner using glass mixtures. The field effect transistor according to Fig. 6 (c) has essentially the same structure as that of Fig. 4c and therefore also provides the same performance *

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A third embodiment of the subject matter of the invention will be illustrated and described below with reference to FIG. 7. In this exemplary embodiment, the emitter regions are implemented with approximately the same depth as is the case with the gate regions. An N-channel field effect transistor FET is thus described. First, the base of the semiconductor device - this consists of a layered construction with an N diffusion layer 31 and an N ~ "region 32, is produced and prepared Pellets of a planar transistor is the case. This means that a silicon dioxide layer 33 is to be produced on the surface of the body by heat oxidation Boron is diffused into the section where the silicon dioxide layer has been removed, which in turn leads to the production of a P diffusion layer 3k . that the P diffusion layer Jk and the emitt areas that will be produced in a later process can be added. Boron is diffused into the aforementioned hole, a P diffusion layer 35 being formed. Of course, the oxidation on the surface of this diffusion layer 35 is ensured during the diffusion process, with a new silicon dioxide

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layer 36 is created. By photo-etching, holes are then worked into a part of this silicon dioxide layer 36 * above dej * areas; / in which the emitter areas arise, whereupon a selective diffusion of phosphorus atoms takes place until the N ~ layer reaches 32 and in this way the N emitter areas have been created. Simultaneously with this diffusion process, a new silicon dioxide layer 38 is created. Now, in the photo-etching process, holes are machined into the part of the silicon dioxide film 38 that lies over the emitter regions 37, as well as in the part of the silicon dioxide layer 36 over the P diffusion layer 3k An emitter electrode 39 and a Gatt electrode k0 are inserted in each case, while a collector electrode is led out of the N ⁺ layer 31. However, this completes the vertical field effect transistor.

As already described above, the group of the emitter regions 37 is surrounded by the gate region 351 , the depth of the diffused emitter regions 37 being approximately equal to the depth of the gate region 35, which in turn means that a triode behavior can be achieved »For the semiconductor device With this construction, however, the following points must be observed: First of all, the impurity concentration of the gate area and the impurity concentration of the emitter area must have a low value. The reason for this is that if these areas receive too much impurity concentration, it is likely to be the cause of a decrease in the dielectric strength in the gate area, resulting in a narrow working area. Even if

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If the difference in concentration between the gate area and the emitter areas is too great, problems can arise. The reason for this is that if the gate area has been given an extremely low concentration in order to make the dielectric strength of the gate area as large as possible, the depletion barrier layer cannot spread on the sides due to the gate control voltage and can therefore not enter the channel areas convert a depletion barrier. Even if the width of the emitter region is made large in the field effect transistor FET according to FIG. Jc, the width of the channel regions immediately below is also widened, and there is a risk that the depletion layers could not be able to function during operation to constrict the channels, which in turn would impair the operation of the field effect transistor FET _or the dielectric strength of the gate area, the gate area is produced with the lowest possible concentration, which is why an increase in the gate series resistance to a certain extent is unavoidable “This increase in Gatt series resistance creates difficulties and problems with regard to high frequency operation. For correction, however, a P-area can be provided in a continuous part of the gate area 35, which consists of a P-area when viewed in plan view "

A field effect transistor, which, taking into account the aforementioned Points is made, has excellent high frequency properties, because it is designed so that the emitter areas are directly surrounded by the gate areas ;,

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and, moreover, can be manufactured using simple processes.

The gate areas and the emitter areas in this Avis guide example were not made using the diffusion method. You can, for example, be produced according to the doped Oxydmet, / ι ode, as is the case with the first and second exemplary embodiments.

A fourth exemplary embodiment of the invention will now be illustrated and described below with reference to FIG. 8. In this exemplary embodiment, the gate regions and the emitter regions are produced simultaneously using doped oxide. The description below relates to an N-channel field effect transistor FET. First, the body of the semiconductor device is manufactured. This body consists as a layer construction of an N diffusion layer 51 and an N ~ region 52. A BSG layer 53 is drawn over the entire upper surface of the body using the low-temperature gas phase method. The BSG layer is processed by photo-etching in such a way that parts of this layer remain as sources of diffusion, while the remaining part of this BSG layer is chemically removed by etching. Then a silicon dioxide layer 5 ^> containing arsenic acid, arsenic-doped SiOp glass, which will be referred to as AsSG in the further course of the patent application, is produced over the entire area of the surface of the body. By photo-etching, this AsSG layer 5h is removed again, except for parts that serve as diffusion sources, by using chemical etching agents. Will now be the

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subject at appropriate temperatures to heat treatment, then you can, because of the differences in the sizes of the diffusion coefficient of arsenic and boron atoms, d ^ e Gattbereiche required 55 and emitter regions 56 in the N * "- range are produced simultaneously _e At the same time created on the upper surface of the semiconductor device a silicon dioxide layer 57 »which has to protect and stabilize the PN junctions at the periphery of the gate areas. In this process, the oxidation can take place during the aforementioned heat treatment of the heat treatment process for the production of the silicon dioxide layer 57 is created «Even if the aforementioned BSG layer and the aforementioned AsSG layer are produced as diffusion contamination sources in the low-temperature gas phase drawing process, when the entire surface is coated with a very pure silicon dioxide layer If the diffusion heat treatment is carried out in such a way that a very dense concentration is generated during this operation, if this diffusion is also carried out in a weakly oxidizing atmosphere, then a heat-oxidized film is generated between the surface of the N-layer 52 and the very pure silicon dioxide layer, which ultimately leads to stabilized PN junctions being produced.

The advantages are that in the construction or structure described above, the emitter regions are directly surrounded by the generic areas that from this

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Basically, the high-frequency behavior is excellent. The advantages lie in the fact that the emitter areas and the gate areas are produced in a single heat treatment process, that the crystal defects that are introduced by the heat treatment are halved because, in addition, the emitter and gate areas are cut in half Generic areas can be reliably produced by precisely controlling only the impurity atoms in the BSG layer and in the AsSG layer.

Inferior to a method of achieving and establishing is now the aforementioned construction or structure shown and described ,, The conditions for the application of the BSG layer 53 can be the that were added in the case of the embodiment of Figure 4 _o "For the application of the AsSG -Layer 54, the following conditions apply: - If the base plate has a temperature of 450 C if the flow of silane gas with a concentration of 3 ^ 0.7 liters / min, if arsenine (AsH ") with a concentration of 1000 ppm flows through in an amount of 0 _or 8 liters / min, when the oxygen flow is 2.5 liters / min, and the nitrogen flow is 35 liters / min, and the whole is carefully stirred when drawing in the gas phase is carried out during a period of 5 minutes, then a AsSG layer can be formed with a thickness of about 3000 a "Now, the AsSG layer while leaving residues for the formation of the emitter regions 56 in the diffuse The diffusion sources created in this way, for example the BSG layer 53, are masked by the AsSG layer for this reason

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the BSG layers are used as sources for the diffusion of boron atoms in a direct downward direction, the P-gate regions 55 being produced by diffusion and the AsSG layer 5 ^ being covered by the BSG layer 53, with the N emitter areas 56 arise from the diffusion of arsenic atoms. If glass diffusion sources are used and the entire base plate is subjected to a heat treatment at a temperature of 1050 ° C. for a period of 80 hours, then the diffusion parameters for Gatt and emitter areas are a diffusion depth of h / n and 1.5 / U as well as a diffusion surface concentration of 3 x 10 atoms / cm and 1 χ 10 atoms / cm “This heat treatment is of course carried out in a weakly oxidizing atmosphere, with the silicon parts on the surface of the PN junction and on the The periphery of the gate areas are oxidized and a silicon dioxide layer is produced to protect and stabilize the surface An emitter electrode 59 and a gate electrode 59 are led out from the corresponding emitter regions 56 and the corresponding gate regions 55, while the collector electrode is led out from the N layer 51 », whereupon the vertical field effect transistor FET is finished.

In the previously beschriebnen four embodiments, additional operations can be carried out, as they can be used for the below listed embodiments _e can be formed in one area and an order of / not departing from the spirit of this invention.

A fifth exemplary embodiment will now be described below

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based on Fig. 9 and Fig. IO are shown and described. In general, it is necessary that the voltage amplification factor / U of field effect transistors FET can be freely controlled. This is the major Eigensdiaft of these field effect transistors FET "In the known methods for controlling the concentration of the impurity diffused d _o h _o the Störstellenkonzentrationkontrolle is moved generally in such a manner that impurities or oxides are vaporized and removed from the gas phase, so then an exact control of the diffused impurity concentrations is also not possible. On the other hand, / U is strongly influenced by the definition of the dimensions of the gate areas and emitter areas as well as by the specific resistance of the channel areas, which made free control and regulation of the factor / U impossible is reveals an emitter region _o can be seen that it is an N-type collector region B3I the region 61, numeral reference 62 stands for the P-leitendeh Gattbereich, numeral reference 63 -type for the N emitter region and the note number 6k for the Canal area. In general, this channel region 6h has the same specific resistance as the collector region 6l, so that when a voltage in the reverse direction is applied between the emitter electrode 65 and the gate electrode 66 , the resistance of the channel region in the vertical direction is through the ! the depletion barrier spreading out from the PN junctions becomes gradually larger. This voltage dependency is physically determined by

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the specific resistance of the channel region 6k, it has been established that if the emitter region is to be diffused in, it is possible to simultaneously use two or more impurities with different diffusion coefficients to change the specific resistance in the channel region 6k and to control the factor , u to diffuse.

As is apparent from Fig. 10, the semiconductor device body which is manufactured has a layer structure composed of an N -diffusion layer 71 and an N- layer 72. On the upper surface of the N- layer 72, a BSG -Layer 73 is applied and, apart from the places that are to form the Gatt areas, removed again in the photo-etching process and removed. Then a mixed glass layer 7 ^ i containing boron and arsenic is applied to the entire surface of the body and except for the Parts that have to form the emitter areas are removed again in the photo-etching process. Now that the diffusion sources for the production of the selective emitter and Gatt diffusion are in this way, the heat treatment is carried out. The boron atoms are removed from the BSG layer 73 directly downwards diffused onto the Gatt areas, the layer 7 ^ acting like a mask or a stencil.On the other hand, the boratons and the arsenic atoms are selectively from the Mi schglas layers 7k diffused onto the emitter areas. In this case, the BSG layer is used as a mask or stencil. The boron atoms of the gate areas are introduced to stabilize the gate areas 75, the arsenic atoms of the emitter areas to stabilize the

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Emittöribereiche 76 "and the boron atoms and the arsenic atoms from the same glass layer 7 ^ diffused warden to the resistivity of the Kanalbereiolxe 77 ^only ^ ⁰ - to change this part" (Reference is made to Figure "96) referenced"

The important factor is now the ratio between the Si site concentration of the boron atoms which have been diffused in simultaneously with the arsenic atoms from the same glass layer 7h , and the concentration of the donor atoms in the initially used N layer 72 mentioned concentration is greater, then extremely narrow P-layers are introduced into the channel regions 77 under the emitter regions 76 , if the first-mentioned concentration becomes smaller, then + one obtains a high specific resistance in the channel regions _o are the first-mentioned concentration and the last-mentioned concentration If the same - (to be precise, if the impurity atoms are the same in the whole N - layer, if these boron atoms have been introduced into the body by diffusion, then the concentration distribution is an error function, so that an even distribution of the concentration throughout the canal area calibration cannot take place), then the parts under the emitter areas J6 become intrinsic layers.

An experimental example is now described: Under the conditions given for the production of the BSG layer 73 if the body is heated to 450 ° C, the is Flow of diburan gas with a concentration of

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50 ppm 0.5 liters / min., The flow of silane gas with a concentration of 3 % 0.7 liters / min., The flow of oxygen 0.3 liters / min and in this mixed gas atmosphere the flow of nitrogen 35 liters / min. In this mixed gas atmosphere, the heat treatment is carried out for a period of 5 minutes, whereby a BSG layer 73 with a thickness of approximately 3000 S. is produced. If the conditions for the production of the mixed glass layer74 are met, then the body is heated up to ^ 50 C, and this with a flow rate of diborane gas with a concentration of 10ppm of 0.5 liters / min, with a flow rate of arsine -Gas (AsH.,), Which has a concentration of 100 ppm, of 0.8 liters / min., With a flow rate of oxygen gas of 2.5 liters / min ₀ , with a silane gas amount, this silane gas has a concentration of 50 ppm, of 0.7 liters / min. and a nitrogen gas flow rate of 35 liters / min, the heat treatment is carried out for a duration of 5 minutes, a mixed glass layer 74 with a thickness of approximately 3000 S. will then be formed. To carry out the diffusion from the glass diffusion sources, a heat treatment is carried out at a temperature of 1050 ° C. for a period of 80 hours in a weak oxidizing atmosphere.

Is the donor concentration in the used

- ■ xh "λ

N layer 72 under these circumstances 5 × 10 atoms / cm (10 ohm cm), then the respective impurity atoms have to have the diffusion parameters listed below: Diffusion depth of the boron atoms belonging to the generic areas = h / u, surface concentration =

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■ ι / f O

3 χ 10 atoms / cm; Diffusion depth of the emitter areas assigned arsenic atoms = 1.5 / ä, surface

17/3 'concentration = 1 χ 10 atoms / cm; Diffusion depth of the boron atoms belonging to the emitter areas = ieJ / W »

15/3 surface concentration = 6 χ 10 atoms / cm, where nearly intrinsic layers are introduced at the ends of the emitter regions 76 and in the gate regions 77 to around 1 / u from the ends of the emitter areas. With this the resistance can be increased to 20 ohm cm. Now the amount of boron atoms for the formation is increased If the emitter areas are enlarged compared to the aforementioned amount, the effect of the will gradually increase increasing resistance lower

When field effect transistors PET, in which there is a difference in the boron atom content, have been fabricated in this way, taking into account their triode behavior, it has been found that P ~ barrier layers have been introduced at the transition surfaces between the emitter regions and the channel regions, and that , when a control voltage is not applied, there is initially only a small current flow «This is due to the fact that the collector current cannot flow as long as the voltage has not yet reached the value for a necessary" breakdown ", namely zero approaching the intermediate // "" barrier layer by applying the collector voltage o In addition, in the Pail in which a y-layer is interposed, there is also a slight drop in voltage, which is why the start of the current flow is very poor. But in the event that a Yj barrier layer or a \ J layer is placed at the junction

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Between the emitter region and the gate region, a depletion layer can easily be built up by the Activation of the expensive voltage, which is why the / u factor is particularly large. In accordance with values that have been determined experimentally, when a barrier layer is built up, the Paktor / U several times greater than with a diffusion of Arsenic atoms alone in the emitter area.

In this invention, arsenic atoms and boron atoms were used as impurity atoms in the mixed glass layer above the emitter regions in the manner described above, but this required precise control of the diffusion layer surface concentration of the corresponding impurity atoms. However, acceptor atoms with larger diffusion coefficients were selected, and the required concentration distribution could be achieved comparatively easily. For example, gallium used instead of boron, the Diffusior.okoeffizientJ is _one three times as large, it can be so easily spread as boron as contaminant. That is why it is easier to control the concentration at the ends of the emitter areas. If the specific resistance or the type of conduction of the channels is to be changed, then this can be achieved via a series of diffusion processes in which the times change, without using two or more impurity atoms which differ in the diffusion coefficient.

When the emitter regions 76 are produced by diffusion the exposed points of the Gatt junctions on the surface of the body should be

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ziumdioxydschicht 78 be covered «An emitter electrode 79 »a Gatt electrode 80 as well as a collector electrode should be in the one already described for the previously described Exemplary embodiments described manner are produced. Does the execution of the subject matter of the invention the aforementioned structure, then it is a structure or construction in which the emitter areas are directly surrounded by the gate areas so that the high frequency performance is excellent, and the factor is controlled as necessary.

In this exemplary embodiment as well, the gate areas and the emitter areas can alternatively also be used any of the methods for the first through fifth embodiments can be prepared, the Resistance of the emitter areas can change.

A sixth exemplary embodiment of the invention will now be illustrated and described below with reference to FIG will. This is an example of a case where the outer peripheral parts of the gate area purposefully deeper than that other parts so that Gatt dielectric strength improves will. In the case of a diffused vertical field effect transistor FET, the body consists of a layer construction of an N diffusion layer 81 and an N ~ layer 82ο Are now in this N ~ layer 82 the category areas and the emitter areas are incorporated, then the dielectric strength between gate and emitter is determined by the specific resistance of the N -layer, · its thickness and the diffusion depth of the Gatt area "·

The dependence on the diffusion depth is particular

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2%

given when the Gatt area, by diffusing in will be produced. This means that if the N ~ layer has a specific resistance of several ohms has, the curvature of the PN junction of the gate area, produced by selective diffusion, is based on their transition voltage resistance »Because now with the Structure of the vertical delde effect transistor FET the diffusion depth of the gate is not large, it is usually not possible to maintain the dielectric strength of the gate to improve without affecting the other properties of the field effect transistor To change FET.

Therefore, a deep P diffusion area 83 is made in the part prior to making the gate area which will be the outer periphery part of the gate area using selective diffusion using a silicon dioxide layer and the photo-etching process. Then using the In connection with the aforementioned exemplary embodiments, the method described Gatt areas 8 ^ and the Finally, the following are used: - a gate electrode 86 an emitter electrode 87, while the collector electrode consists of the N layer is led out, and the field effect transistor FET is complete.

If this is done, then the dielectric strength becomes between gate and collector of the construction parameters determined, but in particular by the curvature that is brought about in the outer peripheral part 83 of the gate area will . But this is a very good way to improve the Gatt dielectric strength without the other

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lo

change their parameters of the semiconductor device. In addition, the DC resistance becomes perpendicular to the cross-section of the peripheral part kept small, therefore also with regard to the peripheral part of the Class area. As a result, when the DC resistance in a vertical direction is small, the Electricity output per unit area can be made larger.

As concerns this exemplary embodiment, the gate areas and the emitter areas can also be used any of the methods mentioned in connection with the embodiments described so far are made »by the fact that the outer peripheral part of the gate area is then also made thick semiconductor devices can be manufactured with the same advantages.

A seventh embodiment of the subject invention vill now below with reference to FIG _o 12 illustrated and described. In this exemplary embodiment, the gate reverse current of a vertical field effect transistor is reduced, and the voltage resistance between gate and collector is also improved. The description thus deals with a P-channel field effect transistor FET. First of all, the body of the semiconductor device is manufactured. This body is made of a layered construction and has the P ⁺ diffusion layer 111 and a P ~ or region 112 Intrinsic semiconductor is referred to as a -layer in the case of a P-channel and as a -layer

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for the pall of an N channel. A silicon dioxide layer to which phosphorus atoms have been added (a PSG layer) is applied to the surface of the area 112 and removed again in the photo-etching process except for the PSG layers 4-13, which form the diffusion sources for the Gatt area. Is then carried out a heat treatment to a selective diffusion of phosphorus atoms from this Gattbereiche PSG layer out in the Gattbereiche for producing perform _o Gattbereiche These are marked with the general reference number IL4. Now the holes for the production of the emitter areas 115, which are to be produced by diffusion, are worked in. At the same time, however, part of the silicon dioxide layer on the outside of the periphery of the gate areas II4 is removed by photo-etching. These silicon dioxide layers were created during production by diffusion the Gatt areas 114. The aforementioned removed parts are removed from the outside of the periphery of the Gatt areas at the necessary intervals to maintain the Gatt dielectric strength. Boron is diffused into the holes created in this way, producing the P emitter regions 115 and a P channel blocking region II6 Silicon dioxide layer on the P -channel barrier layer removed by photo-etching, and a metal layer 119 inserted, which extends over the edge of the peripheral part of the gate areas in such a way that the electric field from the depletion layer,

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which will arise when a reverse voltage is applied to the Gatt electrode is applied, then the same potential becomes on the surface of the semiconductor device Tang, then becomes the channel blocking effect tint sustained from the P -layer a collector electrode is also brought out.

If now a high resistance field effect transistor FET is designed and manufactured, then the area 112, which has a high resistance, has been used, the specific resistance being not less than 20 ohm cm. In addition, if the field effect transistor FET a P channel becomes even when the resistivity of the high resistivity Area is not very large, at the transition of area 112 on the outer periphery of the Gatt region The structure of this easily constructed N-barrier layer Barrier layer occurs through the influence and the EF effect of a redistribution of the impurity atoms, if the silicon dioxide layer is produced and through the action of the alkali ions in the silicon dioxide the effect of the ions in the outside atmosphere due to the external stray field belonging to the contamination layer electric field, when applying a reverse voltage between gate and collector, by the effect of new distribution of polarized molecules and the like. If with a field effect transistor FET with P channel the N layer gets a relatively high specific resistance, there are cases in which the ions in an outside atmosphere because of the external stray field of the electrical generated in the depletion layer Field, the redistribution of the polarized molecules

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72-355

33

as well as the polarization of the foreign matter on the surfaces of the silicon dioxide layer and the like cause more, that a barrier layer or P barrier layer is built up at the transition between the N ~ -Sohioht and rtptn SAliaiumdioxid. If a barrier layer of this kind builds up, the reverse voltage at the gate increases, but beyond that the dielectric strength between gate and collector is destroyed and reduces reliability. For this reason and to prevent a barrier layer of this Kind can spread, the metal layer 119 is provided, which doped the periphery of the gate area with a heavily Layer surrounds and the upper part of the silicon dioxide layer at the same potential as that of the gate area brings. In this way, the aforementioned problems can be solved.

In this embodiment of the subject matter of the invention can the gate areas and the emitter areas also using produced by one of the methods described in connection with the first to fourth exemplary embodiments will. The same effect can be achieved when a channel blocking area is provided to prevent inversion.

An eighth exemplary embodiment will now be illustrated and described below with reference to FIG. This embodiment is an example that the collector electrode together with the emitter electrode and the Gatt electrode is led out of the same major surface of the body of the semiconductor device. The description relates in this case to an N-channel field effect transistor FET. First is the body - this consists of a layer

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construction with an N diffusion layer 121 and an N ~ region 122 - produced. The upper surface of the N - layer 122 is oxidized, with a silicon dioxide layer 123 being formed. A part of this dioxide layer 123 is removed again using the photo-etching process, whereupon phosphorus atoms are diffused in through the opening. In order to clarify the position of the N-layer 124 in the subsequent operations, a heat treatment is carried out in an oxidation atmosphere, the hole in the silicon dioxide, which was used for selective diffusion, being covered with a comparatively thick oxide film. Then the silicon dioxide deposited on the N - layer 122 and on the N - layer 124 is etched and removed from the entire surface. An extremely shallow recess is at the location of the hole for the aforesaid selective diffusion prepared _o due to the formation of the new Siliziumdioxydes Therefore, this recess is taken as a reference in the preparation of the emitter regions 125, the Gattbereiche 126, the emitter electrode 127, and the Gatt -Electrode 128; these are produced using the method according to FIG. 4. Simultaneously with the attachment of these electrodes, a hole is produced by photoetching in part of the silicon dioxide layer above the N diffusion layer 124, the collector electrode 129 then being led out.

The above-mentioned N layer can be arranged so as to surround the peripheral part of the gate area. The collector electrode can be placed around the

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around the Gattberoich to be led out, namely to one or more places. The task of this N -diffusion layer 124 loigt is that the collector electrode 129 led out with the same potential as the N layer 121 will. Instead of the diffusion process, it is possible to work a hole that extends up to the N layer by chemically etching away the silicon from and through the major surface Hole - from the bottom of this hole - to lead out a metal electrode. This goal can also be achieved by combining chemical etching and diffusion, in this way now the The collector electrode is led out on the same side as the emitter electrode and the Gatt electrode be led out. This is a suitable construction in cases where it is desirable to have a metal plate only to be attached to the opposite side for heat dissipation, so that the collector electrode: is led out of the upper surface of the base plate.

Also in this embodiment of the subject matter of the invention For example, the emitter regions and the gate regions can be produced using the methods described in connection with exemplary embodiments one to four will. In this case, too, the construction can be designed in such a way that the collector electrode with the emitter electrode and the gatt electrode is led out on the same side, in addition, the Embodiments five to eight can be combined with one another when carrying out this invention.

It has already been described that when

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the gate area raits the emitter area in direct contact and surrounds this area in the form of a ring, this gate area and this emitter area are common exposed part, the consequence of this is the Gatt series resistance r small and the constriction process reliable, the PW junction and the junction capacitance C "_ between gate and emitter areas become small, what also

results in a small time constant C ₀ r, so that

CrO G

a semiconductor device with an excellent high frequency behavior can be created.

Each illustrated and described embodiment the subject of the invention was a vertical field effect transistor FET of the Molirkanal version, in which a number of gate areas are incorporated into the base plate became. But this invention may also relate to a vertical field effect transistor FET with a semiconductor region the N-conductor version (or the P-conductor Embodiment), which forms a collector region in the body of the semiconductor device, with only one channel is incorporated into the body. That means the installation a vertical field effect transistor FET of this type in an integrated circuit with an N-type body or a P-type body can be easily carried out. Also the construction of a P-channel field effect transistor FET should be taken from the given description of an N-channel field effect transistor FET can be clearly derived. While in the first embodiment to the fifth Embodiment the body of the semiconductor regions consisted of a multilayer construction, with concentration formations that differ from each other, so it can also consist of a single semiconductor area "

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Claims (8)

PATENT LAWYERS F.W. HEMMERICH · GERD MÖLLER · D, LARGE · Γ. POLLMEIER September 1, 1975 g.ke 72 355 TOKYO SHIBAURA ELECTRIC COMPANY LIMITED Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa-ken, Japan Claims f 1.y barrier field effect transistor with a basic ^ """^ body of a semiconductor material of one conductivity type with a drainage area and a source area of the same conductivity type and a gate area of the alternative conductivity type, characterized in that the source area and the gate area of a main surface of the body (12, 22, 32, 52, 72, 82, 112, 122) are arranged starting, and that the source area has a large number of individual districts (15, 26, 35, 56, 63, 76, 85, 115, 125), which are enclosed by closed meshes (13, 24, 37, 55, 62, 75, 84, 114, 126), which are formed by areas of the goal area, directly adjoining them. 2. FET according to claim 1, characterized in that the goal area has a closed mesh Lattice is formed that extends over the length of each mesh from the main surface of the body in this extends, and its source districts each extend from the main surface of the body into the mesh extend. - 36 - 609813/0697 253902Ö PATENT LAWYERS F.W. HEMMER I · GERD MÖLLER · D. GROSSE · F. POLLMEIER 3. FET according to claims 1 or 2, characterized in that that the gate area extends from the surface of the body deeper into it than the Source districts. 4. FET according to claims 1 or 2, characterized in that the gate area extends from the main surface of the Body extends out essentially as deep into these as the source districts. 5. FET according to claims 1 to 4, characterized in that the gate area is preferably along its Circumference has provided areas that extend deeper into the body than the rest, areas located inside its base. 6. FET according to claims 1 to 5,
characterized in that the drainage area (124) is arranged to the side of the gate area (126) in the body (121/122) and extends into the latter from its main surface. 7. FET according to claim 6, characterized in that the body made of semiconductor material a layer (122) of low conductivity adjoining its main surface and on the main surface thereof opposite side has a layer (121) of higher conductivity, and that the drainage area (124) through the layer (122) of lower conductivity to the layer in contact with it (121) higher conductivity extends. 609813/0697 PATENT LAWYERS F.W. HEMMERICH · GERD MÜLLER · Ü. ÜPÜSSE · F. POLLMEIES 8. FET according to claim 7, characterized in that the connection electrodes (127, 128, 129) of the Source, gate and drainage areas (125, 126, 124) on the same major surface of the body are arranged. 60981 3/0697 Ho Blank page