DE2527969A1 - Verfahren zur herstellung oxid- isolierter feldeffekt-transistoren - Google Patents
Verfahren zur herstellung oxid- isolierter feldeffekt-transistorenInfo
- Publication number
- DE2527969A1 DE2527969A1 DE19752527969 DE2527969A DE2527969A1 DE 2527969 A1 DE2527969 A1 DE 2527969A1 DE 19752527969 DE19752527969 DE 19752527969 DE 2527969 A DE2527969 A DE 2527969A DE 2527969 A1 DE2527969 A1 DE 2527969A1
- Authority
- DE
- Germany
- Prior art keywords
- field effect
- effect transistors
- isolated field
- manufacturing oxide
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US484033A US3899363A (en) | 1974-06-28 | 1974-06-28 | Method and device for reducing sidewall conduction in recessed oxide pet arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
DE2527969A1 true DE2527969A1 (de) | 1976-01-08 |
DE2527969C2 DE2527969C2 (de) | 1985-07-04 |
Family
ID=23922460
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2527969A Expired DE2527969C2 (de) | 1974-06-28 | 1975-06-24 | Verfahren zur Herstellung oxid- isolierter Feldeffekt-Transistoren |
Country Status (7)
Country | Link |
---|---|
US (1) | US3899363A (de) |
JP (1) | JPS5436034B2 (de) |
CA (1) | CA1053378A (de) |
DE (1) | DE2527969C2 (de) |
FR (1) | FR2276691A1 (de) |
GB (1) | GB1499848A (de) |
IT (1) | IT1038052B (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3023410A1 (de) * | 1980-06-23 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von mos-strukturen |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4044454A (en) * | 1975-04-16 | 1977-08-30 | Ibm Corporation | Method for forming integrated circuit regions defined by recessed dielectric isolation |
US4008111A (en) * | 1975-12-31 | 1977-02-15 | International Business Machines Corporation | AlN masking for selective etching of sapphire |
US4075045A (en) * | 1976-02-09 | 1978-02-21 | International Business Machines Corporation | Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps |
US4035198A (en) * | 1976-06-30 | 1977-07-12 | International Business Machines Corporation | Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors |
FR2358748A1 (fr) * | 1976-07-15 | 1978-02-10 | Radiotechnique Compelec | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
JPS5341179A (en) * | 1976-09-28 | 1978-04-14 | Toshiba Corp | Semiconductor device and its manufacture |
US4553314B1 (en) * | 1977-01-26 | 2000-04-18 | Sgs Thomson Microelectronics | Method for making a semiconductor device |
US4113516A (en) * | 1977-01-28 | 1978-09-12 | Rca Corporation | Method of forming a curved implanted region in a semiconductor body |
US4070211A (en) * | 1977-04-04 | 1978-01-24 | The United States Of America As Represented By The Secretary Of The Navy | Technique for threshold control over edges of devices on silicon-on-sapphire |
US4182636A (en) * | 1978-06-30 | 1980-01-08 | International Business Machines Corporation | Method of fabricating self-aligned contact vias |
US4198250A (en) * | 1979-02-05 | 1980-04-15 | Intel Corporation | Shadow masking process for forming source and drain regions for field-effect transistors and like regions |
WO1981002074A1 (en) * | 1980-01-11 | 1981-07-23 | Mostek Corp | Method for making a semiconductor device |
US4315781A (en) * | 1980-04-23 | 1982-02-16 | Hughes Aircraft Company | Method of controlling MOSFET threshold voltage with self-aligned channel stop |
US4472874A (en) * | 1981-06-10 | 1984-09-25 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of forming planar isolation regions having field inversion regions |
US4596068A (en) * | 1983-12-28 | 1986-06-24 | Harris Corporation | Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface |
JPS61224459A (ja) * | 1985-03-29 | 1986-10-06 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH06349820A (ja) * | 1993-06-11 | 1994-12-22 | Rohm Co Ltd | 半導体装置の製造方法 |
US6780718B2 (en) * | 1993-11-30 | 2004-08-24 | Stmicroelectronics, Inc. | Transistor structure and method for making same |
JP3319227B2 (ja) * | 1995-06-29 | 2002-08-26 | 三菱電機株式会社 | 電力用圧接型半導体装置 |
US6022751A (en) * | 1996-10-24 | 2000-02-08 | Canon Kabushiki Kaisha | Production of electronic device |
US6190979B1 (en) | 1999-07-12 | 2001-02-20 | International Business Machines Corporation | Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill |
US6348394B1 (en) | 2000-05-18 | 2002-02-19 | International Business Machines Corporation | Method and device for array threshold voltage control by trapped charge in trench isolation |
US6927414B2 (en) * | 2003-06-17 | 2005-08-09 | International Business Machines Corporation | High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof |
JP4718894B2 (ja) * | 2005-05-19 | 2011-07-06 | 株式会社東芝 | 半導体装置の製造方法 |
US20080029893A1 (en) * | 2006-08-07 | 2008-02-07 | Broadcom Corporation | Power and Ground Ring Layout |
JP5444694B2 (ja) * | 2008-11-12 | 2014-03-19 | ソニー株式会社 | 固体撮像装置、その製造方法および撮像装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3440502A (en) * | 1966-07-05 | 1969-04-22 | Westinghouse Electric Corp | Insulated gate field effect transistor structure with reduced current leakage |
DE2238450A1 (de) * | 1971-08-05 | 1973-02-15 | Signetics Corp | Halbleiterbaugruppe und verfahren zur herstellung derselben |
US3742317A (en) * | 1970-09-02 | 1973-06-26 | Instr Inc | Schottky barrier diode |
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
US3752711A (en) * | 1970-06-04 | 1973-08-14 | Philips Corp | Method of manufacturing an igfet and the product thereof |
US3755001A (en) * | 1970-07-10 | 1973-08-28 | Philips Corp | Method of making semiconductor devices with selective doping and selective oxidation |
DE2320195A1 (de) * | 1972-04-24 | 1973-12-13 | Standard Microsyst Smc | Durch ionenimplantation hergestellter speicherfeldeffekt-transistor mit siliciumbasis |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3550292A (en) * | 1968-08-23 | 1970-12-29 | Nippon Electric Co | Semiconductor device and method of manufacturing the same |
US3615875A (en) * | 1968-09-30 | 1971-10-26 | Hitachi Ltd | Method for fabricating semiconductor devices by ion implantation |
US3550260A (en) * | 1968-12-26 | 1970-12-29 | Motorola Inc | Method for making a hot carrier pn-diode |
GB1332932A (en) * | 1970-01-15 | 1973-10-10 | Mullard Ltd | Methods of manufacturing a semiconductor device |
US3659160A (en) * | 1970-02-13 | 1972-04-25 | Texas Instruments Inc | Integrated circuit process utilizing orientation dependent silicon etch |
-
1974
- 1974-06-28 US US484033A patent/US3899363A/en not_active Expired - Lifetime
-
1975
- 1975-04-11 CA CA224,582A patent/CA1053378A/en not_active Expired
- 1975-05-14 IT IT23306/75A patent/IT1038052B/it active
- 1975-05-16 JP JP5751375A patent/JPS5436034B2/ja not_active Expired
- 1975-05-21 GB GB21855/75A patent/GB1499848A/en not_active Expired
- 1975-05-23 FR FR7516564A patent/FR2276691A1/fr active Granted
- 1975-06-24 DE DE2527969A patent/DE2527969C2/de not_active Expired
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3440502A (en) * | 1966-07-05 | 1969-04-22 | Westinghouse Electric Corp | Insulated gate field effect transistor structure with reduced current leakage |
US3752711A (en) * | 1970-06-04 | 1973-08-14 | Philips Corp | Method of manufacturing an igfet and the product thereof |
US3755001A (en) * | 1970-07-10 | 1973-08-28 | Philips Corp | Method of making semiconductor devices with selective doping and selective oxidation |
US3742317A (en) * | 1970-09-02 | 1973-06-26 | Instr Inc | Schottky barrier diode |
US3751722A (en) * | 1971-04-30 | 1973-08-07 | Standard Microsyst Smc | Mos integrated circuit with substrate containing selectively formed resistivity regions |
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
DE2238450A1 (de) * | 1971-08-05 | 1973-02-15 | Signetics Corp | Halbleiterbaugruppe und verfahren zur herstellung derselben |
DE2320195A1 (de) * | 1972-04-24 | 1973-12-13 | Standard Microsyst Smc | Durch ionenimplantation hergestellter speicherfeldeffekt-transistor mit siliciumbasis |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3023410A1 (de) * | 1980-06-23 | 1982-01-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung von mos-strukturen |
Also Published As
Publication number | Publication date |
---|---|
JPS5436034B2 (de) | 1979-11-07 |
US3899363A (en) | 1975-08-12 |
FR2276691B1 (de) | 1977-04-15 |
DE2527969C2 (de) | 1985-07-04 |
IT1038052B (it) | 1979-11-20 |
CA1053378A (en) | 1979-04-24 |
JPS513881A (de) | 1976-01-13 |
GB1499848A (en) | 1978-02-01 |
FR2276691A1 (fr) | 1976-01-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OD | Request for examination | ||
8128 | New person/name/address of the agent |
Representative=s name: OECHSSLER, D., DIPL.-CHEM. DR.RER.NAT., PAT.-ASS., |
|
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |