DE2447437A1 - ARRANGEMENT WITH MEMORY MATRIX - Google Patents

Description

PHN.7186.

DEEN / EVH. DIETER POL-JiG

Jhtentaneuor

Applicant: fl.V.PhÜ'ps ¹ Cx '.-. Npanfabriskan
File no .: f (-J | \, 7 η ^ (. '
Registration from; ^ / C Ii /

Arrangement with memory matrix

The invention relates to an arrangement with at least a memory matrix with memory elements at intersections of rows and columns, with at least one row for at least one storage element belonging to this row and for at least one more distant one Row belonging memory element first and second selection means are provided with which when selecting this Row, the at least one storage element belonging to this row or the at least one of the more distant row belonging memory element selectable and further at a first terminal of the first selection means a control signal and at a second terminal the second

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Dialing means the complement of the control signal can be received «

Such dies provided in the above arrangement are known in a number of forms Task, either a memory element (or a complete memory word) of a line or a memory element Selecting (or a complete memory word) of a more distant line is in the known arrangements a pure matter of addressing. The least significant address bit (θ or 1) addresses the one line or a more distant (usually a following) line in the matrix,

The invention has the object of indicating that there is an interesting possibility of such matrices to use, the addressing itself no longer being the end but just a means to another end is: In data processing technology, so-called "step" commands, or INCREMENT- (+ step-) and DEIvREMENT (step) commands use that must be performed by data processing systems. These "step" commands are in accordance with the invention Arrangement can be carried out in a very simple way. To this end, the invention is characterized in that a Control arrangement is provided in which on the basis of a one-step INCREMENT command and / or one One-step DECREMENT command the mentioned control signal can be determined »

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If, in particular, adding and subtracting operations in a data processing arrangement are to be considered are drawn, a further embodiment of the arrangement according to the invention is characterized in that that the mentioned control arrangement is part of an arithmetic unit and the mentioned control signal is a transmission signal is.

An inventive arrangement in which on far advanced way of using the inventive concept is characterized in that the aforementioned memory matrix is a read-only memory matrix in which one line with the first dialing means and one line with the second Dialing means the following line can be selected and where the control arrangement by a second read-only memory matrix is formed in which one of the columns is a transmission signal collecting column is and wherein said first and second memory matrices each with one as Address selector serving scanning registers together form an adding-subtracting arithmetic unit. In the above mentioned Memory matrix, it is superfluous that with a row of the memory matrix for each to this row and to a more distant row belonging memory element separately first and second selection means are provided. This is just ' necessary in those cases when bit selection is required, i.e. when each memory element must be selectable. However, if one can get by with word choice, i. E.

50981 11 1 0 Λ 3

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2447A37 ²⁵ - ^{9 74}

there must be a whole row of storage elements at one time be selectable, so it is for one in the invention Arrangement used memory matrix possible that the first selection means all belong to one row Storage elements and that the second selection means all storage elements belonging to a more remote Zsile are common, if, especially when using integration techniques for the production of memories, the line and the column structure of a memory matrix must be used or preserved as often as possible, it is for the memory matrix used in the arrangement according to the invention possible that the mentioned first selection means line by line via a first common sub-line conductor with a first control column common to all first selection means and the second selection means line by line via a second common sub-line conductor with a control column common to all second selection means are connected, the sub-row conductors to the rows and the drive columns to the columns of the memory matrix run parallel. This again applies in particular to the memory matrix in which bit selection is possible. Is the Memory matrix set up for word selection and are line-by-line common first and common second selection means present, the above-mentioned condition can also be met by the fact that the first selection means with a first common to all first dialing means

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Control column and the second selection means with one all second selection means common control column connected and the drive columns to the columns of the memory matrix run parallel. Whether this is practical for a particular type of storage is up to the Conditions depending on the surface and speed, for example. The ones present in this arrangement Common first and second dialing means per line are - the power supply over an entire line must deliver, so that these selection means must be designed "strong" enough to be able to meet the speed requirements.

In practice, the means of selection are AND gates be. They are comparable to controlled switches. It it should be noted that in practice the more distant row of the matrix is often an adjacent (following, preceding) Line will be.

The, storage elements for · the storage matrix according to of the invention can be of many types: magnetic cores, semiconductor elements (dynamic, static), etc. Applying of the inventive concept is particularly in read-only memories Interesting. Words that serve as control words in microprograms are often stored here. When executing The above-mentioned "step commands" often come from microprograms before, - "■ - ·

Embodiments of the orfindungsgeraässen

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Memory matrix and the memory with such matrices are explained in more detail below with reference to the drawings. Show it

1 shows an arrangement according to the invention applied memory matrix with first and second selection means per row per memory element,

FIG. 2 shows a memory matrix according to FIG. 1 in a modified embodiment,

3 shows an arrangement according to the invention applied memory matrix in which first and second selection means are common to the memory elements in rows,

Fig. H shows another embodiment in a memory matrix applicable according to the invention,

5 shows a complete in one according to the invention Arrangement of applicable memory,

6a, 6b show an arrangement according to the invention and an associated signal table,

FIG. 7 according to the invention in a ^a: arrangement applicable memory having a read only memory matrix,

8 shows an electrical detailed circuit of a read-only memory matrix which can be used in an arrangement according to the invention according to Fig. 7t

9 shows an electrical detailed circuit of a circuit which can be used in an arrangement according to the invention Write / read matrix according to Fig. 6a,

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24A7437

FIG. 10 shows the read-only memory matrix detail of FIG. 8 in integrated form;

11 shows the read / write memory matrix detail of FIG. 9 in integrated form;

Fig. 1 shows a in a erfindungsgenassen Arrangement applicable memory matrix M in order to, after a row has been selected, a memory element belonging to this row or to select a storage element of the adjacent row · In this matrix there is one option per storage element m present. Namely, each line ri-2, ri-1, ri, .... has first selection means S1 (switches) and second selection means S2 (switch) for each storage element m. The outputs of the storage elements m are marked with columns kj-1, kj,.,. tied together. The first selection means S1 are over first sub-line conductor S1ri-2, S1ri-1, S1ri, ... connected to a first control column a. So are they too second selection means via second sub-line conductor S2ri-2, S2ri-1, S2ri, ... connected to a second control column ä. The example ^ 'of this Fig. 1 shows that the attachment of the dialing means and the associated ladder fits completely into the structure of the original memory matrix of the memory M. Especially with integrated ones Saving this is an advantage. The way it works is as follows. Assuming a row ri is selected. Further provided that a column kj is selected. The control column carries a 0 signal and

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a 1 signal. The memory element mij is hereby selected, because the switch S1 belonging to this element mij is closed via the subline conductor S1ri with the control column a carrying a 1-signal. In this situation, data transmission to / from the element mij can therefore take place via the column kj. If, conversely, the control column carries a 0 signal and a 1 signal, the switch S2 is closed via the sub-row conductor S2ri. The storage element mi-1, j is hereby selected. In this way, when selecting a specific column kj, either the memory element mij belonging to this row ri or the memory element rai-1, j belonging to an adjacent row ri-1 can be selected in the memory. The line selection does not change ₉ but the signal via the control columns is decisive "In other words, each line in the memory ^{matrix has not one but two" labels 1} ! (Information), because when you select a single line and a single column two memory elements have become accessible »If several columns or all columns kj of a memory matrix of a memory are considered in a row selection, then it is a so-called word-organized memory. If a memory with matrices is word-organized as described above, the memory elements m, the together form a word Vf ,, atts selected In the example according to Fig. 1 it is in the selection of the lines ri and a = 0 (a = 1)

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the word Wi, while at a = 1 (a = θ) the word Wi-1 is selected.

Pig. 2 shows another embodiment memory matrix usable in an arrangement according to the invention, starting from the example according to FIG. 1, it is now indicated that the ¥ ählmittel S1 and S2 AND gates E1 and E2 are. Either gate E1 will become via subline conductor S1ri from control column a or gate E2 be prepared via subline conductor S2ri from the control column ä. Will be a line and one or more Columns selected, data can be transmitted via gate E1 or gate E2. this means that is, that storage element (s) belonging to this line ri mi or memory elements mi-1 belonging to the adjacent row ri-1 are selected.

In Fig. 3 one is indungsgeniässen in one of the invention Arrangement, applicable memory matrix shown in the the first selection means, here the AND gates E1, i-2; E1, i-1; E1, i; ... all in one line (ri-2, ri-1, ri, ...) Corresponding storage elements (Vort Wi-2; Wi-1; Wi; ...) are common and in which the second. Selecting means, here the AND gates E2, i-2; E2, i-1, E2, i; ..., all of them to neighbors Lines (ri-1, ri-, ri + 1, ...) belonging to memory elements (word Wi-1; Wi; Wi + 1; ...) together are,

So this is for a word-organized

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Storage matrix M possible. In this example, one input of each AND gate E1, i, ... is connected to a common drive column a, matching the structure of the matrix with rows and columns. An input of each AND gate E2, i, ... is also connected to a common control column & connected. A second input of E1, i, ... and E2, i, ... is connected to the relevant input of row ri. The outputs of the gates E1, i, ..., are connected to the rows ri ... themselves, while the outputs of the gates E2, i, ... are connected to the adjacent rows ri + 1 .... If the column a carries a 0 signal, gates E1, i, ... are prepared and the word Wx will be selected when a row ri is selected. If column a has a 1 signal, gates E2, i, ... are prepared and the word Wi + 1 will be selected when the same row ri is selected.

. H the example is a memory matrix applicable in an inventive arrangement ones shown, ■ represents in which when selecting a line belonging to that row elements or belonging to a more distant line elements, namely in this example, two lines further in Fig. are selectable. In principle, any line that is further away can be selected for this. The rows of the matrix are again labeled ri. It is a column k1 of the matrix and the drive columns a and a are shown. First el, i; ... and second

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Selection means e2, i; ... \ are provided jointly for memory elements in a line. The selection from outside (decoder or scanner) is made at the line inputs, which are marked with gri, .... According to FIG. H , a line input gri is connected to an input of the TJND gate e2, i. and connected to an input of the AND gate e1, i + 2. The AND gate e2, i receives at another input the control signal which is carried by the column a, while the AND gate e1, i receives the control signal of the column ä at another input. The output of the AND gate el, i is connected to the output of the AND gate e2, i. Together these outputs are then connected to the matrix row ri.

The following has been achieved with this list:

The selection z »B, of the line input gri-1 gives the possibility to select either the word Wi-1 belonging to the line ri-1 or the word Wi + 1 belonging to the row ri + 1 more distant by two places in the matrix. A "step" command thus here comprises two steps: a 1 signal at a prepares the AND gate e1, i + 1 before and thus, the selection signal at the line input gri-1 is allowed to pass through this gate and reaches the line ri + 1, that is to say two lines further than ri-1, which would have been selected if the column a had carried a 0 signal »FIG. 5 shows a complete in one

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memory applicable according to the invention. The matrix is the matrix according to the description of FIG. 1 with a few other peripheral devices. The AND gates E1, i ..., E2, i, ... are now intended to be included in the switching arrangement SV. A decoder DEC and an input / output register IHR with input / output IU are also specified, with which the memory is connected to its periphery. In SW, the control columns a and ä, which are connected to the outside via terminals c and c, run. The addresses AD of the lines to be selected are offered to the decoder DEC. A specific address, for example ADn, with which the line rn is designated ₉ selects the input of the line rn. At terminal c, for example, there is a 0 signal and thus terminal c carries a 1 signal. Via the switching arrangement S, the gates E1, ± · “, (Fig. 3) are now prepared and the word Wn is thus selected. Data transfer to / from the input / output register IUR can now take place. If there is a 1 signal (c = O) ₉ at the terminal c, the gates E2, i, »,. (Fig ₀ 3) were prepared and the adjacent word, here through selection of the row τη the word Wn + T = V, * 1, is selected ₀ This has been achieved in that at the end of the memory array, the word Wn is located and in this example the adjacent word to a notch is located, namely, back to the beginning so ;, the word V1 _e to make this verwirklicheng it is necessary only in this example, the output of the gate E2 ₉ i (compare regard, the

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Figure the gate E2, i + 1 in Fig. 3) in Fig. K denoted by u, to be connected to the line rl (behind the switching arrangement STv ').

FIG. 6a shows an arrangement according to the invention with a matrix M according to FIG. 1 with some further devices, among which the control arrangement A5. In this arrangement according to the invention, the line selection takes place with a scanning register SR, "whose" outputs are connected to the lines of the memory matrix M. This register shifts a 1-bit through the register on control by a clock generator via the input Cl. The position of this 1-bit selects a line via the relevant output. The control of the first and second selection means, which may be included in the storage element per storage element, takes place via the dotted (lower and upper) sub-line conductors or first sub-line conductors S1ri and second sub-line conductors S2ri connected to the storage elements. Control columns a and a are controlled via the terminals c and c from the control arrangement AS with the AND gates ED and EI and the inverter TV . Furthermore, there is an input / output register IUR and a data processing arrangement CP in this illustrated arrangement according to the invention. In the matrix M there is an additional row conductor r1 'which is connected to the row r1 so that when selecting the row r1 and with 1- signal

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at a not the word WT, but the word W1-1 = Wn selected will. This takes into account the circulation at the end of the store

With this illustrated according to the invention

The arrangement is the handling of a one-step INKR (EMEXT) -I and a one-step DEKR (EMEXT) -D command with the table according to FIG. 6b described, which is output from the data processing arrangement CP. Output D from CP has a 1 signal, so that the DEKR command is present. Output b carries an O signal (b = 1) as long as a certain Procedure in CP, command D does not yet need to be followed (e.g. CP is in a search procedure involved, whereby it is required that the DEKR command is obeyed during the search process). With D = 1 and b = 0 and also I = O, the AND gates are ED and EI not permeable and so the control arrangement AC does not give a signal to c, while via the inverter IV to the Terminal c 1 signal is present. When selecting a line ri a word Wi is thus selected in the memory matrix. Now b = 1, so that the DECR command is followed has to be, the gate ED becomes permeable and specifies the control arrangement to the terminal c 1-signal or, respectively the terminal c O signal. At this moment it is through Selecting the mentioned line does not select the word Wi, but rather the word Wi-1. This means execution of the DECR (= "one step back") command,

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The following happens for INCR I: Output I of CP has a 1-signal, so that the INKR command is available. Output b has an O signal (b = 1), as long as INKR does not need to be followed. With 1 = 1 and b = 1, AND gate EI is permeable and the terminal, c 1 signal is supplied. This will when selecting a line ri the neighboring location Wi-1 be selected. If b = 1 now, so that the INKR command must be followed, then (see last line according to Fig. 6) both gates EI and ED not permeable, the control arrangement therefore supplies terminal c with a 0 signal and terminal c with a 1 signal. So now is by selecting the line ri, not the Vort Vi-I, but the word Wi selected. This means INIQR (= one step further).

In Fig. 7 is an inventive Arrangement of read-only memory matrix R0M1 shown. In this Fig. 7 is still a normal read only memory matrix R0M2 shown. The purpose of this is to indicate how such an arrangement is used in an arrangement according to the invention Read-only memory matrix R0M1 can be used, in particular in an arrangement according to the invention in which, when executing arithmetic processing of information so-called transfer signals (carries) occur. In order to the arrangement according to FIG. 7 forms an add-subtract arithmetic unit,

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In this FIG. 7, scanning registers SR1 and SR2, an inverting stage IV, an output register UR and a comparison arrangement V are also present. ROM1 and R0M2 are connected to one another via their columns, so that only one output register UR is required for both, R0M1 is filled with a table, namely the digits "0" to "9" in the BCD code. These digits "0" to "9" are stored twice in R0M2: "0" to "(i) 9 ^M positions. In addition, the" tens carry "is stored for positions" (i) 0 ⁿ to "(i) 9", they are thus located at the positions "(i) 0" to "(i) 9" of R0M2, specifically on column kc. A possible embodiment of R0M1 is described below with reference to FIG. 8 and FIG. 10, R0M2 can be a read-only memory that is known per se and implemented using integration technology. The operation of this entire arrangement is largely supplied by an unspecified information-controlling arrangement. Since it does not form part of the invention, its description has been omitted. It is important to indicate how arithmetic processing (adding, subtracting) can be carried out with this arrangement according to the invention. Is this explained below? provided that the input IR1 is offered a digit of a number to be treated. And this digit = "6" is in the BCD code. This digit is offered to the comparison arrangement V. At V there is also the register l ~

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connected. The content of UR is compared with the number parts at IR1. The scanner SR1 can run through pulses at Cl (SR2 is switched off) and TIR are offered successively when selecting the lines rl G, r9, ... the values "0""9", .... A has a 0-signal and a 1-signal. At position "6" of SR1, equality occurs in V. The scanner SR1 is stopped from V (signal VP from V). SR1 now remains in this position. This means that the aforementioned digit “6” is “recorded” in SR1. Also, a digit offered via input IR2, eg "3" in the BCD code, can be recorded in R0K2 with the help of arrangement V: During this time, SR2 runs in the upper part of R0M2 (positions "0" to "9") » until equality occurs in V (SRI is switched off). This happens in position "3" »SR2 stops. The following happens for an addition; the samplers SR1 and SR2 run by pulses on Cl tuid. although SR1 in the specified "R" (return) direction and SR2 in the specified "F" (forward) direction, if SR1 now reaches the "0" position, it emits a STOP signal. Stop the scanners. Meanwhile, the scanner SR2 has reached the position "3" plus "6" is equal to "9". This is the result of the addition. If, for example, digit "7" were offered via IR2, this "7" would be recorded in position "7" in R0M2. When adding (ROMI is at "6"), the sampler SR2 advances six steps vuid

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stops in position "(i) 3" »It thus occurs Transfer on, resulting in a transfer 1 signal CR at column kc, which is offered to flip-flop FF "This is where this lecture is recorded. That The mentioned result "9" (first case) or "3" (second case) can now be transferred to a result register from R0M2 will. This is done from the output register UR to output RR,

The whole organization now looks like that when a digit is recorded from the input RR to the R0M1 at an input T of the ÜXD gate ECR there is always a 1 signal. This gate, if present, allows a transfer CR stored in FF through. In the outlined second case ("6" + "7") this takes place. This means that control column a carries a 1 signal via terminal c. Thus, at the position of the scanner SR1 on a line ri, not the digit position "i" but the digit position "i-1" is selected. If a digit "5" ^a n V is now offered via IR1 and compared with the content of R0M1, equality occurs when the scanner SRT is in position "6", because in this case the digit "5" is selected . At this moment the contents of FF can be emptied.

After a new digit rule also rushed in R0M2, e.g. "2" is recorded, the addition of these new digits "2" and "5" plus transfer CR

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equal to "6": both scanners run until SR1 reaches the "0" position. This happens after six steps, because SR1 was initially in position "6". The result is that the result digit "2" plus "6" is equal to "8" is reached in ROM2. In this way, using ROM1 in the arrangement according to the invention, the transfer CR can be processed in a simple manner. When subtracting, something of this kind occurs mutatis mutandis SR2 in the indicated ^M R "direction. It will be clear that with this arrangement there is also the possibility of processing a DECREMENT and INCREMENT command in accordance with the descriptions according to FIGS. 6a and 6b.

At this point the following should be noted: the arrangement according to FIG. 7 can be based on a practical Advantageously, ROM1 and R0M2 can be integrated in a single solid will. It is even possible to go further: in a solid, in addition to R0M1, R0M2 and the Scanner SR1, SR2 also accommodated further memory sections in which the numbers to be processed are included. While maintaining the matrix structure read-only memories (ROMs) and the other memory

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Sections that can be read / write memories (RAMs), it is possible to continue the selection of the row conductor to leave and also to use in adjacent memory sections. The samplers SR1 and SR2 can then except for line selection in the read-only memories for line selection in the adjacent memory sections serve »The manner of execution is the topic of an earlier one filed application by the same applicant (PHN 7130 = Dutch patent application),

Note that using the Inventive idea and the idea mentioned above Registration is possible in a solid the arithmetic unit with input registers, result registers, keypad inputs and play code converter.

In the following, for the sake of completeness, the description of the invention is supplemented ₈ as to how a memory matrix that can be used in an arrangement according to the invention can be implemented in an integrated circuit.

Fig, 8 shows, together with Fig. 10, the example of a part of the matrix of a Festvertspeichernatrix, while Figure 9 together with Figo 11 represents a read / write memory array, the example of a part of the matrix ,, always a certain row is considered _a that by selecting the Memory elements of this line or the memory elements of the adjacent line can be selected.

In Fig. 8, one embodiment is one

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Fixed-value memory matrix reproduced, The memory matrix is made up of columns Y1, Υ2, ... and rows Χ1, Χ2 built up. It is clear that there are multiple columns -and rows may be used, but in this description the number is limited for clarity of illustration held.

Row X1 is connected on the one hand to the connection point of the gate electrodes of transistors 2 and 3 and on the other hand to the connection point of the gate electrodes of transistors 4 and 5. The row X2 is connected on the one hand to the connection point of the gate electrode of the transistors 10 and 11 and on the other hand to the connection point of the gate electrodes of the transistors 12 and 13. The gate electrodes of the transistors 6 and 8 are connected to the drive column conductor 13 together. The gate electrodes of the transistors 7 and 9 are connected to the drive column conductor 12 together. The main current paths of the transistors 2, 3, 6, 71, 10 and 11 are connected in series. The connection point of the main current paths of the transistors 2 and 3 and the connection point of the main current paths of the transistors 10 and 11 are connected to a point of constant potential, the connection point 16 of the main current paths of the transistors 6 and 7 is connected to the point 17 of the column conductor Y1. The main current paths of the transistors k _t 5 »81 9»

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PHN.7186.

12 and 13 are connected in series. The connection point of the main current paths of transistors k and 5 and the connection point of the main current paths of transistors 13 and 13 are connected to a point of constant potential. The storage locations in the matrix are in this example by the absence or the presence of the connections between the column conductors and aen. Formed connection points of the main current paths of the associated transistors, the gate electrodes of which are connected to the drive column conductors 14 and 14, respectively. For example, there is no connection between the point 16 and point 17 on column conductor deni YI and a connection between the point 18 and the point 19 on column conductor -Y2 present. The presence of the connections characterizes, for example, a logical 1 and the lack thereof, for example, a logical 0. This creates a read-only memory matrix.

A second exemplary embodiment of a memory matrix is shown in FIG. It is here a dynamic type read / write memory array. It shows four memory cells that are accommodated in two rows and columns. It will be evident to everyone appropriate number of cells can be applied. The memory cells are of dynamic type and are made by the transistors 25, 28, 2Q, 30 and from the corresponding ones Capacities 31, 32, 33 and 3 ^ formed. The gate electrodes

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of transistors 25 and 29 are connected to, the row conductor X1 ' and the gate electrodes of transistors 28 and 30 with

the row conductor X2 ^: connected. The main current path of the transistor 25 is arranged between the column conductor Y1 and the capacitance 31. The main current path of the transistor is arranged between the column conductor Y1 and the capacitance 33. The capacitance 32 is connected to the column conductor Y2 via the main current path of the transistor 29 and the capacitance 34 is connected to the column conductor Y2 via the main current path of the transistor 30. The connection points of the mentioned capacitors 31, 32, 33 and 34 facing away from the main current paths of the associated transistors are connected to a point of constant potential, eg ₀ earth The gate electrode of the transistor 23 is connected to the drive column conductor 22 and the gate electrode of the transistor 24 is connected to the drive column conductor 21. The connection point of the main current paths of the transistors 23 and 24 is connected to a decoder or sampling register 20 via the conductor X1. Between

1 1

Row conductors X2 and X3, the series connection of the main current paths of the transistors 26 and 27 is arranged. The gate electrode of the transistor 26 is connected to the Ansteuer.'ipaltenleiter 22 and the gate electrode of the

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Transistor 27 is connected to drive column conductor 21. The connection point of the main current paths of the transistors 2.6 and 27 is connected to the decoder or scanning register 20 via the conductor X2 «

The memory matrices according to FIGS. 8 and 9 can be made with the aid of the conventional methods used in semiconductor technology Technologies are implemented as an integrated circuit. In this context, for the sake of completeness, it should be noted that that the field effect transistors shown in FIGS. 8 and 9 can be completely or partially replaced by bipolar transistors, but especially when used of field effect transistors with insulated gate electrode relatively compact matrices can be achieved, and an example of such an integrated one The circuit is described below with reference to FIG.

Fig. 10 shows a part of a semiconductor body k z, Be of η-doped silicon in the doped p-with field effect transistors with an insulated gate electrode of the enhancement type and with a channel, the circuit of FIG. 8 is realized "The n-type semiconductor body ho contains a number p-surface zones hl, kZ and 4 3, while a crossbar system of conductor tracks is arranged on the surface of the body, the conductor tracks kh , hS and hG and in an almost vertical

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Conductor tracks 47 running thereon in the direction is formed. The conductor tracks are for the sake of clarity hatched in the figure. Located between the almost parallel conductor tracks 44, 45 and 46 and the conductor tracks 47 a layer of insulation.

In Fig. 8, the transistors have each of the

Transistor pairs 2 and 3 or 4 and 5 »10 and 11, 12 and a common electrode zone, these electrode zones each being connected to the same reference potential. In the integrated circuit, these electrode zones are designed as continuous zones 4i per matrix line. At the edge of the matrix, these zones 41 can with the help of a schematically indicated conductor track 48 with one another and with a connection point 49 for a supply voltage source get connected,

Veiter also have the transistors of transistor pairs 3 and 6 or 5 and 8, 10 and 7> 12 and 9 have a common electrode zone, in the integrated version it is also evaluated that the common electrode zones of pairs 3 and 6 and 5 and 8 are connected to one another without affecting the memory matrix is adversely affected. For the same reason, the common electrode zones of the pairs 10 and 7 and 12 and 9 are connected together. In Fig. therefore, each zone 41 becomes one on both sides

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also flanked continuous zone 42.

Between the zones 41 and 42 there are channel areas bordering the semiconductor surface the gate electrodes 44 extend, it is indicated schematically in FIG. 10 that the two always extend opposite side of each zone 41 lying gate electrodes, e.g. at the edge of the memory matrix. These two and two connected to each other Gate electrodes form the row conductors X1, X2 etc.

Finally, the transistors of the transistor pairs 6 and 7 or, S and 9 have one thing in common Electrode zone, these common electrode zones are formed by the surface zones 43 and correspond the points 16 and 18 of Fig. 8, between the zones and 43 there are channel areas which can be controlled with the aid of isolated gate electrodes 45 and 46. All of the gate electrodes 45 are at the edge of the matrix with the drive column conductor i4 and all of the gate electrodes 46 connected to the drive column conductor 15, as schematically is specified.

The data content of the memory matrix is determined by the fact that the zones 43 each have a column of the zones 43 lying conductors 47 are connected or not which conductors make up the column conductors Ύ1, Y2, etc. For example, the column conductor Y1 is via an opening 50

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in the insulating layer with the one in the middle of the Figure lying zone 43 connected, while such Opening above the adjacent zone 43 is missing. The latter zone 43 is therefore not associated with the associated one Column conductor Ύ2 connected.

The integrated circuit described can be completely based on that customary in semiconductor technology Ways to be manufactured «The surface zones can e.g. be attached by diffusion or ion implantation. The insulating layers can be made of silicon oxide, for example and / or silicon nitride. The conductor tracks are e.g. made of aluminum, molybdenum or semiconductor material, The gate electrodes shown horizontally can advantageously consist of polycrystalline silicon, wherein the conductor tracks shown vertically can, for example, be made of metal such as aluminum.

Instead of p-channel field effect transistors you can also n-channel field effect transistors are used,

The second exemplary embodiment, the circuit of which is shown in FIG. 9, can also be used as an integrated Circuit are executed. It is about a read / write memory matrix in

in the sense that within the scope of the invention the in the matrix j

memory cell to be used almost freely from the cells known for memory, both dynamic and

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static, can be selected. In addition to memory cells with field effect transistors, for example Memory cells with bipolar transistors into consideration.

In a read / write memory, switches can be implemented for each memory cell in an analogous manner to that described in the first exemplary embodiment. Depending on the memory cell chosen, they can possibly be combined into a common switch with a size of a single cell, as in the previous example. In the example below, a further possibility is applied, wherein the switch on the side of the memory array and between the matrix and the decoder or the scan register 20 (Fig. <?) Are arranged.

The right part of the integrated execution form 11 shows a conventional memory array having cells of the one transistor per bit type. The transistors are field effect transistors with an insulated gate electrode made of polycrystalline silicon and for the storage capacity is the capacity between an isolated polycrystalline electrode and one below it Inversion layer formed in the semiconductor body 60 is used.

The semiconductor body 60 consists, for example, of η-doped silicon and is, for example, on the underside with

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PIIN. 71 86. 9/25/74.

a schematically indicated connection point 61 is provided. At the top there is an insulating layer on the semiconductor surface, the thickness of which between the dash-dotted lines 62 is significantly less than outside these lines; rather an insulating layer, insulated electrodes 63 and 64 made of polycrystalline silicon extend. The electrodes 63 are connected to one another via the conductor 65 at the edge of the matrix. They form the electrodes of the storage capacitors 31 to 3k connected to a point with reference potential (FIG. 9). The conductor 65 is connected to the connection point 61 via the connection point 66 and a voltage source 67, with the electrodes 63 having a negative potential with respect to the semiconductor body which is large enough to enable the point at which the insulating layer is thin, to form a number of mutually separate inversion layers under each of the electrodes 63 in thermal equilibrium. Each of these inversion layers adjoins a p-electrode zone 68 of a field effect transistor on one side in the semiconductor body, the other -p-electrode zone 69 of which is connected to a conductor track 70. Each zone 69- is common to the two adjacent transistors of the memory cells of adjacent parts. An opening 71 is provided in the insulating layer for the connection to the relevant conductor track 70.

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The conductor tracks 70 form column conductors YI, Y2, etc., of the memory _{matrix t} . The gate electrodes 6h of the transistors 68, 6h, 69t, which likewise the row conductors X1, X2, X3, etc., are located perpendicular to them. For the sake of clarity, the separate conductor tracks running in different directions are hatched in different directions in the figure.

In the left part of FIG. 11 it is indicated how the switches 23 to 27 according to FIG. 9 can be integrated, for example. Conductor tracks 72, which form the conductors X1, X2, etc. according to FIG. 1, extend near the left edge of the figure. The conductor tracks 72 are connected via openings 73 in the insulating layer to electrode zones 7 ^ · of the p-type, which are each common to two field effect transistors. The gate electrodes of these transistors are formed by the conductor tracks 75 and 76, which correspond to the drive column conductors 21 and 22 of FIG. At the location of the transistors before these transistors, thin parts of the insulating layer indicated by a dash-dotted line 77 are present. The field effect transistors concerned also have electrode zones 78 which are also common to two transistors. In this case, however, a shift is applied compared to the common zones lh , so that each of the zones lh with the aid of the gate electrode 75 with a first of the

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Zones 78 and can be connected to an adjacent second zone 78 with the aid of the gate electrode 76. Each of the electrode zones 78 is connected to one of the conductor tracks 6h and thus to a row conductor of the memory matrix via a conductive layer 79 and openings 80 in the insulating layer.

The conductive layers 80 and the conductor tracks 72, and 76 may, for example, be made of aluminum or some other suitable Made of metal. The field effect transistors in the left part of the figure are then in a different technology executed as those recorded in the memory matrix Transistors, however, it is also possible to implement the conductor tracks 75 and 76 in polycrystalline silicon and the field effect transistors in the left part with the same self-aligning technology as preferably in the Memory matrix applied to produce.

In the example described, the conductors XO, X1,

X2, etc., connected to an electrode zone Jh and that of the

ι ι

Charging and discharging of the column conductors X1, X2, etc. required Current must flow through these conductors XO, X1 etc. In a modification of this example, the electrode zones are 7 ^ not directly connected and opposite this zone there is still an elongated, p-surface zone extending in the column direction, which with a supply or clock voltage source is connected.

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This surface zone forms one with each of the zones 74 another field effect transistor, its gate electrode is formed by the associated conductor XO, or X1, etc. In this way flow through the above mentioned Charging currents do not affect the decoder or the scan register, but the clock voltage connection. This can be beneficial for speed, for example. Next can for the Field effect transistors that serve as switches 23 to 25, Transistors with a larger ratio of the channel width to the channel length can be easily realized when the channel areas with respect to that shown in FIG Situation is shifted a quarter turn. The switches are then e.g. by -a row next to each other lying surface zones formed, which in turn the Zones 74 and 73 of FIG. 11 correspond. In doing so, extend the gate electrodes are between these zones and parallel to the conductor tracks 64. The ones transverse to these Gate electrodes running drive column conductors can can now be arranged between the switches and the matrix of memory cells. This topology offers the Possibility, in particular, of the channel width of the field effect transistors simply to be placed in the memory matrix ' Adapt speed requirements.

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Claims (1)

PHX ₄ 7186. 9/25/7 ^. -33- 24,743? PATENT KITCHEN : 1, arrangement with at least one memory matrix with memory elements at intersections of rows and columns, with at least one row for at least one memory element belonging to this row and for at least one memory element belonging to a more distant row first and second selection means being provided with which when selecting this row the at least one belonging to this line memory element or at least one belonging to the distant line memory element and further ¹ to a first terminal of the first Vählmittel a drive signal and at a second terminal of the second ¥ the complement of the Anstetiersignals ählmittel be received can be selected as required, characterized in that a drive arrangement is provided in which on the basis of a one-INliREMENT-Cmd Ehls and / or a ^v-step decrement command, the mentioned drive signal can be determined. 2, arrangement according to claim 1, characterized in that said control arrangement is part of a Arithmetic unit and the aforementioned control signal a transmission signal is, 3 «arrangement according to claims 1 and 2, characterized in that the aforementioned memory matrix a 509817/10 43- PHN.71 86th - 3h - 25.9.1h, Fixed storage matrix is in the one with the first selection means one line and the following line can be selected with the second selection means and wherein the control arrangement is formed by a second read-only memory matrix in which one of the columns is a transmission signal column and wherein said first and second memory matrices each with one as an address selector serving scanning register together an add-subtract arithmetic unit form, h, memory matrix for an arrangement according to claim 1, 2 or 3 »characterized in that the first selection means are common to all memory elements belonging to a row and the second selection means are common to all memory elements belonging to a more distant row. 5. Memory matrix for an arrangement according to claim 1, 2 or 3 »characterized in that the first ■ selector means row by line via a common subline conductor with a first control column common to all first selection means and the second selection means row by row via a second common subline conductor with a second Selector means connecting common control column. are, the sub-row conductors with the rows and the drive columns z _; u the columns of the memory matrix run parallel, 6 »memory matrix according to claim h, characterized in that the first selection means with all 509817/1043 PIIN. 71 86. 9/25/74. first ¥ ählmittel common first control column and the second dialing means with one of all ΖΛ ^ βίΐβη dialing means common drive column are connected and the drive columns to the columns of the memory matrix run parallel. 7 »Memory matrix according to one or more of claims h to 6, characterized in that the more distant row is an adjacent (following, preceding) row of the matrix, 8, memory matrix according to one or more of claims 4 to 7 »characterized in that the Matrix is executed in a solid state integration technology. 50981 7/1 (K 3