DE2261786C3 - - Google Patents

Description

The invention relates to a read-only memory unit consisting of semiconductor strips diffused into a semiconductor substrate and address lines or selection lines forming a matrix with the semiconductor strips, with first field effect transistors that are selectively conductive by signals on the address lines and correspondingly stored data 6 "Are arranged at the intersections of address lines and selected pairs of adjoining diffused semiconductor strips and are connected to them.

From US-PS 36 1 I 437 a read-only memory is diffimdicrten into a semiconductor substrate and into Semiconductor strips arranged in a matrix are known in the / to the structure of an eight column having Storage unit twelve such semiconductor strips are required.

The invention is therefore based on a further, ii Fig. 1 shown read-only memory unit, ie conductive semiconductor strips shown by vertical lines in a semiconductor substrate and field-effect transistors denoted by circles has address lines A ₁ to A _ti and selection lines S ₁ to S ₈ form with adjacent semiconductor strips: a matrix. The address lines are shared in several bit positions in separate storage units of the substrate. For the sake of simplicity, only one storage unit is shown. The data are stored at specific addresses of field effect transistors such as the field effect transistor 3, which is between a first semiconductor strip 4 connected to a reference potential (e.g. ground potential) and an adjacent semiconductor strip. 2 are arranged, which has a further field effect transistor, ζ. Β. the field effect transistor 5 is connected to a common output 10 for each semiconductor strip of the respective bit position.

Eight words are selected via each address line, the bits of which are stored in several such memory units. These words are used individually, e.g. B. read successively by signals on the selection lines S ₁ to S ₈ , which drive the transistors 5 into the line. Eight memory units are provided for words having eight bits, the bits of a word being stored in corresponding locations in the eight memory units. The field effect transistors 1 and 5 are in series in the vertical semi-conductor strips, and the horizontal lines through these field effect transistors represent connections to the corresponding control electrodes of the field effect transistors. Each field effect transistor is connected to the two semiconductor strips, and the horizontal lines (A ₁ to A _h ) therefore represent both these connections and the connections to the control electrodes.

In normal operation, only one address signal and one select signal are "true" during a particular memory cycle. Before the addressing the memory unit precharge field effect transistors 1 are turned on by a signal on a precharge to each Halbleiterslreifcn 2 to a potential - to place V and charge at about that potential. The precharge Fcldcffekt transistors are then switched off and the semiconductor strips are addressed by signals which are present on the address lines / I ₁ to A _H. Signals at the selection elements S ₁ to S _n enable a specific semiconductor strip to be connected to the output K). The semiconductor strip must therefore be addressed and selected at the same time so that an output signal occurs.

Do the lines A , and S _{1 have} a "true" potential. so the semiconductor strip 2 is connected via the field effect transistor 3 to ground potential which is applied to the semiconductor strip 4. Since the field effect transistor 5 is conductive. the output is connected to ground. Therefore, even in the presence of z. B. a Fcldcffeki transistor 3 'for another, an address bit / f, corresponding semiconductor strip 2'. without a sign on the selection line 53 corresponding to the other semiconductor strip, no

Output signal occur. Since eight address lines ^ eight selection lines are provided, each read-only memory unit according to FIG. 1 stores one bit for! «Of the word of 8 × 8 = 64 words.
Although the hard disk memory unit shown in FIG. 1 already has an inexpensive memory structure, it has disadvantages insofar as a considerable amount of semiconductor substrate area is required in order to store a large number of words each containing many bits. Since three semiconductor strips (e.g. 2, 4 and 6) are required for two selection columns, twelve semiconductor strips are required in the illustrated memory unit with eight columns. Large numbers of data words each having many bits are z. B. often used to store commands for microprograms.

The object of the invention is therefore to provide the information required for a read-only memory with a high storage density Reduce semiconductor substrate area.

According to the invention, this object is achieved in that the semiconductor strips alternate over second field effect transistors with a reference potential and via third field effect transistors with a common output for the memory unit are connected, the second and third field effect transistors selectively become conductive by signals on the selection lines. Furthermore, the semiconductor strips are through fourth field effect transistors connected to a second potential different from the reference potential and a selection line is connected to two second field effect transistors, the two different semiconductor strips connect to your reference potential, with at least one of the two second field effect Ti ansistors in series with a further second field effect transistor is connected, Her is connected to another selection line.

In addition, there are the address lines and selection lines common to all storage units of a permanent storage unit, and several storage units collectively store an equal number of bits of each word of a number of words.

Advantageously, according to the invention, is therefore only about a semiconductor strip is required to provide addressable storage locations for the respective bit position of a binary word, so that in contrast to the memory unit that requires twelve semiconductor strips according to FIG. 1 now only 9 semiconductor strips for the construction of a read-only memory unit unit with 8 columns are required.

Embodiments of the invention are shown in the drawing and are sewn in the following described. It shows

1 shows a schematic representation of a read-only memory unit the state of the art,

2 shows a schematic representation of the inventive Fixed value spoke purity and

F i si. 3 shows a schematic representation of part of the storage unit according to FIG. 2. ^{6 <)}

Fig. 2 shows a fixed-value memory unit. The eight Rcihenadrcssen. . I. to. I _s , and eight Spalk'iiadresses, S ₁ .,, To .V ₇ . _s has. This results in 64 possible memory locations (addresses). To address a memory location, a spy selection line and a row address line must have a "true" signal. Normally only one row address signal and one column selection signal "true" during a memory cycle. The row address and column select lines are equivalent to the X and Y lines of a memory array. The bit locations can be designated with 1: 1 to 1: 8, as can be seen in the figure for some addresses.

The memory unit consists of P-conductive semiconductor strips 20 to 28 diffused into the semiconductor substrate, which are electrically connected to a potential, e.g. B. -V, and either an output 71 or a reference potential, such as ground potential are connected. According to the invention, P-conducting semiconductor strips, such as, for example, the semiconductor tires 21, 23, 25 and 27, are alternately connected to the output and the remaining P-conducting semiconductor strips 20, 22, 24, 26 and 28 are connected to ground potential.

Of course, the memory unit can alternatively also have diffused N-conductive semiconductor strips have, the use of positive potentials is required. In this case the logical assignment described in connection with the preferred embodiment of the invention will also be changed. Since P-conducting semi-conductor strips were selected here, they are negative Voltage level for controlling the field effect transistors forming the storage locations and Representation of a "true" logical state (logical "1") required. Represent ground potentials a "wrong" logical state (logical "0").

The memory unit also has first field effect transistors 29 to Sl, which are between adjacent P-conductive semiconductor strips are arranged and form the storage locations. The presence or Absence of such a first field effect transistor between the P-conducting semiconductor strips denotes the logical state of the information stored at this particular address. When so there is no first field effect transistor (e.g. at 1: 2 and 8: 1), the stored bit is one logical "1", and if there is a first field effect transistor (e.g. at 1: 1 and 1: 3), that's it stored bit a logical "0". The presence or absence of a first field effect transistor leads to a "false" or "true" output signal when connected to the first field effect transistor corresponding A.dressenleitung and the two selection lines "true" signals or potentials issue.

In addition, second field effect transistors 52 to 61 and 19 are formed in series in the P-type semiconductor strips 20 to 28, in contrast to the first field effect transistors which are formed between the P-type semiconductor strips. The second FeldeiTekt transistors switch the P-conducting semiconductor strips that are to be connected to ground potential or the output. It should be noted that column selection signals for two adjacent P-conducting half-liter strips are "true" during the memory addressing interval. As a result, at least two second field effect Tran sislorcn are conductive during each address cycle. B. one of the storage locations 1: 1 to 8: 1 is selected. The signals .S _s ., and S ₁ .., »are true and the field effect transistors 52, 53 and 54 are conductive during the corresponding memory addressing cycle.

The P-conducting 1 semiconductor strips are input

Charged via fourth field effect transistors 62 to 70 to approximately the potential - V. This v _o rlade interval occurs before a SpeichcradresscnzykUis. The charge is stored due to the self-capacitance of the P-conducting fall arrester strips. Then, depending on the addressing, a semiconductor strip is connected to the reference potential via a second field effect transistor controlled by a signal from a selection line, while the adjacent semiconductor strip is connected to the common output via a field effect transistor controlled by a signal from the adjacent selection line in order to enable reading of the signal representing the data stored in the adjacent semiconductor strip. The selection signals are applied to the selection lines during the entire addressing period, so that the second field effect transistors of the adjacent semiconductor strips conduct simultaneously in order to select the address corresponding to a specific semiconductor strip.

The high storage density of the storage unit according to FIG. 2 compared to the storage unit according to FIG. 1 becomes clear when comparing the two figures. In the memory unit according to FIG. 1, three are diffused in Semiconductor strips 2, 4 and 6 are required for each two NOR elements of a bit position. Will with N denotes the number of selection columns, then is the number of diffused semiconductor strips

yN. On the other hand, in the case of the memory unit 2 only two P-conducting semiconductor strips. e.g. 20 and 21, required for two NOR elements. The number of semiconductors diffused in is thus N-M and therefore corresponds almost exactly to the number N of selection columns. Although NOR members here can be used to build the storage unit. other types of logic can also be used will. When using NOR elements, the output signal is »false« if a signal is present. d. H. the logical state is "true". If there is no signal, i.e. if the logic state is "false", see above the output signal is "true". The terms "true" and "false" become - as already mentioned - used to represent the binary states of a logical "1" and a logical "0".

Since in the memory unit according to FIG. 1 an additional P-conducting semiconductor strip is required to form two NOR elements, a ^{substrate area approximately 1} Zs larger than the memory unit according to the invention according to FIG. 2 is required for the construction of such a read-only memory.

In Fig. 3 the read-only memory unit according to FIG. 2 is shown schematically. Like F i g. 3, the field effect transistor 29 is located between the P-conducting semiconductor strips 20 and 21. A “true” (negative) signal on the address line A j drives the field effect transistor 29 into the line around the semiconductor strips 20 and 21 to connect electrically to each other. The semiconductor strips 21 and 22 continue to be insulated from one another. On the other hand, if the signal A _{2 is} "true", there is no electrical connection between the P-conducting semiconductor strips 20 and 21. In this case, the electrical connection is between the P-conducting semiconductor strips 21 and 22. The fourth field effect transistors 62 and 63 are located in series with the P-conducting semiconductors sUcifcn 20 and 21, respectively, in order to apply each P-conducting omnidirectional strip to the poicnlial - V before a memory addressing cycle, if a "true" Yorladc signal is present . This means that the P-conducting semiconductor strips are brought or precharged to cuis potential Γ. Thereupon the fourth field effect transistors block, and the potential -I 'is stored by the capacitance of the P-lcitcndcn semiconductors.

ίο Furthermore, in F i g. 3, the column selection illustrates UEIC second field effect transistors 52 and 53 for the select lines S and S _{1 H} ,, _4., Are connected in series with the P-type semiconductor region lcitenden 20th If the column selection signals are “true”, then the P-line semiconductor strip 20 is at ground potential. The field effect transistor 54 is connected in series with the P-leilendcn semiconductor strip 21 in order to send an output signal to the corresponding NOR elements, e.g. B. the NOR element belonging to the P-conducting semiconductor strips 20 and 21, when these are addressed.

According to FIG. 2, at the beginning of an operation cycle of the memory, the fourth field-effect transistors 62 to 70 are driven into the line, and each P-lcndc semiconductor strip 20 to 28 is precharged to approximately the potential V. The second field effect transistors 52 and 61 block during the precharge interval. .J of the precharge interval held locked.

After the precharge interval, a specific memory location is addressed by emitting a true signal via one of the address lines, (, to A ^ and a "true" signal via two of the selection lines Sg ₄ , to S _7, j ;. As an example, it is assumed that the signal of the address line A. And the signals of the selection lines. ^., And 5 ,,., Are "true" during the memory cycle. The other signals are false second field effect transistors 52 and 53 are driven into the line so that the P-lcitendc semiconductor strip 20 is connected to ground Semiconductor strips are electrically connected to one another, and the P-conductive semiconductor strip 21 is also discharged via the field effect transistor 29. The field effect transistor 54 "also conducts, so that the output signal is" false ". In other words, because the Field effect transistor 29 lies between the P-conducting semiconductor strips 20 and 21 and conducts, in order to establish a connection between the semiconductor strips, these are discharged to ground potential, and the output signal is "false".

On the other hand, when the field effect transistor 29 is absent. discharges the charge of the P-lcitenden semiconductor strip 21 does not have the field effect transistors 52 and 53 to ground potential.

and the signal at the corresponding NOR element is "false" and the output signal is thus "true".

Of course, the address and select lines extend to other bit locations in further sections of the read-only memory (not shown). The output signal for all bit segments of the added read-only memory is obtained at the same time at corresponding output connections 71. The field effect transistors 52 and 53 and 19

.iur

and 61 form two AND gating arrangements which are required to prevent the P-type semiconductor strips 20 and 28 from being selected at the same time. If z. B. the memory location 8: 1 is selected, the lines / I ₈ , S ₈ ,, and S ,. ₂ at a "true" potential. Since the line A _{s is} at a “true” potential, the field effect transistors 36, 39, 41, 44, 46, 49 and 51 conduct, and if only the field effect transistor 19 were present in the semiconductor strip 28, the output 71 could more erroneous

wise via the field effect transistors 19, 51, 49, 46, 44, 41, 39, 36 and 54 are grounded. This circuit is blocked by the field effect transistor 61, so that the half-strip 28 is only grounded when a "true" potential is present _{on both the line S 8 H} and the line S ₁ , _B. In the same way, the semiconductor strip 20 is only grounded via the field effect transistors 52 and 53 when a "true" potential is present _{on both the line S 8} , and the line S ₁ , _2.

For this purpose 3 sheets of drawings

Claims (4)

Patent claims: 1. Read-only memory unit made of semiconductor strips diffused into a semiconductor substrate and address lines or selection lines forming a matrix with the semiconductor strips, with first field effect transistors that are selectively conductive by signals on the address lines and correspondingly stored data at the intersections of address lines and selected pairs of adjacent diffused semiconductor strips are arranged and connected to them, characterized in that the semiconductor strips (20 to 28) alternately via second field effect transistors (52, 53, 55, 57, 59, 19, 61) with a reference potential and via third field effect transistors (54, 56, 58, 60) are connected to a common output (71) for the memory unit, the second and third field effect transistors being selectively transmitted by signals on the selection lines (S "., to S _7. , ) become conductive. 2. Read-only memory unit according to claim 1, characterized in that the semiconductor strips (20 to 28) are connected by fourth field effect transistors (62 to 70) to a second potential (■ - V) different from the reference potential. 3. Read-only memory unit according to claims 1 and 2, characterized in that a selection line (S _s ,,) is connected to two second field effect transistors (52 and 19), the two different semiconductor strips (20 and 28 ) connect to the reference potential, and that at least one of the two second FeIdeffek transistors (52 or 19) is connected in series with a further second field effect transistor (53 or 61), which is connected to another selection line (S ₁₄₂ or S _7. ^) Is connected. 4. Read-only memory unit according to claims 1 to 3, characterized in that the address lines (Λ 1 to A 8) and selection lines (S _8. , To S _{7 + 8} ) are common to all memory units of a read-only memory and several memory units together are the same Number of bits of each word.-Incr Store the number of words.