DE2544434A1 - Rapid switching LSI circuitry - has clock pulses to consecutive FET stages mutually inverse for binary signal processing - Google Patents

Abstract

Binary processing LSI circuitry consists of stages each of which has a load FET in series with connecting and active FETs and is controlled by a separate clock pulse. One main terminal of the load FET is connected to a capacitor, and is the stage output, connected to the input of at least one other stage. To speed signal processing the clock pulses to consecutive stages should be mutually inverse, consecutive stages (3, 4) have linking FET (T2, T3, T6, T7) of different conduction type from the load transistors (T4, T5). The wall transistors are connected alternately to the voltage source terminals.

Description

"Integrated circuit in dynamic CMOS technologyU

The invention relates to an integrated circuit with MOS transistors for processing binary signals with at least two stages, each of which from the series connection of a charging transistor of one conductivity type as well as one or more linking transistors connected in series and / or in parallel with one another and an activation transistor of the other conductivity type between the poles a voltage source, the control terminal of the charging transistor and of the activation transistor is connected to the same clock line and that of the Pole facing away from the main terminal of the charging transistor is connected to a capacitance and represents the output of the stage and the output of a stage with the input at least one other stage is connected and successive stages with different clock lines is connected.

Such a circuit is known from DT-OS 2 316 619, and this structure is called dynamic CMOS technology.

At one level of the clock signal, the charging transistor is switched on, which then charges the capacitance almost to the voltage of the pole to which the Charging transistor is connected.

During this time, the activation transistor is blocked. With the other At the level of the clock signal, the charging transistor is blocked and the activation transistor conductive, so that now the link transistors are effective and, depending on the signals applied to the logic transistors discharge the capacitance again can.

This technology combines the advantages of dynamic MOS technology, which has a simple and very space-saving structure, with the advantages of complementary technology that only consumes low power and high switching speeds can achieve. When connecting several stages in series, however, it is disadvantageous that that an input signal cannot be processed at the moment it is is supplied by the previous stage, but only with the next clock signal, so that there is inevitably a considerable delay in running through several stages Signal occurs.

The object of the invention is to provide an integrated circuit of the initially mentioned specified type in CMOS technology to indicate that a higher signal processing speed enables. This object is according to the invention by those specified in the main claim characteristics solved. With such a circuit it is possible that an input signal passes through all successive stages in a clock phase. The clock signals fed to the successive stages are useful here inversely to each other.

Further refinements of the invention are set out in the subclaims marked.

Embodiments of the invention are described below with reference to the drawing explained. FIG. 1 shows two successive stages with logic transistors different conductivity types, Figure 2 is a timing diagram to explain the Function of the stages according to FIG. 1, FIG. 3 successive multiple stages init downstream inverters as a buffer, Figure 4 is a diagram for explanation the function of the circuit according to Figure 3, Figure 5 is the block diagram of a programmable logical arrangement, Figure 6 shows the more precise structure of the arrangement according to Figure 5, Figure 7 shows an arrangement for counting and for generating control signals for a display, figure 8 shows the arrangement of some transistors of the circuit according to FIG. 3 or 6 on one Semiconductor wafer.

In Figure 1, two interconnected stages 3 and 4 are shown, in which the link transistors are of different conductivity types. The substrate connection of N-channel transistors with the negative pole is the Supply voltage and the substrate connection of P-channel transistors with the positive Pole of the supply voltage connected. Stage 3 contains a charging transistor T4, which in this example is an N-channel transistor and its one main connection is connected to one pole 1 of a voltage source, the voltage of which is here as OV is designated. The other main terminal of the charging transistor T4 is connected to a Capacitance Cl, which is usually formed by a parasitic capacitance, with the output D1 of stage 3 and a main connection of a first logic transistor T3 connected. This is just like the second link transistor connected in series with it T2 and the activation transistor T7 a P-channel transistor. The other main line of the activation transistor T1 is connected to the other pole 2 of the voltage source, whose voltage is denoted by + U. However, it would also be without changing the function and the structure possible, the voltage of this pole 2 with OV and the voltage of the Designate pole 1 with -U. It is also possible to change the conductivity type of all Reverse transistors if likewise the polarity of the voltage source is reversed will. It is also possible, compared to the circuit shown in FIG Order of the activation transistor T1 and the link transistors T2 and T3 to be swapped without changing the function of the circuit. These possibilities all also apply to the exemplary embodiments described below.

The function of stage 3 in Figure 1 should be based on the timing diagram are explained in more detail in FIG. In the time segment t1, the clock signal #l has the clock line denoted by the same reference number, the one with the control connections of the transistors T1 and T4 is connected, a high potential, as can be seen from FIG.

This switches off the activation transistor T1 and the charging transistor T4 switched on at the same time. The latter now charges the capacity Cl to OV, and this voltage is then also at the output Di, as shown in FIG. Included it does not matter which voltages are applied to the control connections via the control inputs Al and BI the linking transistors T2 and T3 are supplied as the activation transistor T1 is blocked anyway and no current flow is possible. For further description however, it is assumed that a low voltage at the control input B1 and a low voltage at the control input Al the voltage curve shown in Figure 2 are present.

In the time segment T2, the clock signal §1 is negative, as shown in FIG. 2 emerges, so that now the charging transistor T4 is blocked and the activation transistor Tl is conductive. However, the capacitance C1 cannot be discharged because it is at the control input Al another positive Signal is present that the link transistor T2 locks.

In the time period t), the clock signal # 1 is positive again, so that the Charging transistor T4 is switched on again. Since the capacitance C1 in the meantime has not been reloaded, nothing changes to the cargo. However may during this time period, the signal at the control input Al will be negative, as in Figure 2 is shown.

If the clock signal #l becomes negative again in the time segment t4, are now both link transistors T2 and T3 and the activation transistor T1 conductive, so that the capacitance C1 is now charged to the voltage + U of pole 2 becomes, # and the output D1 has a positive voltage at @, as shown in FIG is. In the time segment t5, the capacitance Cl is again due to the charging transistor T4 Reloaded to OV, which results in the corresponding voltage at output D1. In the time segment t6, the same process is repeated as in the time segment t4. In the time segment t7, the voltage at the control input Al is again high, so that im following the same states as in the time segments t1 and t2 alternately appear.

If now a level like level 3 is built up at output D1 Was connected, which would be operated with the character clock signal, results the following problem: At the beginning of the time segment t4, the voltage is at the output D1 initially still negative, since the capacity C1 from this time segment is only reloaded to + U via the transistors T1 to T3. In a subsequent Stage, which is structured like stage 3, is caused by the initial low voltage The corresponding logic transistor is initially switched on and at output D1 so that the capacity connected to the output of this next stage is initially discharged, until the voltage at output D1 has risen so far that the connected Linking transistor no longer conducts. The capacity in the following stage would be then at least partially reloaded, although according to the logical state at the exit D1 at the end of the time period t4 no transfer should have taken place, so that the the following stage would emit a false logical signal. Therefore, the from DT-OS 2 316 619 known arrangement successive stages with one another offset clock signals fed to avoid this error, thereby reducing the logical Signal needs a longer time to get to the output of the last stage.

In the arrangement shown in Figure 1, the differs Stage 4 connected to stage 3 in that the link transistors T6 and T7 are of the opposite conductivity type, as are the link transistors T2 and T3, but this also causes the transistors T5 and T8 to swap their function, d. H. the charging transistor is the P-channel transistor T5, one of which is the main connection with the pole 2 and its other main connection with the output D2 and the capacitance C2 and is connected to the main terminal of a logic transistor T6. The activation transistor, on the other hand, is the N-channel transistor T8. If now the charging transistor T5 and the activation transistor T8 are fed with a clock signal Q2 that is inverse to that of the previous stage 3, as shown in Figure 2, can an input signal at the control input Al to within a clock period Run through output D2.

First, the clock signal P2 is low in the time segment t1, so that the activation transistor T8 of stage 4 is blocked and the charging transistor T5 is switched on is and the capacitance C2 charges to the voltage + U of the pole 2, so that the output D2 assumes the corresponding voltage, as shown in FIG. The period of time So t1 is just like the following time segments t3, t5 ....... for both stages 3 and 4 the charging phase.

In the time segment t2, the key signal H2 is positive, so that the activation transistor T8 is conductive, and the voltage at control input A2 is positive, so that the Linking transistor T6 is conductive, but the output D1 and the one with it connected control input B2 negative, so that the logic transistor T7 blocked is. The capacitance C2 is therefore not recharged, the voltage at the output D2 remains unchanged, as shown in FIG.

During the next charging phase in time segment t3, this therefore results no change at the output. Only in the following time segment t4 will the Voltage at control input B2 positive with a certain delay, so that with a corresponding delay of the linking transistor T7 now also conductive and accordingly the capacitance C2 is discharged with a delay to OV, so that the voltage drops at output D2 with a delay, as shown in FIG. The signal at the control input Al is therefore within a single clock phase within the time segment t4 walked through to exit DZ. No difficulties can arise here, because the capacitance C1 initially charged to OV blocks the link transistor T7 and makes stage 4 inactive initially, so that capacitance C2 is not erroneously can be reloaded.

The input of another can now be connected to output D2 of stage 4 Stage can be connected, which is structured like stage 3 and through the same Clock signal is controlled, and in this way a whole chain of stages can be created be arranged in which the conductivity of the link transistors and the The function of the charging transistor and the activation transistor changes from stage to stage and the maximum number of stages connected in series is only determined by the Sum of the delay times of the individual stages is limited.

In Figure 2 is also shown how the signal on exit D2 behaves in the next time segments. In the time segment t5, the capacity C2 is charged again to the voltage + U by the charging transistor T5, which is then switched on and the voltage at control input A2 drops to OV. Received in time period t6 the control input B2 now has a positive signal, but the low Signal at the control input A2 of the logic transistor T6 blocked, so that the capacitance C2 cannot be discharged and the voltage at output D2 therefore remains positive.

In Figure 1, the logic transistors of both stages are 3 and 4 each connected in series. Instead, one or both stages can also be used the linking transistors must be connected in parallel, i.e. all of their main terminals are with the corresponding main connection of the charging transistor or the activation transistor connected so that with the same assignment of the input signals the corresponding other linking function results. It is also possible to use the logical connection from a combination of series and parallel connection. Furthermore can a plurality of similarly structured stages can also be arranged in parallel, with each stage processes a different combination of input signals. Such a one The arrangement is shown in FIG. In it are the elements and signals that give them correspond to Figure 1, denoted by the same reference numerals.

In stage 5, the logic transistors T2 and T3 consist of P-channel transistors that are again connected in series and their control connections connected to input conductors I1 and I2. The one main connection of the series connection the link transistor is connected to the activation transXstor Tl, and other main connection is possibly via the series connection of further, not Linking transistors shown, which are connected to other input conductors are connected to the charging transistor T4. At the connection point of the series connection of the linking transistors with the charging transistor is the capacitance Cl as well as the Output D1 connected. Further series connections of linking transistors are indicated by the transistor T12, one terminal of which is also connected to the Activation transistor T1 is connected, so for all linkage levels of the Level 5 is common. The other ends of the series connections lead to each its own charging transistor, of which the transistor T14 is shown in Fig. 3bea ## is to which the further capacitance C11 and the output D11 are connected. Any series connection of linking transistors with different combinations of input conductors II, I2 etc. is connected, thus results in an output. In the same way as in figure 1 the one main connection of the activation transistor T1 is connected to the pole 2, and the charging transistors T4, T14 etc. are connected to pole 1 of a voltage source connected, and the control connections of these transistors receive the clock signal b1.

Stage 5 outputs feed a set of input lines of stage 6, in which the logic transistors consist of N-channel transistors and are connected in parallel in groups. One of these groups is through the Transistors T16 and T26 indicated, their control connections with different input lines are connected. The one main connections of these linking transistors as well all others in this stage share a common activation transistor T8 connected, which is connected to pole 1 and its control connection receives the clock signal P2.

The other main connections of the linking transistors T16 and T26, to which further transistors, not shown, can be connected in parallel can, are together with a charging transistor T15, a capacitor C12 and the Output Q1 connected. Also the other groups of link transistors that may be indicated by the transistor T36, are each common with one Charging transistor, a capacitance and an output connected, of which hir is only for example the transistor T25, the capacitance C22 and the output Q2 are shown. The charging transistors T15, T25, etc.

are again P-channel transistors, which are connected to pole 2 of a voltage w ll be connected. The signals at each of the outputs Ql, Q2 etc.

each correspond to a function that is differentiated by each AND link and subsequent OR link of the signals on the input conductors I1, I2 etc. is given.

For complex interconnections of different W4D and OR link levels it is often necessary that the output signals are stored in buffers, before they can be further processed. Such a buffer or a sequence of two buffers is created by the stages shown in FIG 7 and 8 formed. Stage 7 consists of a series connection of two N-channel transistors T41 and T42 and two P-channel transistors T43 and T44. The control connections of the the two middle transistors T42 and T43 are connected to the output Q2 the connected to the previous stage, and the junction point of these two transistors is connected to a capacitance C41 and the output Q3. The transistors T41 and T44 receive clock signals Q1 and §2 in phase opposition to one another, which are the same Are clock signals as in the previous stages 5 and 6. Level 7 works thus as a clock-controlled inverter, the transistors T42 and T43 being the actual Represent inverter transistors. Only when the clock signal §1 is low and the clock signal §2 is high, the inverter transistors are effective and charge the capacitance C41 a signal voltage corresponding to the inverted input signal, and this The signal then appears at output Q3. When the clock signals §1 and b2 are opposite Assuming values, the transistors T41 and T44 are blocked and no charge reversal is possible of the capacitance C41, so that the signal at the output Q3 is retained.

Another stage 8 is connected to this output, the same Way as stage 7 is constructed, with the clock-controlled transistors T45 and T48, however, are controlled by other clock signals, namely in the illustrated Example of the opposite clock signals as in stage 7. The function the circuit according to FIG. 5 will be explained with reference to FIG again the timing of the clock signal al illustrated, and the clock signal # 2 is inverse to this. In the time segment t1 in which the clock signal #l is high, the capacitances C1 and C11 are then switched on by the charging transistors T4 and T14 are charged to OV, so that, among other things, output DA has a low signal leads. In the time segment t2, the activation transistor T1 is through the low Clock signal Q1 and the linking transistor T2 by the low signal on the Input line I1 conducting, but the signal on input line 12 is still high and blocks the linking transistor T3, so that the capacitance CI is not reloaded and the signal at output D1 remains low. Takes place in time segment t3 therefore no change in the charge of the capacitance C1 or the paleung at the output D1. The signal on input line 12 is also negative only in time segment t4 (where possibly

further linking transistors lying in series are assumed to be conductive are), so that now the capacity Cl is reloaded and the voltage at the output D1 assumes a high value, as shown in FIG. The one at this exit connected link transistor T36 in the following stage 6 is thereby conductive, and since the clock signal 22 is high in this time segment t4, is also the activation transistor T8 of stage 6 conductive, and the capacitance C22, which is at least in the previous time segment t3 through the charging transistor T25 to the voltage sU was charged, it is now transferred to OV, so that the in The voltage curve shown in FIG. 4 arises.

In this time segment t4, however, the transistors are also in stage 7 T41 and T44 made conductive by the appropriate clock signals so that the low Signal at output Q2 now a high signal at the output due to the charge reversal of the capacitance C41 Q3 of the inverter stage 7 is generated. Through the hatching in the temporal representation of the signal at the output Q3 in Figure 4, the time segments are shown in which the inverter stage 7 is active.

In the time segment t4, on the other hand, the inverter stage 8 is inactive, since the transistors T45 and T48 are blocked, so that the voltage at the output Q4 this stage does not change.

In the next time segment t5, all charging transistors in stages 5 and 6 are turned off such as, among other things, the transistors T4 and T25 switched on, so that the corresponding Capacities are discharged and the voltages at the outputs Dl and Q2 on their return to the previous value, as shown in Figure 4, but in the Inverter stage 7, the transistors T41 and T44 blocked, so that the capacitance C41 cannot be reloaded and the voltage at output Q3 of this stage is constant remain. In contrast, the transistors T45 and T48 of the inverter stage 8 are switched on, so that now the signal at output Q3 is inverted after the capacitor C42 has been recharged Output Q4 of inverter stage 8 appears.

In time segment t6, a high signal appears again at output D1 and a low signal on output Q2, which in turn is a high Signal at the output Q3 of the inverter stage 7 is generated. Since the capacity C41 is still was charged to this signal voltage, there is no change in the output signal, as shown in FIG.

In the time segment t7, the same processes result as in the time segment t5, the signal at input 11 also becoming positive again, which however does not yet affect one of the outputs. It is only in the time segment t8 the logic transistor T2 locked in the stage, so that the signal at the output D1 remains low, and so the signal at output Q2 again retains its high Value. However, since the inverter 7 becomes active again in this time period, through the high signal at output Q2 discharges the capacitance C41 to 0V, and the signal at output Q3 again assumes a low value. Since the inverter stage 8 in this Zeitsohnitt is inactive, however, the signal at its output Q4 remains low. The inverter stage 8 only becomes active again in the time segment t9 and takes over this Signal at output Q3 of the previous inverter stage, so that output Q4 has a high signal again. In this way, the signal is at output Q2 by two clock phases, d. H. delayed by an entire valley period. The output Q4 could thus connected to one of the inputs II ...... to create a sequential circuit to be generated, because in the time segment t8, in which the input signals are processed, the signal is still present at this output Q4.

From Figure 4 it can be seen that in the odd time segments t3, t5, t7, ..... the output Q2 is always positive, so that the inverter transistor T43 of inverter stage 7 is then always blocked. Therefore, the transistor T44, which should block the inverter in these time periods, and the transistor T43 must be connected directly to pole 2 of the voltage source. The transistor T44 is therefore the one corresponding to the charging transistors of the immediately preceding stage 6 Transistor. So if the inverter stage 7 is built on a corresponding to the stage 5 Stage connected asare, in such a case the transistor T41 be saved. Of course, this is not the case with inverter stage 8, all 4 transistors T45 to T48 are necessary here.

The arrangement according to Figure 3 can be beneficial for the construction of a programmable logical arrangement can be used, which is shown as a block diagram in FIG is. The programmable logical arrangement PLA shown therein is based on your known principle, in particular complex logic combinations of many input signals too many output signals not directly by means of appropriately constructed gates, but to build in the sense of a read-only memory in which the combinations of Input signals represent the addresses and the content of the addressed memory cells is chosen so that the outputs correspond to the input combinations Signals appear. Such read-only memories can be easily integrated because they contain regular structures. In the case of the one shown in FIG The signal combinations on the inputs are programmable logical arrangement Q51, Q52 and Q54, for example, are shown for a larger number of inputs are decoded in the decoder 5, whereby only the signal combinations are decoded, which actually occur to the smallest possible number of outputs D61, D62 etc. of the decoder that control the actual memory matrix 6. The decoder is constructed in accordance with stage 5 in FIG. 3, and the matrix corresponds of stage 6 in FIG. 3. The outputs Q61, Q62 etc. of the matrix and that of the programmable Logical arrangement PLA lead to a memory 9, which consists of a number of inverter stages can be constructed according to stages 7 and 8 in FIG. From the exits Q51, Q53, Q53, which are only shown as examples for a larger number of outputs are, the former are with the inputs of the programmable logic array PLA, d. H. connected to the inputs of the decoder. Depending on the application, i. H. depending on the number of inputs and outputs, all outputs can be connected to inputs be connected. Furthermore, there are further inputs of the decoder in Figure 5, of which the input Q54 is shown, for example, those not with the memory 9 are connected, but are controlled from the outside. By signals on this With the same signal combinations on the input lines Q51 and Q52 different ones of the outputs D61, D62 etc. are energized and thus different areas selected from the matrix.

The more precise structure of the programmable logic arrangement with feedback is shown in FIG. The decoder goes through stage 5 with the AND gates effective series connections of P # channel linking transistors T62, T63 ....

educated. In each series connection shown, additional ones can be used ~ not shown linking transistors be arranged by corresponding additional inputs can be controlled. The one end of all series connections is driven by the common activation transistor T1, and the other end is connected to the charging transistors T64 ...... and the outputs D61, D62 ....., the capacities at the outputs are no longer shown for the sake of simplicity are. The matrix controlled by these outputs consists of level 6 with groups of parallel connections of N-channel combination transistors T66, T67, T68, where Further linking transistors can be connected in parallel in each group, which can be controlled by further outputs of level 5. The one connection all groups are connected to the activation transistor T8, while the others Connections with charging transistors T65 ....... and the outputs Q6l, Q62 ..... connected are. Here, too, the capacities at the outputs are no longer shown.

The outputs Q61, Q62 ..... have a first inverter stage 7 from a number of clock-controlled inverters from the series connection of two each N-channel transistors T41 and T42 and a P-channel transistor T43 connected. This Structure corresponds to that of Stage 7 in Figure 3; being the transistor T44 is omitted.

Also the structure of the previous levels 5 and 6 as well as the following Stage 8 and its control with clock signals corresponds to the circuit according to FIG 3. At the outputs Q63, Q64 .....

is the second inverter stage 8 from a number of clock-controlled inverters connected, each consisting of the transistors T45 to T48. The outputs Q51 and Q52 of this second inverter stage are connected to the inputs of the decoding stage 5 as well as connected to the control input of a non-clocked inverter stage 10, the series connection of an N-channel transistor T49 and a P-channel transistor 50 exist between the poles of the supply voltage and the inverted signal via the outputs Q51, Q52 ..... also to the decoding stage 5 to generate a allow full decoding.

In Figure 7 is the use of a programmable logic arrangement with winding coupling for a decirial counter with simultaneous decoding for the Control of a 7-segment display shown in a simplified manner. Both Levels 5 and 6 are the activation transistors, the charging transistors and the KaTrazities completely omitted and the linking transistors only by an oblique line at the crossing points of input row lines and output column lines indicated on which a link transistor in series in the output line is arranged and with its control connection to the relevant input line connected. In the same way, in levels 6 and 6 ' each link transistor by an oblique line at the crossing point of the input column line, to which the control terminal of this link transistor is connected, and the Row output line with which the relevant logic transistors are connected in parallel are connected, indicated. The outputs of stage 6 lead to a buffer 9, whose outputs QW to Qz represent the output of the decimal counter in binary code and connected to the inputs of stage 5 and inverters 10 at the same time that control the other inputs. In each column of level 5 there is one Decimal number assigned to binary number, which is indicated at the very bottom on the column lines is, decoded, and stage 6 generates the code for the next following binary number respectively.

Decimal number. This next binary number is stored in the buffer 9 is returned to the input of stage 5 delayed by one clock period and decoded again, whereby the level 6 then the code for the following binary number generated, etc.

The decimal numbers that are already present in this way are used in stage 6 'to control the signals for a 7-segment digit display to create. Because the counter works with dynamic technology and therefore every state can only be sustained for fractions of a second, the output signals of the Level 6 by a signal on the St. at the to be displayed Counter setting taken over in a static register 11 to a stationary display to create.

In this way it is programmable by means of a feedback loop logical arrangement a ten counter with display decoding with minimal effort specified.

FIG. 8 shows a section of the semiconductor wafer in which the Circuit arrangement according to Figure 6 in a conventional manufacturing process for complementary Integrated NOS technology using polycrystalline silicon as the gate electrode is. The inputs Q51, Q51, ... of the decoder are used as aluminum tracks 20, 21 guided via the AND level according to level 5. Strip-shaped ones run perpendicular to it Diffusion regions 22, 23 with P-doping, which during production by a corresponding strip-shaped diffusion mask are generated after the gate electrodes 24, 25, 26 made of polycrystalline silicon were attached, so that the diffusion areas are interrupted at the points where the gate electrodes are attached. By the interruption is formed by a link transistor, while the diffusion regions form the connections of the linking transistors in the form of a series circuit. The gate electrodes are connected to the aluminum tracks 20, 21 via contact windows 27, 28 tied together. The position of the gate electrodes 24, 25, 26 creates the logical structure, i.e. the logic function of the AND level is defined.

The ends Doi, D62 of the diffusion regions 22, 23 of the AND plane are connected to the input lines of the OR level according to stage 6 in Figure 6, which are guided over this plane on tracks 30, 31, 32 made of polycrystalline silicon will.

These tracks form the gate electrodes of the link transistors this level. The link transistors can only be generated at that point on which the gate electrodes 30, 31, 32 and the aluminum tracks 33, 34 cross. The one main connection of the linking transistors is each through the diffusion regions 40 formed, which are common to the activation transistor T8 in Figure 6 are connected. The other main connection of the link transistors is formed by diffusion regions 37, 38, 39 when this diffusion region is up to reaches up to the corresponding gate electrode. Otherwise, as shown in the Example is the case with the diffusion region 39 on the right side, arises no link transistor. Through the remaining link transistors will the logical structure, i.e. the logic function of this OR level determines. The individual diffusion regions 37, 38, 39 are connected via contact windows 35, 36 connected to the aluminum paths 33, 34, thus making a parallel connection of all logic transistors one line. The diffusion regions 40 and 37, 38, 39 have the same doping and after attaching the gate electrodes 30, 31, 32 through a diffusion mask generated whose contour 41 by the dashed lines and those connecting them strongly drawn lines is indicated.

PATENT CLAIMS: Blank page

Claims (8)

Claims: 1. Integrated circuit with MOS transistors for Processing of binary signals with at least two stages, each of which consists of the series connection of a charging transistor of one conductivity type and one or several linking transistors connected in series and / or in parallel and an activation transistor of the other conductivity type between the poles a voltage source, the control terminal of the charging transistor and of the activation transistor is connected to the same clock line and that of Pole connected main terminal of the charging transistor connected to a capacitance and represents the output of the stage and the output of a stage with the input at least one other stage is connected and successive stages with different clock lines are connected, characterized in that in successive Stages (3,4) the linking transistors (T2, T3, T5, T7) of different Conductivity type and the charging transistor (T4, T5) alternately rit one of the both poles (1,2) of the voltage source is connected. 2.) Integrated circuit according to claim 1, characterized in that that the clock signals of the clock lines (#i, 2) also of successive linking stages (3,4) are inverse to one another. 3.) Integrated circuit according to claim 1 or 2, characterized in that that the output (Q1, Q2) of the last stage (6) of a series of stages (5,6) with the input of a memory circuit (7,8) is connected to the output signal of the last stage at the latest with the end of the clock signal (ç2) that takes over the Charging transistor (T15, T25) of the last stage blocks. 4.) Integrated circuit according to claim 3, characterized in that that the memory is a first clock-controlled inverter (7), which the series circuit each of two series-connected transistors (T41 to T44) different Conductivity stye between the poles (1,2) of the voltage source contains, the Control connections of the two middle inverter transistors (T42, T43) the output signal of the immediate previous stage (6) and the connection both inverter transistors with a capacitance # (C41) is connected and the output (Q3) of the inverter, and the control connections of the with the poles (1,2) of the Voltage source connected control transistors (T41, T44) with different clock lines (# 1, # 2) are connected, which carry such clock signals that they are the control transistors block and make the inverter inactive as soon as the charging transistor (T15, T25) of the immediately preceding stage becomes conductive. 5.) Integrated circuit according to claim 4, characterized in that that the first clock-controlled inverter (7) a second; same structure Inverter (8) is connected downstream, and that the two inverters with clock lines (41, §2) are connected, which carry such clock signals that the inverters to different Times are active. 6.) Integrated circuit according to claim 4 or 5, characterized in that that the directly connected to the last stage (6) inverter (7) only the two middle transistors (T42, T43) and the activation transistor (T8) of these last stage corresponding transistor (T41) and the corresponding the middle transistors (T43> directly with the corresponding pole (2) of the coil voltage connected is. 7.) Integrated circuit according to claim 4 or one of the following, characterized in that the with the inverter (7) or with the inverters (7,8) connected clock lines ~ (# 1, 2) those with the previous linkage stages (5,6) are connected clock lines. 8.) Integrated circuit according to claim 1 or one of the following, characterized in that several mutually similar stages (5,6) with Linking transistors (T62, T63, T66, T 67) each have the same conductivity type are available and the AI # tiviefl # ngstransistor (T1, T8) for at least several these stages is common. 4 9.) Arrangement according to claim 1 or one of the following, characterized characterized that to form a programmable logic arrangement (PLA) a number of lower in other similar first stages (5), each in series Switched link transistors (T62, T63) of the same conductivity type are present whose control connections are connected to a common set of input conductors (Q51, Q52) are connected that each output (DS ?, D62) of the first stages (5) only at an output signal for a specific combination of signals on the input conductors produces that a number of mutually similar second stages (6) are present in which the logic transistors (T66, T67) are each connected in parallel and are of the opposite conductivity type as in the first stages, their control connections with the outputs (d61, D62) of various first stages (5) are connected, and that the outputs (Q61, QS2) of the second stage (6) are the outputs the programmable logic arrangement (PLA). 1O.) Integrated circuit according to claim 9, characterized in that that the outputs (Q61, Q62) of the programmable logic arrangement (PLA) over Intermediate storage (9) connected to at least part of the input conductors (Q51, Q52) are.