JPS62271297A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make access to an address obtained by adding and subtracting the number of the various addresses according to a control signal with respect to the original address outputted by a circuit by connecting selecting circuits consisting of MOS transistor groups respectively to the output terminals of a decoder circuit. CONSTITUTION:In the decoder circuit 2, one output terminal of the plural output terminals O-1-O-n is selected by input signals (I-1)-(I-l). If the k-th output terminal O-k is selected, one of four word lines 1-k-1, 1-k, 1-k+1, 1-k+2 is brought into an active state through the selector circuit 6-k connected to the output terminal O-k. The control signals P-1, P+0, P+1, P+2 control it and only one of the four signals goes to 'H', thereby, one of the four transistors 6-k, 1-6-k, 4 is conductive and any one of the addresses of the values obtained by adding -1, 0, +1, +2 to the original address designated by the decoder circuit 2 is designated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device comprising a semiconductor integrated circuit device.

[Conventional technology]

A conventional semiconductor memory device of this type will be explained with reference to FIG.

FIG. 2 shows an example of a conventional memory device of, for example, m bits×n words. In the figure, word lines 1-1 to 1-n are connected to an address decoder 2, and each word line has m
memory cells 3 are connected. Therefore, the memory cell is m
It is a storage device containing xn pieces. Among these memory cells, the memory cell group connected to the word line 1-1 is designated as address 1, and the memory cells constituting each bit of this address 1 are designated as 3-1.
゜1.3-1.2,...,3-1. Number it m.

Hereinafter, the memory cell groups connected to word lines 1-2, 1-3, . . . , l-n are located at addresses 2, 3, .
The memory cells of each memory cell group are also numbered in the same manner as the case of address 1 above. For example, each memory cell of each memory cell group with an address is 3-, 1.3-, and 2.3-k.

3,..., 3-, m. Memory cells for each same bit in each memory cell group are connected to common bit/node lines 4-1 to 4-m. The bit line is connected to an input/output buffer circuit 5, and data is exchanged with other circuits such as an ALU (not shown) via this buffer circuit 5.

Next, the operation will be explained.

In the m-bit x n-word random access storage device configured in this way, the stored data is read out via the address decoder 2, and the data in the storage cell group at the address specified by the address signal applied to the storage device is read out. is output to the output sofa via common bit lines 4-1 to 4-m. In addition, the write data is also the same for each address.
? 14 1 to 4-m.

[Problem that the invention seeks to solve]

In a semiconductor integrated circuit equipped with a semiconductor memory circuit configured as described above, when reading or writing stored data, the address to be accessed is specified by the decoder circuit, but at this time, only when a certain control signal becomes a specific value There are cases where you want to access an address that is the result of adding or subtracting a certain number from the address. At this time, in the conventional semiconductor memory circuit, it is necessary to provide an adder/subtractor before the decoder circuit, resulting in a complicated circuit and a large chip area.

This invention was made to solve the above-mentioned problems, and only when the control signal reaches a specific value, a fixed number is sent to the original address specified address without the need to provide an adder/subtracter in front of the decoder circuit. An object of the present invention is to obtain a semiconductor memory circuit that can access an address of a value obtained by adding or subtracting .

[Means for solving problems]

In the semiconductor memory device according to the present invention, the source and drain terminals of a plurality of MOS transistors are connected to each decoder output terminal, and the source and drain terminals of each of the other MOS transistors are connected to each decoder output terminal.

Connect the drain terminal to the word line and connect it to the gate electrode? 1
'll signal is connected, and each decoder output terminal connects multiple M
This allows branching to any one of a plurality of word lines via an OS transistor.

[Effect]

In this invention, a MOS transistor provided between the output terminal of the decoder circuit and each of the plurality of word lines allows the output terminal of the decoder circuit and the address specified by the MOS transistor to output a certain number of addresses indicated by the control signal. Connect it to the word line that specifies the address that has been added or subtracted.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention. This device is an example of a memory device with an m-bit x n-word configuration, and the original address output from the decoder circuit is determined by four control signals. , it is possible to move to an address that has been subjected to three types of additions and subtractions. In the figure, word lines 1-1 to l
-n is connected to the decoder circuit 2 via selector circuits (selection circuits) 6-1 to G-n, and a memory cell group consisting of m memory cells 3 is connected to each word line. Reference numeral 7 denotes an n-type depletion type transistor for pull-off. Of this memory cell group, the memory cell group connected to the word line 1-1 is designated as address 1, and the memory cells constituting each bit of this address 1 are designated as 3-1.1.3-1.2, . . . ,
3-1. Number it m. Below word line 1-2.1-3,
. . , 1-n, respectively, are designated as addresses 2, 3, . Each memory cell of the same bit in the memory cell group at each address is connected to a common bit line 4-1 to 74-m. Selector circuit 6-
1 to 6-n are each four n-type enhancement type MOs.
For example, the k-th selector 6- has MOS transistors 6-, l, 6-, 2
．． 6-, 3.6-, and 4, each source or drain terminal is connected to the output terminal ○-k of the decoder circuit 2, and the drain or source terminal is connected to -1, k, and 4, respectively.
-1, 1 to word line 1-, which specifies +l and +2 addresses.
-k, 1- is connected to +1. 1- is connected to +2. However, in each selection circuit, the own address is -1, O, +1. +
The address to be selected by adding 2 is n
It is assumed that the next address is the 1st address, and for example, the drain or source terminal of the n-th selector 6-n is connected to the word line 1-1, which specifies addresses n-1, n, and 1.2, respectively.
Connected to n-1, 1-n, 1-1.1-2.

Also, gate 1 of each of the four MOS transistors constituting each selector circuit! The poles are control signals P-1 and p+, respectively.
o, p+1, and P+2 are connected.

Next, the operation will be explained. In FIG. 1, in the decoder circuit 2, one output terminal among a plurality of output terminals 0-1 to O-n is selected by input signals T-1 to I-1.

If 'lJ< is selected for the output terminal 0-, then -1, 1-k, -1, 1-k, and One of 1-+1 and 1-+2 becomes active.

Control signals P-1, p+o, P+1,
P+2, and only one of the four signals is “
By becoming H5, one of the four transistors 6-, 1 to 6-, becomes conductive, and - to the original address k specified by the decoder circuit 2.
1, O, +1. One of the addresses of the value obtained by adding +2 will be specified. The contents of the memory cell group connected to that word line are read and written to bits vA4-1 to vA4-m via the input/output buffer 5.

Note that in the above embodiment, the address obtained by adding -1, 0, +1, or +2 to the original address specified by the decoder circuit is configured to be accessible. The number of branches from one address to another address can be set arbitrarily.

In addition, in the above embodiment, the addresses to be selected in each selection circuit are assumed to be 1 and the last address are consecutive.
Although the configuration is made so that two loops are drawn, the two loops may be made thinner so that a certain address in the middle and the first address are continuous, and the next address after the coughing address and the last address are continuous. It is also possible to further increase the number of loops.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, each of the output terminals of the decoder circuit has M
Since a selection circuit using a group of OS transistors is connected, an adder/subtracter is installed in front of the decoder circuit to provide a semiconductor memory device that can access addresses obtained by adding and subtracting various numbers of addresses according to control signals to the original address output by the decoder circuit. There is an effect that can be easily achieved without providing any.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a memory device using a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional m-bit Xn word semiconductor memory device. 1-1~ln...word line, 2...address decoder, 3-Ll~3-n, m...memory cell, 4-1~
4-m...bit line, 5...popular cover sofa circuit,
6-1 to 6-n-...Selector circuit, 1 to 6 to 6-
-k. 4...MOS transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A storage area consisting of a plurality of memory circuit groups each consisting of a plurality of basic memory circuits and having one address and one word line, and for selecting a specific address from among the addresses of the memory circuit group. a decoder circuit, and a decoder circuit provided corresponding to each output signal of the decoder circuit that selects the memory circuit group at an address obtained by adding or subtracting a fixed number of addresses determined by the control signal group to the address of the output signal of the decoder circuit. A semiconductor integrated circuit device comprising a selection circuit. (2) The selection circuit is composed of a plurality of MOS transistors, the source or drain terminals of the plurality of MOS transistors are commonly connected to one output terminal of the decoder circuit, and the drain terminal of each of the MOS transistors is connected to one output terminal of the decoder circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the source terminal is connected to each word line, and each of the control signal groups is connected to each gate electrode.