DE2357500C3 - Circuit for storing the status of a binary counter in the event of a power failure - Google Patents

Description

The invention relates to a circuit for storing the state of a binary counter in control loops Operating voltage failure according to the preamble of the claim.

A method and a circuit of this type are described in DE-OS 22 58 632. The said The circuit works so that if the operating voltage fails, the switching states of the bistable stages of a Binary counter in these stages assigned magnetic core memory are entered that when the return occurs Operating voltage the states of the magnetic core memory can be entered in the assigned read-only memory, that a clock generator continues to switch the binary memory until a connected coincidence matrix identifies the same states in read-only memories and bistable stages and then the clock generator through the Coincidence matrix is switched off until the next power failure.

The process that takes place here takes a certain amount of time. But that is often not wanted. the

Information from the binary counter should be returned as soon as possible after the operating voltage has returned Disposal loan.

From CH-PS 4 95 090 a digital memory circuit is known with a multi-stage up-down counter and a digital-to-analog converter. Between the up-down counter and at least one file Stages of the digital-to-analog converter is connected to a buffer, which both its memory status when reading out as well as after interruption of a supply voltage. At the exit of the Signals are taken from the buffer and sent to a digital-to-analog converter for further processing (Frequency readjustment). For coupling between the buffers and the Up-down counters are provided with equivalent circuits that only switch through when the counter outputs of the up-down counter and the outputs of the buffers have the same logic level.

The object of the present invention is to provide a circuit of the type mentioned at the beginning which restores the status of a binary counter immediately after the operating voltage has been restored. Based on DE-OS 22 58 632, which is described as known, the effort is to be further reduced significantly will.

The solution to this problem is characterized in that the individual bistable stages of the binary counter special control inputs are assigned, the state of which is shared by all stages Control pulse at the control pulse input can be transferred to the associated outputs that the special Control inputs are directly connected to the outputs of the associated read-only memory and that of all bistable stages of the binary counter common control pulse input to a third output of the operating voltage discriminator which emits an impulse a short time after reaching the response threshold.

The figure shows an embodiment of the circuit according to the invention. It is part of a frequency tracking control with an S-level binary counter. In the figure, SD is a voltage discriminator with hysteresis, BZ is an S-level binary counter with the outputs Q2 to QS and the control inputs / 2 to / 8 of the last seven bistable levels assigned to each level, and the common control input Pr, Ts2 to Ts 8 driver transistors for the write windings , RS2 to RS8 toroidal core memory each with a write, a query and a read winding R 2 to R 8 emitter series resistors for the driver transistors, Ra 2 to RaS resistors to limit the query current, SP2 to PLC read memory, Tss a write transistor and Tsa a query transistor.

The mode of operation of the arrangement is as follows:

Since the first stage of the binary counter only causes very small changes in the manipulated variable, the state of the first stage is not saved; the memory error possible as a result is small. During operation, the transistors Tsa and Tss do not receive any base current from the voltage discriminator; the windings of the toroidal core accumulator are de-energized.

In the event of a power failure, the drop-out threshold of the voltage discriminator SD is reached first; the write transistor Tss receives a short base current pulse and becomes conductive for a short time. Received according to the position of the binary counter

those Trciberiransistorsen 7s 2 to Ts 8 base current, their associated outputs of the bistable stages, Q 2 to QS. show a logical 1. The associated write windings of Ringkernspeiche.- get on ku ^r z / .eitig live driver transistors a write current pulse and di ·. Corresponding ring core memories also store a logical I.

When the operating voltage returns, the response threshold for voltage discrimination, SD , is reached first. The interrogation transistor Tsa receives a short base current pulse and becomes conductive for a short time. All query windings of the toroidal core memory receive an interrogation pulse, whereby a read pulse is induced only in the read windings of the toroidal core memory with a written logical 1, which brings the associated read memory SP2 to PLC into the active position. This means that at each input / the state is given again that the corresponding output (? Of the counter had before the operating voltage failure. The voltage discriminator SD then sends a pulse to the control input Pr of the counter via its third output, which causes the States of the inputs / the bistable stages are transferred to the associated outputs Q. The counter is thus immediately returned to the position it was in before the power failure.

Compared to the previously known circuit, a coincidence matrix is no longer required, so components are saved and the setting of the binary counter is also significantly accelerated after a power failure.

In the circuit according to the invention there is an additional gain in operational reliability, went: a second hysteresis-free operating voltage discriminator is installed, whose response threshold is within the hysteresis range of the first discriminator SD and whose pulse output is connected to the reset inputs of the read-only memory and to the base of the query transistor.

1 sheet of drawings

Claims (1)

Claim: Sounding for storing the status of a binary counter in control loops in the event of an operating voltage failure, especially for communication systems in which a hysteresis-afflicted operating voltage discriminator is provided with at least two pulse outputs, the first of which emits a pulse when the drop-out threshold is reached and the second when the response threshold is reached and the first The output is the base of a write transistor and the other output of which is the base of an interrogation transistor, in which each output of a bistable stage of the binary counter, from which a signal can be removed for further processing, has a driver transistor, a magnetic core memory with write, interrogation and read winding and a read memory are assigned, the base of each driver transistor is connected to the output of the associated bistable stage, the collector of each driver transistor is connected to the write winding of the associated magnetic core memory and the read winding of each magnetic core memory leads to the input of the assigned read memory, while the collector-emitter path of the interrogation transistor is in a common line to the operating voltage and the collector-emitter path of the write transistor is in a common emitter lead for all driver transistors, characterized in that that the individual bistable levels of the binary counter (BZ) are assigned special control inputs (J 2 ... JS) , the status of which can be transferred to the associated outputs (Q2 ... QS) by a control pulse common to all levels at the control pulse input Pr that the special control inputs (J 2 ... JS) are directly connected to the outputs of the associated read-only memory (Sp2 ... 5p8) and that the control pulse input (Pr) common to all bistable levels of the binary counter (BZ) is sent to a third output of the Operating voltage discriminator (SDX) is switched, the short time after reaching the claim echschwelle emits an impulse.