DE2217634C3 - Safety circuit for counting pulses according to the binary number system in digital data processing systems, especially in railway systems - Google Patents

Description

The invention relates to a safety device for counting pulses according to the binary number system in digital data processing systems, in particular in railway systems, using an accumulator which consists of an arithmetic calculator in connection with a // -stepped circulating register, the counting information contained in η binary levels through a shift pulse triggered with each counting pulse with / 1 shift pulses is read out and written back again, increased or decreased by one, using two accumulators with a / 1-part comparator.

In many technical fields, counting processes are required to control operating sequences. For example, when determining the length of parts to be machined in machine tools Control of digital calculating machines for performing arithmetic operations the factory monitoring to determine Quantities and also in nuclear physics measurement technology.

In the railway safety system, the clearance and traffic reporting of Sirecken sections are becoming stronger Dimensions of axle counting systems used. These often consist of a streekengeräl fixed in place with at least two pulse generators arranged one behind the other in the direction of travel at the beginning and at the end of the route section to be monitored. The pulse generator are influenced and given one after the other at the vehicle axles passing the counting points each time two overlapping pulses from each other. These are / to determine the respective direction of movement of the rail vehicle is evaluated and converted into a direction-dependent one Axle counter converted. This axle counting

! Impulse that is thin as a counting / counting pulse, of the ten elements, is not registered by the test circuit

Acnsznhlunliigc. Which can be found at the Aths / uhlmilugen

used counters usually do not need an absolute The invention is based on the object of a safety

To deliver Zühlergchnm, because it is used for free or busy clock circuit for counting pulses

message »It is sufficient to know whether the relevant 5 corresponds to the binary number system with two accumulators and

Section is free or not free of axles. to create a «-part comparator, whereby

But there are also axle counting systems in which the usual, non-fire-proof «· digital circuits

individual paying agents are to be used for higher-level headquarters. Then the test

Task an exact message about the respective circuit in the form of a comparator be designed in such a way that

Must submit number of axles. Such payment points 10 that a monitoring of this test circuit for proper

are referred to as axle reporting points. appropriate work is possible. Further lies

If in the listed digital Dalenverarbei- the invention is based on the object that the two

systems, especially in the field of accumulators, are designed in such a way that dynamic

Railway safety system for axle reporting points, mixed testing of all levels is possible.

a counting circuit according to the binary number server 15 According to the invention, the object is achieved by

is to be used, which with standard commercial evidence that each part of the comparator with two equal

knüpfiingsbaustcinen is to be created, for example in binary levels of the two U meow registers

TTL technology, for security reasons it is often linked to a leg test signal

required a great deal of effort in terms of a match or mismatch

unambiguous monitoring riiif correct work of the "o of the present Rirtärrustaiide that mm er-

To operate the counting device if in the \ erc-

Deien circuit techniques in more or less gm-pulse .insoluble shifting pulse,. norator provided

During periods of time, a disturbance is to be expected, which via two sliding lines per η different

nuilV during puhe triggers, which against each other around IHO 'pha-

A device in which additions are never through 35 senversci.above, and that the test signal counts in common, but with the help of an adder, one of the two shift pulses is applied gen, in which a first summand is included as the result of a pre-EXK! .IiSIV-C) DER member. the one failure cii arithmetic calculation and the number one can be entered as the message memory steep, second summand. Essential for this safety circuit is / is in the book by A. P. Speiser with the title -Digi- 30 counting pulses that the two accumulators tale arithmetic systems «, published by Springer-Verlag, each one / a number impulse for you is processed separately in 1961, on pages 17 ') and ISO, describe in more detail!' heal, and / was with a phase shift of An ISi I is the basis of such a facility. This measure is more advantageous Accumulator which, from an arithmetic unit for arithmetic means, achieves that with every addition or symbology Operations in connection with an initiation of the two tasks of the accepteration level Circulating registers exist, the / around storage accumulators with legal information viewers of the calculated result. save a change / gave way to inequality If to the one in the accumulator. Number one and equality of the two binary information items is to be added, the in (current regi- Bcfindlihe number through a number of tactical and thus security-related testing of the pulses are read out and in there :, arithmetic calculation - two accumulators possible, plant entered, the new under summation. Any comparator can be used recovered number in the Umlaufrcr-k-i to become again. However, a backlog is particularly useful. The use of di. r known same, which itself can also be monitored. A vorlcil accumulator as a counter in technical fields 45 a further development of the invention provides a reference high safety requirement si ni, 1 without \ being the same, in which each part consists of two N AND-Glielercs possible, especially not then. -Acnn to the one with two inputs each for the one hand Construction of commercially available link circuits .iu, ui \ alenlen and, on the other hand, the complementary ones which inherently does not consist of error sig- nals of the two assigned binary levels, rather are. 50 in which the two NAND gates also have a

From the German Auslegeschrift 1 132 972 a third NAND element is linked, the third being

Arrangement for the control of counting chains known. NAND members of all parts on the output side with one another

In this circuit arrangement are connected to increase una the output of the comparison

form two counting chains in order to ensure safety and reliability.

Synchronous operation provided. To control the two accumulators, the counting elements of the two counting chains are Ix. ^{1 For} each number pulse to be entered, two to ISO each one of resistors and diodes, the best opposing component, connected to a test circuit, consisting of phase-shifted displacement pulses. Ix'iioiigt. of! enen each as many shifting impulses that do not show any disturbance with concurrent counting chains, as the two revolving registers of the accumulation message output. This test circuit contained binary steps for the post-60 iators. Part that it cannot be monitored itself, so that a preferred embodiment of a shifting system can also act as a fault in this circuit: puhgeucniiors to trigger the fceidcn required, so that the necessary error message of accidental impulses advantageously consists of a disrupted one No counting drive. For another no pulse generator, the pulse of which can be seen in the fact that the individual stages are in the form of a ring or, in the case of a slightly different counter only, a static pnfctricb directly controls a bistable flip-flop, obviously the switching area unli'rlicgcn . so that bc at .leren; u | ui \ alenlcn and antivalcnl output each siimmlc errors in corresponding counters with one of the two shift lines output

scilig vcrbuiv.lenes Sch.iltmittcl with associated bistable Slciin, i.lwili .r is connected, the control switch "tunk Virn eisten shifting pulse of the two shifting pulses brings the two switching means for outputting the shifting pulses into effect the output of shifting pulses is provided, which switches off after outputting η shifting pulses via one of the two switching means with the aid of the associated control switch.

The two switching means, which ultimately output the shift pulses phase-shifted by IKO ', can be constructed, for example, as an AND-olied. However, it is also possible to use two gate circuits, each of which can be activated by the associated bistable control switch, that is to say in the switched-on state, in which shift pulses are output. In each case after the output of a number of η Vcrsehiebimpulscn, the respective gate circuit is switched off again by the assigned control switch.

The one explained in more detail in the following text The circuit is based on the knowledge that when using a yarn specific comparison for the Heiden circulation register, as it has already been identified in more detail it is possible to then use this comparator even to work properly to be able to monitor when the 'uciucn accumulators controlled according to a given test program. When processing the specified Program, a binary number defined as an error must appear in the two circulating registers Comparator must be recognized so that the fault message memory responds. The termination of the program sequence and thus the setting of the basic position of the two accumulators when the Operation is also dependent on the successful addressing of the fault message memory made dependent.

The test program, particularly for the Verglcicher is triggered in an advantageous manner by a test circuit that includes a three-stage control unit, which by means of a Einschaltbcfehls be switched in its first stage, on the output side with the set and reset inputs of the individual binary stages of the two Umlaufrcgis ¹ er is connected in such a way that the number 2 " - 2 is set in the two circulating registers, whereby the control unit can be set to the second stage with the help of a feedback branch after the first stage has been activated and the switch-on command is still present, the output side for both accumulators and the shift pulse generator triggers a test counting pulse to set the number 2 "- 1 and to delay setting the basic position of the fault message memory, which is connected to the control unit on the output side, so that when the basic position of the fault message memory is set, the third level is still present when the switch-on command is still present e of the control unit takes effect and also triggers a test counting pulse to set the number 2 ".

By using this test circuit, which can also be doubled for safety reasons, is achieved in an excellent way that to achieve a high level of security in error detection all facilities provided for counting pulses including comparing for the two Circulation register and the fault message memory were monitored. This makes it more advantageous Way possible to refrain from an intrinsically safe structure with the named assemblies and through Use of commercially available control circuit technology to keep the costs for the safety circuit low.

Exemplary embodiments of the invention are provided below explained on the basis of the drawing. It shows in one

Fig. 1 shows the block diagram of all circuit parts of the Safety circuit for counting pulses.

F i g. 2 the block diagram of a transmission pulse generator for two against each other by ISO phase- • 5 beautiful shift pulses,

3 shows a timing diagram for the transfer pulse generator according to Fig. 2,

Fig. 4 is a block diagram of another advantageous one Shift pulse generator, * ° FIG. 5 shows a pulse diagram for the shift pulse generator according to Fig. 4,

Fig. (S the block diagram of a test circuit for Triggering a test run of the entire counting sound, and

* S Fig. 7 and H tabular compilations of binary values of the individual levels of the revolving register in the basic position and up to the set number 1 as well as for the read run bni the stored number 2 "- 2 and when or after the deposit of two further pulses including one Comparison of the binary values of a test signal with one of the two shift pulses.

Fig. 1 shows schematically a block diagram of all circuit parts of the safety circuit for counting pulses. An application example for railway safety technology is shown, whereby it is assumed that the number of axles driven past at a paying point is processed depending on the direction in an axle counter so that the paying point can be used for higher-level central tasks, i.e. as an axle reporting point. The safety circuit to be described in more detail in the present application serves as the axle counter. The payment point is formed by two pulse generators PGl and PGl , which are attached to a track (not shown) that when influenced by a vehicle axle, partially overlapping pulses result, which in the exemplary embodiment are fed to two direction units RTl and RTl at the same time for safety reasons. As a rule, however, one direction unit is sufficient to determine the respective direction of movement of the vehicle axles that have passed the counting point from the sequence of the pulses emitted by the two pulse generators PG1 and PG2. Corresponding to the determined direction of movement, there is a direction indicator output by the output RTU or RTIl of the directional unit RTi or RTl . When passing an axis at the counting point, a single counting pulse is output via the RT10 or RT10 output. This passes via an OR gate Ol Ol or an accumulator Al or Al. Each of the two accumulators is composed of an arithmetic calculating unit RWL or RWL in conjunction with a three-stage circulation register whose stages in the accumulator is all Al, All and A 10, respectively. The corresponding equivalent levels of the circulating register from the accumulator

or Αϊ carry the references All, Ali and / 120. The number of stages to be anticipated for the circulating registers is to be chosen so that the storage volume of the circulating registers is not fully utilized even with the highest number of axes. In the present exemplary embodiment, only three-stage circulating storage units were chosen for a better overview of the drawing documents; However, the subject of the application is in no way restricted to the use of such circulating registers. The individual binary levels of the circulating register consist of flip-flops with dynamic clock inputs to which Vcrschicbcimpulsen are applied. The clock inputs of three Binärslufcn All, Al \ and / JIO are the accumulator Al with a Schicbcleitung VSI and the binary stages AU. All and / 120 of the accumulator Al vcibundcn with a Schicbcleitung KS'2. As will be explained in more detail later, two shift pulses TI and 711 of a shift pulse generator VPR , which are phase-shifted by 180 'with respect to one another, reach the two circulating registers via these negative shift lines VS1 and KS 2, in such a way that information is transmitted first in the accumulator A 1 and then only in the accumulator Al takes place.

In accordance with the dial number system, the binary levels in the two revolving registers have a fixed value assigned to them. The equivalent binary levels All and Al? ^{Represent the value 2 2} in the set L state. The downstream binary level .411 or All saves the value 2 'in the L state and the last level A 10 or AlQ of each circulation register the value 2 ". The highest number that can be represented with a three-level circulating memory is calculated according to the formula 2 "- 1; in the present case with "= 3, the number of binary stages 7. A results from the arithmetic calculator RWL or RWL to the Binärstufc All or All Binärkennzeichen given the value of O or L is the A input 120 and / 1220 one at the trailing edge Vcrschiebcimpulses taken over on the visual line KS1 or KS2. The binary identifier is simultaneously fed to the input / 1121 of the binary stage A 12 or to the input AIII of the binary stage AU via an integration link / Vl or N2.

The Binärstufc All in the accumulator is Al / 1110 and ALW one hand connected with its inputs to the ALU of the equivalent output Binärstufc All the other hand, at the output antivalentcn Aiii. Since complementary signals are available for controlling the binary level All , a negation element, as provided between the binary level All and the arithmetic unit RW1 , can be dispensed with. The same applies to the binary levels All and / 110 and the equivalent binary levels in the accumulator A1 .

Further inputs for the binary levels / 412, All and / 110 are marked with AIlA, AIlA and / 1105. With the aid of the inputs AIlA and AIlA , the binary levels All and All can be set and the binary level / HO can be reset via input / 4105 with a corresponding setting signal. Then only the last-mentioned binary level / HO is in the marked basic position. Since the Eins'cllsignal in the same manner to the binary stages AU, All lind / 420 acts in the accumulator Al, this applies to both Umlaufrcgister independently of a Vcrschiebcimpuls, the two high-order binary stages and AU All are also set, while at the end of Umhuifregisters current binary level / 120 is reset. Thus, with the aid of the above-mentioned entry signal, it is possible to enter the binary number LLO in both circulation registers independently of the binary number already stored, which corresponds to the number 6 'in the numbering system.

As long as a retriggerable monostable multivibrator

to MK is in the stable basic position, an output means ASG that the binary stages AU, Al \ and / Al 120 connected in the accumulator with the equivalent outputs of aluminum, AIII and ALOL turned on. The stored in the accumulator Al binary number is encoded on line -4.SGt output. A via the OR gate Ol given Ziihlimpuls controls the retriggerable multivibrator inonostabile MK in the unstable state for the duration of a Informationsumspci-

ao chcrung remains in the accumulators while the output device ASG is switched off.

At the individual binary levels of the two circulating registers in the accumulators Al and Al is a

5 three-part comparator VG connected, which has the task of determining whether similar outputs of two equivalent binary levels of the two circulating registers have the same or different logical words. Further details are explained in more detail later in the text using tabular compilations. Each part of the comparator VG consists of two NAND elements NDI1 and / VD22, each with two inputs for, on the one hand, the equivalent and, on the other hand, the complementary outputs of the two assigned binary levels All and AU. The two inputs of the NAND element NDIl are connected to the equivalent outputs AlU and AIII of the two associated binary levels and the inputs of the NAND element NDU are connected to the complementary outputs Aiii and AWb of the same binary levels. On the output side, the two NAND elements ND 12 and ND22 of the first part of the three-part comparator VG are connected to a third NAND element NDt. As the structure of the three-part comparator VG shows, three of the NAND elements described are required for each of the three comparison cells. The third NAND elements ND1, NDl and NDi in the three parts of the comparator VG are connected to one another on the output side (wired-and-combination in positive logic). The point of connection practically represents the output of the comparator, the output signal of which, however, in the example is inverted with the aid of a negation element Ni, reaches an EX-CLUSIVE-OR-Glicd EO as a binary test signal UE .

In the event of a fault, the test signal VE has a characteristic state compared to a comparison signal, in which the EXCLUSIVE-OR element EO has a downstream fault message memory SR

adjusts from the basic position shown to the other position. The initial position output of the fault report memory SR is connected via a delay device KDl to a fault indicator SM which works according to the quiescent current principle and which outputs or forwards the fault detected! If the Störungsmeldungsstcichcr SR is switched from the basic position shown to the other position only for a very short time, i.e. not there

ίο

If there is a short period of time and then it is reset to the basic position, the malfunction indicator SM does not respond because of the intended delay. Only when the fault message memory SR is not in the basic position for a long time will the fault indicator SM be triggered. Further details will be explained in more detail later.

The circuit arrangements according to FIGS . 2 and 4 represent advantageous embodiments of the displacement sense, denoted by the reference symbol IiKXl of the relevant output of the bistable multivibrator BKl . The dash-dotted vertical line Ll represents that point in time at which a counting pulse is given via the OR gates Ol and Ol (Fig. 1), which is sent to the two accumulators AI and Al and at the same time to the setting input TGE of the gate circuit TG . The diagram line labeled T (J shows a curve that goes to

Pulse generators VPR , which optionally at the ^{time of the counting pulse accepted from pulling} the 180 ° phase shifted position from "off" to the state "on". In order to

- "■ - -" - · - ^: ·> —cu: .- k..i “:! / Ei j _st <} \ _c Gate circuit TG permeable for the in the

Diagramlinic BKIi shown pulse. The first Vordcrflankc BKl 10 of the pulse in diagram line SACI1 switches the two bistable control switches SSP 1 and SSR2 so that the connected AND gates SLl and SLl are prepared; see diagram lines

Shift pulses for the two shift lines VSL and VSL can be used. First of all, the displacement pulse generator VPR1 according to FIG. 2 is explained in more detail below. A pulse generator PR '5 for square- wave pulses controls a bistable multivibrator BKl, whose equivalent output BKIl is connected on the one hand to a gate circuit TG and on the other hand to an AND element 5Ll. The anti

SSRi and SSRl. The following first trailing edge BKHl of the pulse in the diagram line BKH switches

valente output BKH of the bistable multivibrator BKl, ^iu the control shift register SSi from the first stage ^e " ° . . ■■, ■ ...... ι ·. cc «<: _ .4:": · - c ".. f" ei. * "·» »__. i_ ι \ <.. ",.,., t

which is given away with the Grundstcllungsmarkicrung is connected to an AND element SL1 . Furthermore, two bistable control switches SSRl and SSRl are provided in the form of bistable trigger stages, which with their

SSIl continues into the second SSH stage. At that moment, the first shift pulse of the Vcrschicbepulscs Tl is already given to the shift line VSl (Fig. 1) via the AND gate SLl; see diagram linic

Equivalent outputs with the two AND-Glic- ^a 5 VSl. After switching over the bistable multivibrator

the SLl and SLl are connected. When the two bistable control switches SSR 1 and SSRl are in the basic position, the two AND gates SLl and SL2 are switched off. The gate circuit TG

The first shift pulse of the shift pulse TII, which is 180 out of phase with respect to the: m shift pulse TI, arrives via the AND element SL2; see Diagramlinic VS2. The next

On the one hand, it acts on the dynamic 3 ° trailing edge BKl 12 of the pulse in the diagram line

Control inputs of the two bistable control switches BKH causes the control shift register SSl in

SSR 1 and SSRl when a logical transition from its third stage SS13 is set. When entering

() takes place after 1, i.e. on the leading edge of a by setting the fourth stage SS14 of the control shift register

the gate circuit TG output signal. Furthermore, at the leading edge BKH3 , the bista-

the gate circuit TG via an OR gate 03 with 35 bile control switch SSRl through one of the third

a four-stage control shift register SSl connected to stage SS13 given trailing edge pulse again

"" "" '"■■'" the marked basic position is switched back. then

if the AND element SLl is no longer prepared, see this

the one from which the last stage SS14 on the output side returned to the first stage SSIl via the OR element 03

is coupled. In addition, the output of the last that more of the bistable multivibrator COS out stage SS14 of the control shift register SSl with 40 gebcnc pulses no longer be given of the bistable VSI the Schicbeleitung the basic position-adjusting input. See also the curve in the Dialcn control switch SSRl connected. The third level grammar SSRl. Up to this point in time, a shift pulse has reached SS 13 of the control shift register SSl acts on a shift line VSl, the dynamic control input with the effect of logically precise three individual, successive Ver-1'nach 0 to set the basic position_des_bista- 45 schicbeimpulsen, see Diagram line VS !.

With the next trailing edge BK114 of the pulse switching the control shift register SSL on the one hand, the bistable control switch SSRl is set back to the marked basic position, see diagram-

bile η control switch SSRl. The input TGE for switching on the gate circuit TG is connected to the OR gate O1, so that each counting pulse given by this gate circuit TG becomes effective

switches. The blocking input TGS of the gate circuit TG 50 linie SSRl. The AND element SL2 is thus activated

is connected to the output of the last SS14 stage of the control system, so that more of the complementary output

shift register SSl connected. The action output ßK 12 of the bistable flip-flop BKl output

wise of the shift pulse generator VPRl, pulses are no longer sent to the shift line VS2gclan-

below on the basis of the pulse diagram of gen. From the diagram line VS2 it can be seen that daG

Fig. 3 explains in more detail. 55 the sliding pulse TII also consists of only three sliding

The individual diagram lines of the pulse diagram pulse exist. The leading edge of the one from the last

mcs according to FIG. 3 have reference numerals which are also output by stage SS14 of the control shift register SSl.

Assemblies or parts of assemblies in the switching pulse reach the TGS dci locking gear

according to fig. 2 mark. The equivalent gate circuit TG and switches it off; see curve

gear BKH of the bistable flip-flop BKl leads at 60 in the diagram line TG. The trailing edge of the pulse

The switched-on pulse generator PR stands in the scs of the last stage SS14 of the control shift register;

- - · · '■ ^{! : D} ~ - ^u - ⁰ ^ "SSl finally prepares over the OR-equation

O3 the first stage SSIl of the control shift register:

CC · ΓΛ-! .. I 1_ 1 · -r- ■. . . .

first diagram line, which is also referred to as BKIl , represented rectangle sign ^. The complementary output BKIl of the bistable flip-flop BKl

SSl forward. However, since the gate circuit TG switched off

leads to a 180 "compared to the signal of the equi-65, this stage remains in the prepared! valent output BKIl phase-shifted Si state until another counting pulse via the OR

Link Ol (Fig. 1) arrives and the described!

Process of triggering the two displacement pulses

gnal, which in the pulse diagram according to h ig. 2 in the second diagram line from above is shown and

repeated.

The circuit arrangement for another advantageous displacement pulse generator VPR1 is shown in FIG. 4. Here those main groups and logic elements which have already been described for the arrangement according to FIG. 2 and which have the same functions are provided with the same reference symbols. A superficial comparison of the two circuit arrangements according to FIGS. 2 and 4 shows that in the latter circuit arrangement the gate circuit 7X7 according to FIG. 2 is not required. Another significant difference is the type of Steuersch'cberegisters used SS2 in conjunction with the AND Cilicd Ul compared with the control shift register

551 in the arrangement according to FIG. 2. While the '5 Stcucrschicbercgister 5Sl gets by with a number of stages which is one higher than stages for the two circulating registers in the accumulators A 1 and / 42 (Fig. 1) are provided , fürdasSteuerschiebcrcgister SS2 is in the arrangement of Fig. 4 ^a ° a number of steps required, which is calculated according to the formula in brief + 2 when the number of turn, η indicates the number of stages of the Umlaufrcgister. In the present case, the control shift register exists

552 therefore consists of eight stages. ^a 5 In the exemplary embodiment under consideration, the controls

Pulse generator PR sends the structure register 552 directly and continuously. The unstable multivibrator BK1 is connected to the outputs of the individual stages via the AND element 1/2, which is connected on the output side to a 3 »gate circuit SL10 and to the AND element SL2. The AND gate Ul is also connected to the pulse generator PR . The AND gate SL1 used in the circuit arrangement according to FIG. 2 could also be used in place of the gate circuit SL10. It would just as well be possible to use another gate circuit instead of the AND element SL2. The shift line VS1 is connected on the output side to the gate circuit SL10 and the other shift line VS1 is connected to the AND gate 5L2 on the output side. The bistable control switch SSRi is used to switch the gate circuit SLlO on and off, while the other bistable safety switch SSRl can prepare the AND element SL2.

The mode of operation of the Vcrsch'cbepulsgcnL-rator VPR1 is based on the pulse diagram of Fig. 5 explained The same applies to the designation of the niagrammlinicn of this pulse diagram as for the pulse diagram according to FIG. 3. The first diagram line labeled PR shows the pulse output by the pulse generator PR to the control switch register 5S2. The graph lines SSRl and SSRl show by their curves the respective switching state of the two bistable control switches SSRl and SSRl, based on the devices downstream of these. Finally, the last two diagram lines KS1 and KS2dic illustrate shift pulses emitted on the two shift lines after this counting pulse, which are also phase-shifted by 180 ° with respect to one another.

During the period in which no shift pulses are emitted, none of the eight stages of the control shift register SS2 is set; The Schicbcbi »is missing, and the AND element U1 is blocked. Thus, the pulse given by the pulse generator PR to the input of the first stage SS21 of the Slcucrschieberegislers SS 2 and to the AND element Ul has no effect. Only when a counting pulse reaches the first stage SS21 of the control circuit register SS2 via the line coming from the OR element O1 (FIG. 1) is this stage set so that the register 552 can be forwarded. This point in time is again marked in the pulse diagram according to FIG. 5 with a vertical, dash-dotted line L2. The first trailing edge PRl - see diagram line PR - switches the control shift register S52 from the first stage SS21 to the second stage S-S22. The two bistable control switches SSRl and SSR2 are switched from the marked basic position to the other position, whereby on the one hand the gate circuit 5L10 is switched on and on the other hand the AND element SL2 is prepared and initially also remains. The signal emitted by the first stage 5521, the Steuerschicbcrcgisters SS2 controls indirectly via the AND element Ul the bistable flip-flop BKl from the marked basic position below the Influence of the pulse from the generator PR in the other position. Further control pulses for the bistable multivibrator BK1 are then triggered as long as the other stages of the control shift register 552 are switched. With the return flange PR6 of the pulse emitted by the pulse generator PR , see diagram line PR the seventh stage 5527 of the control shift register SS2 is set 526 emits a pulse that switches the bistable control switch SSRl back to the marked basic position. As a result, the gate circuit SL10 is switched off again, so that the shift pulse 71 on the shift line VS1 ends with a length of three shift pulses, see penultimate diagram line VS1. At the next trailing edge PR7, see diagram line PR, di? eighth stage SS28 of the control shift registerSi SS2 set. The pulse emitted by the seventh stage SS27 restores the basic position of the bistable control switch SSR2, as a result of which the subordinate AND element SL2 is no longer prepared. This also terminates the shift pulse 711, phase shifted by 180 ", on the shift line KS2 with a length of three shift pulses, see DiitgrammlinN KS2 SS21 is provided, the input; assumed output days of the shift generator VPR2 is reached again, in which, among other things, the AND element U1 is also blocked.

F i g. 6 shows the block diagram of a test circuit PSG for triggering a test run of the entire counting circuit after a special switch-on command, which can be triggered, for example, when the counter has reached its basic position. This can be done by counting vehicle axles or by specifically setting the basic position; via the reset inputs (not all shown! of the individual binary levels in the circulating register! (Fig. I). Since it is assumed that the switch-on command is only pending for a very short time, a memory switching center is provided for this in the form of a bistable flip-flop BK1 , the lack g for yet to be described control operations spti chert. an essential component of Prüfschaltun PSG by F i the Einschaltbe. 6 is a control unit SK, the inde gig gisternder of the number of binary stages in the Umlaufre accumulators Al and Al (Fig. 1) has three In the exemplary embodiment, the third stage is

■

SKi of the control unit SK fed back to the first stage SKI via an OR-üüed O4. This is also connected to the bistable multivibrator BKZ via the OR element 04. Another feedback branch leads from the output of the first stage SKI of the control unit SK via an OR element OS and an AND element i / i to an incremental input of the control unit SK. The AND element Ul has the task of only forwarding incremental pulses to the control unit SK if a Einüehaltbefchl was present. Thereafter, the bistable flip-flop BKl is outside the marked basic position. The dynamic input of the OR gate OS is connected to the output of the Störungsmcldungsspeicher SR . The connection can also follow the output of the error message memory SR that marks the initial position, but then a dynamic input must be provided for the OR element OS , which responds to the transition from logic 0 to 1. The output of the first stage SKi of the control unit SK supplies the setting signal for the Selz- and Rücksttzeingängc of the binary stages, in the circulating registers of the arrangement according to FIG. 1. Both the output of the second stage SKI and that of the third stage SKi of the control unit SK is over an OR gate O6 connected to the two OR gates Ol and Ol (Fig. 1). At a given time, two successive test counting pulses are given via this connection line. On the output side, a delay element VD1 is connected to the second stage SKI of the control unit SK, which delay element is connected to the input of the disturbance signaling device SR which sets the basic position.

The mode of operation of the test circuit PSG according to FIG. 6 is initially without special consideration of the effect on other assemblies: After a switch-on command via input K , the bistable flip-flop BKl is controlled from the marked basic position to the other position and sends an incremental pulse to the three-stage control unit SK via the OR element OA . By advancing from the first stage SKI to the second stage SKI , a pulse is emitted via the output of the first stage SKI , which on the one hand serves as a setting signal in the circulating registers (FIG. 1) and on the other hand for further advancing the control unit KS . Since d; a: s Ui'iD-Glicd Ul is prepared by the bistable flip-flop BKl , the pulse emitted by the first stage .VKl is passed via the OR element (75 to the stepping of the control unit SK. When stepping up from the second step SKI w in the third step SK3; ird the output from the second stage SKI impulsalsTesl-Zählimpulsund also output to the delayed return of the Störungsmeldungsspcichcrs SK function of this provision, the control circuit SK via the two Vcrknüpfungsgliedcr Oi and Ui is incremented again, wherein the. A test counting pulse is also emitted in the last stage SKi . This pulse sets the unstable flip-flop stage BKl back into the marked basic position and prepares the first stage SKi of the control unit SK for a later cycle again.

FIGS. 7 and 8 show tabular compilations of binary values of the individual stages of the circulation registers in the accumulators Al and Al (F i g. I), values of the binary test signal UE of the comparator VQ and the respective binary instantaneous values of the displacement pulse 111. In the The first two columns of the tabular compilation according to FIG. 7 are binary values of the equivalent outputs

Aiii and / 1222 of those binary levels AiI and / 122 with the highest value 2 ² (FIG. 1) are entered. As a result, the two columns are overwritten with the reference symbols of the corresponding binary levels All and All. The same applies accordingly

»» For the following two columns as well as for the fifth and sixth columns, which are overwritten with Ali, All or AW and / 120. The penultimate column contains values of the binary test signal UE, which is fed to the EXCLUSIVE-OR gate EO. The last column

»5, which is overwritten with ΤΉ, contains instantaneous values of the shift pulse 711, which is also fed to the EXXLUSIV-OR element EO for comparison / awakening. The values in the first line apply to the basic position of the two accumulators Ai and

“Oh, Al. All equivalent outputs of the binary level, such as output AIII of the binary level All, have the value (I. The same applies to the binary test signal UE of the comparison VG because of the existing agreement.

»5 punkl no shift pulse 7TI is triggered, after which its value on the shift line VS1 and then also on the EXCLUSIVE-OR element EO is equal to 0. It is now assumed that an axis passes the two pulse generators PGl and PGl in this way.

3 "means that the direction units RTi and RTl each trigger a counting pulse, which is added to the existing count with the help of the arithmetic units RWl and R W1

the addition process as logically and for the subtraction process, i.e. in the case of counting pulses, as logic! To be defined. These directional indicators arrive at the inputs RWIl and RWIl of the two arithmetic units RWi and RWl. At ci-

There is no need for any other type of procedure to have a special identifier on the inputs RWIl and RWIl in order to trigger an addition process. For this reason, the b triggered by the test circuit of Figure PSG. TCST-count pulses are arithmetically processed without the presence of a specific Richtung.skcnnzcichcns from the Richtungscinheilen RTL and RTL in the arithmetic units RWL and RWL.

The respective binary value of the binary stage / HO is read out and given to the arithmetic unit R Wl with the shifting pulse of the shifting pulse 71 on the shifting line VS1, which is triggered first with the counting pulse. There the addition takes place with a logical L as well as the output of the calculated value in the form of a binary identifier to the binary level All. The second line of the tabular compilation according to FIG. 7 shows that the equivalent output AIII of the binary level All Io gisch L leads after the first shift pulse of the shift pulse 71. Because on the second Schiebcleitung VSI no Vcrschicbcimpuls was available because of the phase shift of 180 "of the two displacement pulses 71 and 711, has the Umspeichcrvorgang in the accumulator Al hitherto not yet taken place, so that the equivalent output / 1222 of the binary stage AU still logically 0. As a result of the mismatch of the values at the outputs of the binary levels A 12 and AU , the value of the binary

Test signal UE equal to Z ,. Since after the first pulse of the operation pulse Π the value of the

EXCLUSIVE QDER element EOMn output signal to the fault message memory SR, after the first shift pulse of the shift pulse ΠΙ, the storage process in the accumulator / 12 has also started. As can be seen from the third line of the table according to FIG. 7, the equivalent outputs / 1122 and / 1222 of the two binary levels AU and A22 then both have the value L. Because of this agreement and the simultaneous agreement of the values at the complementary outputs the value of the binary test signal UE equals 0. This value corresponds to that of the shift pulse 711 after the first shift pulse, so that in this case too the EXCLUSIVE-OR element EO does not output a signal to the downstream fault message memory SR . This remains in the marked basic position. After the respective second shift pulses of the shift pulses 71 and 711 of the re-storing in the two accumulators / 11 and Al is up to the two binary stages / ill and Al \ of valency 2 progressed '. The restoring process is ended after the di itth shift pulses of the two shift pulses 71 and 711, when the equivalent outputs of the two binary levels AiO and / 120 the Wer! L lead. Since the last-mentioned binary levels have the value 2 "and only these last two levels have the value L , the two circulating registers are set from the initial position to the value 1 after the first counting pulse has been entered.

If, when entering the counting pulse on one of the three steps with the help of the EXCLUSIVE-OR element EO, a difference between the values of the binary test signal UE and the shift pulse 711 had been determined, the fault message memory .ST? has been steered from the marked home position into the other position. After a delay time specified by the delay element VDi, the malfunction indicator SM, which works according to the reverse current principle, is addressed and the detected malfunction is reported until the malfunction message memory SR has been reset to the basic position by a signal via the withdrawal input R 7.

The test circuit PSG according to FIG. 6 is used to check the safety circuit / to count pulses, in particular the comparator VG (Fig. 1), which - as already briefly explained in the introduction to the description - can, for example, come into action once for each basic meter setting . For this purpose, a switch-on command is given to input K , which controls the bistable flip-flop BK1 from the marked basic position into the other position. The three-stage control unit SK triggers a setting signal which sets the two circulation registers in the accumulators / II and A1 to position 2 "-2. In the exemplary embodiment, the counter position 6 is selected. The tabular compilation of FIG Fig. 7 and shows in the first line the values of the equivalent outputs of the individual binary air flows after the setting signal.

The Ausgatigssignal the second stage of the control SKI SK work passes via the OR gate Whether as a test Zöhlimpuls via the OR gates 02 and OX to the two accumulators Al and A2 and on the Verschlebepulsgenerator VPR. After each of the three displacement pulses of the two

shift pulse 71 and ΠΙ is included in place of the number 6 in the two accumulators Al and A2 the number. 7 After the first two shift pulses of the two shift pulses 71 and ΠΙ, all equivalent outputs of the six binary levels lead to the

ίο value L. Since the value of the binary test signal UE is equal to 0 and thus corresponds to the value of the shift pulse 711, the EXCLUSIVE-OR element EO does not respond. Since the values of the equivalent and the complementary outputs of the binary stages do not change after the second and third shift pulses of the two shift pulses 71 and 711, the value O of the binary test signal UE is retained. In contrast, however, the value of the shift pulse 711 changes, so that after the second shift pulse of the shift pulse 71 there is a difference between the values of the binary test signal Uli and the value of the shift pulse 71i, see line 4 in the compilation according to FIG How high the η of binary steps is in the two circulating registers of the accumulators Ai and Al , when entering the number 2 "- 1 an apparent disturbance occurs, which is determined as a value difference between the binary test signal UE and the shift pulse TiI the Störungsmeldurgsspeicher SR is temporarily set from the basic division to the other stable position.

The delay time of the delay element VDl in the test circuit PSG according to FIG. 6 is selected, for example, so that the output signal emitted by the second stage .SA'2 of the control unit SK only reaches the input of the Störungsmcldungspeicher SR which causes the basic division when the third shift pulse of the two Verschiebcpulse 71 and 711 finished Umspeichervorgänge in the two Umlaufrcgistern the batteries Ai and Al. The malfunction indicator SM speak! in the test described does not come on because of the delay caused by the delay element VDi.

When the basic position of the Störungsmelclungsspcichers SR is set, the OR element O5 and the AND element Ui in the test circuit PSG according to FIG. 6 the control unit SK advanced again. The third stage SKi outputs a pulse.

which on the one hand brings the bistable flip-flop BKl back into the marked basic position and on the other hand is used as a second test counting pulse via the OR element Ob. By means of this test counting pulse, the two circulating registers in the accumulator doors Ai and Al are set to the number 2 "= 8 after being resumed three times. It is essential that, one after the other, the binary runs AU and All, AU and All and finally the Binary levels AlO and AlO occur after the first, the second or after the third displacement pulse of the displacement pulse 71, see lines 2, 4 and 6 in the compilation according to FIG of different

bepulses 711 if the binary values correspond to corresponding outputs of equivalent binary signals, the value of the binary test signal UE agrees in all lines of the compilation according to FIG. 8

409 635/329

ten values of the shift pulse ΠΙ, so that the EXCLUSIVE-OR element EO does not respond. For example, if the comparator VG (Fig, I) were to work properly or if one of the binary levels of the two circulating registers were to fail in the course of the three-time re-storage operations, the malfunction indicator SM would inevitably respond during this test run because a reset via the OR element 06 to the Time did not take place. A reset could only be initiated again by a special signal via the withdrawal input RT. The two u «

in

in the »« Ρ '^' ΐΖηΓζ
the Sicherheitschaljung Wg

Re-admitting is for Safety circuit is m

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Function. For this purpose 4 sheets of drawings

Claims (4)

Patent claims: 1.Safety circuit for counting pulses according to the binary number system in digital data processing systems, especially in railway systems, using an accumulator, which consists of an arithmetic calculator in connection with a / i-level circulating register, whose counting information contained in η binary levels is given by one with each counting pulse triggered shift pulse is read out with η shift pulses and written back again increased or decreased by one, using two accumulators with an n-part comparator, characterized in that each part of the comparator with two similar binary levels (.4 12. Λ22) of the two circulating registers connected i.si for a binary test signal ( UL \ depending on agreement or non-agreement of the respective binary states that / in order to generate the shift pulses (71, 711) a shift pulse generator ( VPR) that can be triggered by each counting pulse is provided white .Schiebeleitungen ( VSl, VSl) triggers each η Verschiel.eimpulse, which are phase shifted by 180 "from each other, and that the test signal ( UE) is led together with one of the two shift pulses to an EX-CLUSIVE-OR-GHeJ (EO) which controls a fault report memory (SR). 2. Safety circuit according to claim 1, characterized in that each Te ^: "of the comparator (KG) from two NAND members (JVZ) II, ND22) each with two inputs for on the one hand the equivalent and on the other hand the anlivalentcn outputs (/ 1122, / 1222 or / 1123, / 1223) of the two associated binary levels (/ 112, All) , the two NAND elements (NDH, DNIl) are linked via a third NAND element (ND!), The third NAND elements ( NDl. NDl, NDi) of all parts are connected to one another on the output side and form the output of the comparator ( VG) . 3. Safety circuit according to claim 1, characterized in that the displacement pulse generator (VPR) consists of a pulse generator (PR) whose pulse directly or indirectly controls a bistable multivibrator (BKl in Fig. 4 or Fig. 2), on their equivalent and complementary output each one with one of the two shift lines (VSl or VSl) connected on the output side (5Ll, SLl in Fig. 2, 5L10, 5L2 in Fig. 4) with an associated bistable control switch (SSRl, SSRl) is connected, the control switches (SSRl, SSRl) brings the two visual means (SLl, SLl in Fig. 2; 5L10, 5L2 in Fig. 4) into the operative position for outputting the shift pulses (71, 711) at the first shift pulse of the two shift pulses (71, 711) and that a switchable control shift register (551, Fig. 2; 552, Fig. 4) is provided when outputting displacement pulses, which after output of / i displacement pulses via one of the two holding means (5Ll or SLl, Fig. 2; 5L10 b / w. 5L2, Fig. 4) this switches off with the help of the associated control switch (55Ä1 or 55Λ2). 4. Safety circuit at least according to claim 2, characterized in that for: the comparator ( VG) a test circuit [PSG) with a three-stage control unit (SK) is provided, which can be switched on with the aid of a switch-on command in its first stage (SKI) The output side is connected to the set / and reset inputs (/ 4124, / 1114, A105) of the individual binary levels (All, Al 1, A 10) of the two circulating registers so that the number 2 "-2 is set in the two circulating registers that the control unit (SK) can be set to the second stage (5A.2) after the first stage (SKI) has been activated and the switch-on command is still present with the aid of a feedback branch, which on the output side for both accumulators (Al, Al in Fig. 1) and the displacement pulse generator (VPR) triggers a test counting pulse to set the number!? " - 1 and ITIG ausgangssi-connected to the delayed adjusting the basic position of the Siörungsmcldungsspeichers (SR) connected to the control unit (SK) is such that when adjusting the basic position of the Störungsmeldungsspcichers (SR) in still present Einschallbefehl the third stage (ski) of Control unit (SK) becomes effective and also triggers a test zab'.impulse to set the number 2 "(Fig. 6).