DE2352329B2 - SEMICONDUCTOR COMPONENT AND METHOD FOR ITS PRODUCTION - Google Patents

SEMICONDUCTOR COMPONENT AND METHOD FOR ITS PRODUCTION

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Publication number
DE2352329B2
DE2352329B2 DE19732352329 DE2352329A DE2352329B2 DE 2352329 B2 DE2352329 B2 DE 2352329B2 DE 19732352329 DE19732352329 DE 19732352329 DE 2352329 A DE2352329 A DE 2352329A DE 2352329 B2 DE2352329 B2 DE 2352329B2
Authority
DE
Germany
Prior art keywords
layer
polyimide resin
resin layer
electrode
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19732352329
Other languages
German (de)
Other versions
DE2352329A1 (en
DE2352329C3 (en
Inventor
Masami Kokubunji Tokio; Abe Akira Takasaki Gunma; Harada Seiki Hachioji; Sato Kikuji Kokubunji; Tokio; Takagi Takeshi Takasaki Gunma; Kamoshita Genichi Koganei; Oya Yuichiro Kodaira; Saiki Atsushi Musashimurayama; Tokio; Tomono (Japan)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2352329A1 publication Critical patent/DE2352329A1/en
Publication of DE2352329B2 publication Critical patent/DE2352329B2/en
Application granted granted Critical
Publication of DE2352329C3 publication Critical patent/DE2352329C3/en
Expired legal-status Critical Current

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    • HELECTRICITY
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    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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Description

(( /COx /COx / CO x / CO x

—4-R'—N R N-—4-R'-N R N-

in der die Reste R' und R aromatische Reste sind und mit durch die SiO2-Schicht (23) und durch die Polyimidharz-Schicht (24) auf die Oberfläche des Halbleiterkörper (20) hindurchgreifenden Anschlußelektroden (25, 28; 39, 40), dadurch gekennzeichnet, daß die Baugruppen die spezielle Strukturin which the radicals R 'and R are aromatic radicals and with through the SiO2 layer (23) and through the Polyimide resin layer (24) on the surface of the semiconductor body (20) extending through connection electrodes (25, 28; 39, 40), characterized in that the assemblies have the special structure

COx /COx /COx /COx CO x / CO x / CO x / CO x

/ Ar, N-Ar1-N Ar4 N-/ Ar, N-Ar 1 -N Ar 4 N-

/ / ^CO7 ντοχ Vox / / ^ CO 7 ν το χ Vo x

N-CN-C

-An-At

C-NC-N

Il οIl ο

aufweisen und die Reste Ar1 und Ar3 vom Benzol, Diphenyläther, Naphthalin, Diphenylsulfon und Di-(phenoxyphenyl)-sulfon abgeleitete Gruppen und die Reste Ar2 und Ar4 vom Benzol, Diphenyläther und Benzophenon abgeleitete Reste sind.and the radicals Ar 1 and Ar3 are groups derived from benzene, diphenyl ether, naphthalene, diphenyl sulfone and di- (phenoxyphenyl) sulfone and the radicals Ar2 and Ar 4 are radicals derived from benzene, diphenyl ether and benzophenone.

2. Halbleiterbauelement nach Anspruch 1, dadurch gekennzeichnet, daß die Reste An und An vom Diphenyläther abgeleitete Gruppen, der Rest Ar2 eine vom Benzol abgeleitete Gruppe und der Rest Ar4 eine vom Benzophenon abgeleitete Gruppe sind.2. Semiconductor component according to claim 1, characterized in that the radicals An and An are derived from diphenyl ether groups, the radical Ar 2 is a group derived from benzene and the radical Ar4 is a group derived from benzophenone.

3. Halbleiterbauelement nach Anspruch !,gekennzeichnet durch eine Polyimidharz-Schicht (24), erhalten durch Polykondensation von 5 Mol-% 4,4'-Diaminodiphenyläther-3-carbonsäureamid) 45 Mol-% 4,4'-Diaminodiphenyläther, 25 Mol-% Pyromellitsäuredianhydrid und 25 Mol-% 3,3',4,4'-Benzophenontetracarbonsäuredianhydrid. 3. Semiconductor component according to claim!, Characterized by a polyimide resin layer (24), obtained by polycondensation of 5 mol% 4,4'-diaminodiphenyl ether-3-carboxamide ) 45 mol% 4,4'-diaminodiphenyl ether, 25 mol % Pyromellitic dianhydride and 25 mole% 3,3 ', 4,4'-benzophenone tetracarboxylic dianhydride.

4. Halbleiterbauelement nach einem der Ansprüche 1 bis 3, gekennzeichnet durch eine zwischen der SiO2-Schicht (23) und der Polyimidharz-Schicht (24) eingefügte Grundierung (36) aus einem organischen Material, wie eine Aminosilanverbindung oder eine Epoxysilanverbindung.4. Semiconductor component according to one of claims 1 to 3, characterized by a primer (36) made of an organic material, such as an aminosilane compound or an epoxysilane compound, inserted between the SiO 2 layer (23) and the polyimide resin layer (24).

5. Halbleiterbauelement nach Anspruch 4, dadurch gekennzeichnet, daß die Grundierung (36) auch zwischen den Anschlußelektroden (25, 28; 39, 40) und der Polyimidharz-Schicht (24) aufgebracht ist.5. Semiconductor component according to claim 4, characterized in that the primer (36) also is applied between the connection electrodes (25, 28; 39, 40) and the polyimide resin layer (24).

6. Halbleiterbauelement nach einem der Ansprüche 1 bis 5, gekennzeichnet durch eine Dicke der Polyimidharz-Schicht (24) von 2 bis 15 μίτι.6. Semiconductor component according to one of claims 1 to 5, characterized by a thickness of the Polyimide resin layer (24) from 2 to 15 μίτι.

7. Verfahren zur Herstellung eines Halbleiierbauelementes nach einem der Ansprüche 1 bis 6, bei dem eine Polyimidharzlösung auf die SiO2-Schicht aufgebracht wird, wobei sich die Vorrichtung zum Aufbringen der Lösung und der Halbleiterkörper relativ zueinander drehen, bei dem die Lösung durch Erwärmen ausgehärtet wird, bei dem die Polyimidharz-Schicht und die SiO2-Schicht geätzt werden, so daß Öffnungen für die Anschlußelektroden gebildet werden und bei dem Elektrodenmetall innerhalb der7. Method of manufacturing a semiconductor component according to one of claims 1 to 6, in which a polyimide resin solution is applied to the SiO2 layer is applied, wherein the device for applying the solution and the semiconductor body rotate relative to each other, in which the solution is hardened by heating in which the polyimide resin layer and the SiO2 layer is etched so that openings for the connection electrodes are formed and in the case of the electrode metal within the

3535

4040

4545

5555

6o öffnungen abgelagert wird, dadurch gekennzeichnet, daß der Halbleiterkörper (20) beim Aufbringen der Lösung gedreht wird, daß die Polyimidharz-Schicht (24) mit einem Sauerstoffplasma geätzt wird und daß das Elektrodenmetall unter Drehung des Halbleiterkörpers (20) aufgedampft oder aufgestäubt wird. 6o openings is deposited, characterized in that the semiconductor body (20) is rotated when the solution is applied, that the polyimide resin layer (24) is etched with an oxygen plasma and that the electrode metal is evaporated or sputtered while rotating the semiconductor body (20).

8. Verfahren zur Herstellung eines Halbleiterbauelementes nach Anspruch 5, bei dem eine Polyimidharzlösung auf die SiO2-Schicht aufgebracht und durch Erwärmen ausgehärtet wird, bei dem die gebildete Polyimidharz-Schicht geätzt wird, bei dem in der SiO2-Schicht öffnungen für die Anschlußelektroden gebildet werden und bei dem Elektrodenmetall innerhalb der öffnungen abgelagert wird, dadurch gekennzeichnet, daß zunächst in der SiO2-Schicht (23) öffnungen für die Anschlußelektroden (39, 40) gebildet werden, daß dann das Elektrodenmetall auf die SiO2-Schicht (23) aufgebracht und so geätzt wird, daß über die Oberfläche der SiO2-Schicht (23) überstehende Elektroden (39, 40) mit trapezförmigem Querschnitt entstehen, daß dann die Oberfläche der SiO2-Schicht (23) und der Elektroden (39, 40) grundiert und auf die Grundierung (36) die Polyimidharz-Schicht (24) aufgebracht wird und daß anschließend die Polyimidharz-Schicht (24) mit einem Sauerstoffplasma gleichmäßig so weit abgetragen wird, bis die obere horizontale Fläche der Elektroden (39, 40) in der Ebene der Oberfläche der Polyimidharz-Schicht (24) freiliegt.8. A method for producing a semiconductor component according to claim 5, in which a polyimide resin solution is applied to the SiO 2 layer and cured by heating, in which the polyimide resin layer formed is etched, in which openings for the connection electrodes are formed in the SiO2 layer and is deposited in the electrode metal within the openings, characterized in that openings for the connection electrodes (39, 40) are first formed in the SiO 2 layer (23), and then the electrode metal is applied to the SiO 2 layer (23) is applied and etched in such a way that electrodes (39, 40) protruding over the surface of the SiO 2 layer (23) with a trapezoidal cross-section are formed so that the surface of the SiO 2 layer (23) and the electrodes (39, 40) primed and the polyimide resin layer (24) is applied to the primer (36) and that then the polyimide resin layer (24) is evenly removed so far with an oxygen plasma d until the upper horizontal surface of the electrodes (39, 40) is exposed in the plane of the surface of the polyimide resin layer (24).

Die Erfindung betrifft ein Halbleiterbauelement mit einer auf der Oberfläche des Halbleiterkörpers liegenden SiO2-Schicht und einer über der SiO2-Schicht liegenden Schutzschicht aus einem Polyimidharz mitThe invention relates to a semiconductor device with a lying on the surface of the semiconductor body and a SiO 2 layer overlying the SiO 2 layer protective layer of a polyimide resin having

Baugruppen der allgemeinen StrukturGeneral structure assemblies

/COn /COn \
'-N^ R n4-
/ CO n / CO n \
'-N ^ R n4-

ir. der die Reste R' und R aromatische Reste sind, und mit durch die SiOrSchicht und durch die Polyimidharz-Schicht auf die Oberfläche des Halbleiterköipers hindurchgreifenden Anschlußelektroden.ir. which the radicals R 'and R are aromatic radicals, and through the SiOr layer and through the polyimide resin layer connecting electrodes extending through the surface of the semiconductor body.

Die Polyirüdharz-Schicht dient sowohl dem Schutz des Halbleiterbauelementes als auch der vollautomatischen Verlötung der Anschlußdrähte. Bei diesem Vorgang wird das beschichtete Bauelement zunächst zur Herstellung der Lotperlen in ein Bad mit dem geschmolzenen Lot getaucht. Die Polyimidharz-Schicht darf sich weder bei diesem Tauchen noch beim späteren Aufschmelzen der Lotperlen weder hinsichtlich ihrer chemischen noch hinsichtlich ihrer mechanischen, noch hinsichtlich ihrer elektrischen Kenndaten verändern.The Polyirüdharz layer serves to protect the semiconductor component as well as the fully automatic one Soldering of the connecting wires. During this process, the coated component is initially immersed in a bath with the molten solder to make the solder beads. The polyimide resin layer must not change either with this dipping or with the later melting of the solder balls, neither with regard to their chemical nor in terms of their mechanical, nor change with regard to their electrical characteristics.

Ein Halbleiterbauelement der genannten Art ist aus der DT-AS 17 64 977 bekannt Die Polyimidharz-Schicht wird selbst bei sehr dünner Ausbildung in einem Bad aus geschmolzenem Blei-Zinn-Lot, also bei einer Lottemperatur von etwa 180 bis 2000C, nicht angegriffen und bleibt gut auf der SiOj-Schicht haften. Bei der Verwendung von Loten mit höherer Schmelztemperatur, insbesondere bei Loten mit einer Schmelztemperatur von über etwa 350°C, werden jedoch die elektrischen Kenndaten der Polyimidharzschicht des bekannten Halbleiterbauelementes um Größenordnungen verschlechtert. Dies führt bei dem Bauelement zu einer spürbaren Erhöhung des Leckstroms und beispielsweise bei Transistoren zu einer spürbaren Verkleinerung des Verstärkungsfaktors. Außerdem ist die dielektrische Durchschlagfestigkeit der im bekannten Halbleiterbauelement verwendeten Polyimidharz-Schicht bereits bei Raumtemperatur mit Werter zwischen etwa 250 bis 300 V/μΐη nicht allzu groß.
Einer Automatisierung der Herstellung der Drahtanschlüsse stehen außerdem die Miniaturisierungsbestrebungen auf dem Gebiet der Halbleiterbauelemente entgegen. Die in gebräuchlichen Halbleiterbauelementen zur Herstellung der Drahtanschlüsse zur Verfügung
A semiconductor device of the kind mentioned is known, the polyimide resin layer is even with very thin training in a bath of molten lead-tin solder, that is at a soldering temperature of about 180 to 200 0 C, not attacked from the DT-AS 17 64 977 and adheres well to the SiOj layer. When using solders with a higher melting temperature, in particular with solders with a melting temperature of more than approximately 350 ° C., however, the electrical characteristics of the polyimide resin layer of the known semiconductor component are deteriorated by orders of magnitude. In the case of the component, this leads to a noticeable increase in the leakage current and, in the case of transistors, for example, to a noticeable reduction in the gain factor. In addition, the dielectric breakdown strength of the polyimide resin layer used in the known semiconductor component is not too great, even at room temperature, with values between about 250 to 300 V / μΐη.
The miniaturization efforts in the field of semiconductor components also stand in the way of automating the production of the wire connections. Available in common semiconductor components for making the wire connections

ίο stehenden Elektrodenoberflächen weisen einen Durchmesser im Bereich von etwa 60 bis ΙΟΟμπι auf, Angesichts der aus technischen und wirtschaftlichen Gründen angestrebten Verkleinerung der Oberflächenabmessungen von Halbleiterbauelementen könnte eine Vergrößerung der Anschlußelektrodenoberfläche nur dadurch erreicht werden, daß diese über das Anschlußfenster hinaus auf die äußere Isolatorschicht des Halbleiterbauelementes hinaus ausgedehnt wird. Die gebräuchlichen Werkstoffe für diese Isolatorschichten, einschließlich der aus der DT-AS 17 64 977 bekannten Polyimidharze, weisen jedoch so ungünstige dielektrische und bzw. oder thermische Kenndaten auf, daß sich eine solche Vergrößerung der Anschlußelektrodenoberfläche aus kapazitiven Gründen verbietet.ίο standing electrode surfaces have a diameter in the range of about 60 to ΙΟΟμπι, in view of the reduction in surface dimensions of semiconductor components sought for technical and economic reasons, an enlargement of the connection electrode surface could only be achieved if it extends beyond the connection window onto the outer insulator layer of the semiconductor component is extended beyond. The materials commonly used for these insulator layers, including the polyimide resins known from DT-AS 17 64 977 , have such unfavorable dielectric and / or thermal characteristics that such an enlargement of the connection electrode surface is forbidden for capacitive reasons.

Angesichts dieses Standes der Technik liegt der Erfindung die Aufgabe zugrunde, ein Halbleiterbauelement der eingangs genannten Art zu schaffen, dessen Drahtanschlüsse auch bei hohen Lot- oder Schweißtemperaturen mit relativ einfachen Massenproduktionsgeraten ohne Beeinträchtigung der elektrischen Kenndaten des Bauelementes herstellbar sind.In view of this prior art, the invention is based on the object of a semiconductor component of the type mentioned to create the wire connections even at high soldering or welding temperatures with relatively simple mass production equipment without affecting the electrical characteristics of the component can be produced.

Zur Lösung dieser Aufgabe wird ein Halbleiterbauelement der eingangs genannten Art vorgeschlagen, das erfindurigsgemäß dadurch gekennzeichnet ist, daß die Baugruppen die spezielle StrukturTo solve this problem, a semiconductor component of the type mentioned is proposed which according to the invention is characterized in that the Assemblies the special structure

COn /COn /COn /COn CO n / CO n / CO n / CO n

/ Ar2 N-Ar1-N Ar4 N / Ar 2 N-Ar 1 -N Ar 4 N

/ / Vo7 ^co'/ / Vo 7 ^ co '

N-CN-C

-Ar-Ar

C-N
O
CN
O

aufweisen und die Reste Ari und Ar3 vom Benzol, Diphenyläther, Naphthalin, Diphenylsulfon und Di-(phenoxyphenyl)-sulfon abgeleitete Gruppen und die Reste Ar2 und Ar4 vom Benzol, Diphenylether und Benzophenon abgeleitete Reste sind.and the radicals Ari and Ar 3 are groups derived from benzene, diphenyl ether, naphthalene, diphenyl sulfone and di- (phenoxyphenyl) sulfone and the radicals Ar2 and Ar 4 are radicals derived from benzene, diphenyl ether and benzophenone.

Dieses Halbleiterbauelement kann auch Löttemperaturen im Bereich von 300 bis 450°C, mitunter auch höheren Temperaturen, ausgesetzt werden, ohne daß seine elektrischen oder die dielektrischen Eigenschaften seiner Polyimidharz-Schicht beeinträchtigt werden.This semiconductor component can also solder temperatures in the range from 300 to 450 ° C, sometimes also higher temperatures, without affecting its electrical or dielectric properties its polyimide resin layer.

Die Erfindung ist im folgenden anhand von Ausführungsbeispielen in Verbindung mit den Zeichnungen näher erläutert. Es zeigtThe invention is described below using exemplary embodiments in conjunction with the drawings explained in more detail. It shows

F i g. 1 einen gebräuchlichen Planartransistor,F i g. 1 a common planar transistor,

Fig. 2 bis 2b ein Ausführungsbeispiel der Erfindung und seine Herstellung,Fig. 2 to 2b an embodiment of the invention and its production,

F i g. 3 ein zweites Ausführi.'ngsbeispiel der Erfindung,F i g. 3 a second embodiment of the invention,

Fig.4 bis 4b ein drittes Ausführungsbeispiel der Erfindung und dessen Herstellung,4 to 4b a third embodiment of the invention and its production,

F i g. 5 bis 5c ein viertes Ausführungsbeispiel der Erfindung und dessen Herstellung undF i g. 5 to 5c a fourth embodiment of the invention and its production and

Fig. 6 in graphischer Darstellung die Produktionsausbeute bei der Anschlußherstellung als Funktion dei Dicke der Polyimidharz-Schicht.6 shows a graph of the production yield in connection manufacture as a function of dei Thickness of the polyimide resin layer.

Zum besseren Verständnis der Erfindung ist in dei Fi g. 1 zunächst ein gebräuchlicher Planartransistor mi einem Kollektorsubstrat 1, einer Basis 2, einem Emittei 3 und einer Isolatorschicht 4 gezeigt. In Anschlußfen stern, die in der Isolatorschicht 4 geöffnet sind, sind ein« Basiselektrode 5 und eine Emitterelektrode 6 angeord net, an denen der Basisanschlußdraht 7 und dei Emitieranschlußdraht 8 befestigt sind. Der Durchmesse: der Elektroden 5 und 6 liegt, wie vorstehend ausgeführt ge^räuchlicherweise im Bereich von 60 bis 100 μιη. Be Siliciumhalbleiterbauelementen ist die Isolatorschich gebräuchlicherweise eine SiO2-Schicht, die aus techni sehen und wirtschaftlichen Gründen nicht wesentlich dicker als etwa 1 μιη ist. Eine Vergrößerung der /1 Anschlußzwecken zur Verfugung stehenden Oberfläche der Elektroden 5 und 6 über den Durchmesser de; Fenster hinaus auf die Oberfläche der Isolatorschicht < ruft Störkapazitäten zur Basis und zum Emitter hervotFor a better understanding of the invention is in dei Fi g. 1 initially shows a common planar transistor with a collector substrate 1, a base 2, an emitter 3 and an insulator layer 4. In connection windows star, which are opened in the insulator layer 4, a «base electrode 5 and an emitter electrode 6 are angeord net, to which the base connection wire 7 and the emitting connection wire 8 are attached. The diameter of the electrodes 5 and 6 is, as stated above, usually in the range from 60 to 100 μm. In the case of silicon semiconductor components, the insulator layer is usually an SiO 2 layer which, for technical and economic reasons, is not significantly thicker than about 1 μm. An enlargement of the / 1 connection purposes available surface of the electrodes 5 and 6 over the diameter de; Window on the surface of the insulating layer <brings out interference capacitances to the base and to the emitter

Der gleiche Effekt tritt bereits bei der in F i g. 1 gezeigten Lotverteilung bei der Anschlußherstellung auf. Die daraus resultierenden Nachteile werden durch die Erfindung behoben, ohne daß auf eine relativ große Anschlußelektrodenoberfläche, die Grundlage der Massenfertigung ist, verzichtet zu werden braucht.The same effect already occurs with the one shown in FIG. 1 shown solder distribution during connection production on. The disadvantages resulting therefrom are eliminated by the invention, without a relatively large one Terminal electrode surface, which is the basis of mass production, needs to be dispensed with.

Als erstes Ausführungsbeispiel der Erfindung ist in F i g. 2 ein Planartransistor gezeigt. Ein n-Si-Substrat dient als Kollektor. Im Substrat ist in Planartechnik eine p-leitende Basis 21 und in dieser ein η-leitender Emitter 22 ausgebildet. Die Oberfläche des Substrats 20 ist mit einer SiO2-Schicht 23 und diese mit einer Polyimidharz-Schicht 24 bedeckt. Die Polyimidharz-Schicht 24 ist 5 μηι dick. Durch eine öffnung in der Polyimidharz-Schicht 24 und der SiO2-Schicht 23 greift eine Basisanschlußelektrode 25 durch beide Schichten auf den Basisbereich des Transistors durch. Die Basiselektrode 25 besteht aus zwei Metallschichten. Die erste Metallschicht liegt auf der Oberfläche der Transistorbasis und stellt die Verbindung zwischen dieser und der :o zweiten Metallschicht 27 her, die sich zum Teil bis auf die Oberfläche der Polyimidharz-Schicht 24 erstreckt. In gleicher Weise besteht auch eine Emitterelektrode 28 aus einer ersten Metallschicht 29 und einer zweiten Metallschicht 30. Auf den Oberflächen der Elektroden sind ein Basisanschlußdraht 31 bzw. ein Emitteranschlußdraht 32 befestigt.As a first exemplary embodiment of the invention, FIG. 2 shows a planar transistor. An n-Si substrate serves as a collector. A p-conducting base 21 and an η-conducting emitter 22 are formed in the substrate using planar technology. The surface of the substrate 20 is covered with an SiO2 layer 23 and this with a polyimide resin layer 24. The polyimide resin layer 24 is 5 μm thick. Through an opening in the polyimide resin layer 24 and the SiO 2 layer 23, a base connection electrode 25 extends through both layers onto the base region of the transistor. The base electrode 25 consists of two metal layers. The first metal layer lies on the surface of the transistor base and establishes the connection between this and the: o second metal layer 27, which extends in part to the surface of the polyimide resin layer 24. In the same way, an emitter electrode 28 also consists of a first metal layer 29 and a second metal layer 30. A base connection wire 31 and an emitter connection wire 32 are attached to the surfaces of the electrodes.

Der in F i g, 2 gezeigte Transistor wird wie folgt hergestellt: Der Basisbereich 21 wird durch Einditfundieren von Bor in das n-Si-Substrat 20 ausgebildet. Der Emitter 22 wird durch Eindiffundieren von Phosphor in den bordotierten Bereich hergestellt. Anschließend wird die SiO2-Schicht 23 mit dem Basisanschlußfenster und dem Emitteranschlußfenster aufgebracht. Als erste Metallschicht für die Anschlußelektroden werden die Aluminiumschichten 26 und 29 in die Fenster eingebracht (F i g. 2a). Anschließend werden die Oberflächen der SiO2-Schicht 23 und der Aluminiumschichten 26 und 29 mit einer 5 μΐη dicken Polyimidharz-Schicht 24 überzogen. Auf die Polyimidharz-Schicht 24 wird eine Metallmaske 33 aufgebracht, in der an den über den Aluminiumschichten 26 und 29 liegenden Stellen Fenster 34 und 35 geöffnet sind (F 1 g. 2b). Anschließend wird die Polyimidharz-Schicht 24 durch diese Fenster 34 und 35 hindurch so entfernt, daß die Oberflächen der Aluminiumschichten 26 und 29 freiliegen. Nach Entfernen der Maske 33 wird das zweite Elektrodenmetall 27 bzw. 28 in der in F i g. 2 gezeigten Ausbildung unter Herstellung eines elektrischen Kontaktes zu den Aluminiumschichten aufgebracht. Die so hergestellten Anschlußelektroden 25 und 28 erstrecken sich auch auf die Oberfläche der Polyimidharz-Schicht 24 und stellen so eine genügend große Oberfläche zum Aufschweißen oder Auflöten der Anschlußdrähte 31 und 32 zur Verfugung. Aufgrund der hervorragenden und auch unter Löttemperatur nicht verschlechterten dielektrischen Eigenschaften der Polyimidschicht 2 weist das in F i g. 2 gezeigte Halbleiterbauelement keine Streukapazitäten zwischen den Anschlußelektroden und dem Halbleiter auf.The transistor shown in FIG. 2 is produced as follows: The base region 21 is formed by dit-fusing boron into the n-Si substrate 20. The emitter 22 is produced by diffusing phosphorus into the boron-doped area. Subsequently, the SiO2 layer 23 with the base connection window and the emitter connection window is applied. The aluminum layers 26 and 29 are introduced into the window as the first metal layer for the connection electrodes (FIG. 2a). The surfaces of the SiO 2 layer 23 and the aluminum layers 26 and 29 are then coated with a 5 μm thick polyimide resin layer 24. A metal mask 33 is applied to the polyimide resin layer 24, in which windows 34 and 35 are opened at the points above the aluminum layers 26 and 29 (F 1 g. 2b). Then the polyimide resin layer 24 is removed through these windows 34 and 35 so that the surfaces of the aluminum layers 26 and 29 are exposed. After the mask 33 has been removed, the second electrode metal 27 or 28 is in the form shown in FIG. 2 applied with the production of an electrical contact to the aluminum layers. The connection electrodes 25 and 28 produced in this way also extend onto the surface of the polyimide resin layer 24 and thus provide a sufficiently large surface for the connection wires 31 and 32 to be welded or soldered on. Due to the excellent dielectric properties of the polyimide layer 2, which are not impaired even under the soldering temperature, the in FIG. The semiconductor component shown in FIG. 2 does not have any stray capacitances between the connection electrodes and the semiconductor.

Die Polyimidharz-Schicht 24 wird zunächst in Form einer Vorpolymeren-Lösung aufgebracht Eine solche Vorpolymerenlösung wird beispielsweise durch Vorkondensieren eines wie folgt zusammengesetzten Gemisches erhalten:The polyimide resin layer 24 is first applied in the form of a prepolymer solution The prepolymer solution is prepared, for example, by precondensing one composed as follows Get a mixture:

Nichtflüchtige Bestandteile:Non-volatile components:

4,4'-Diaminodiphenyl-4,4'-diaminodiphenyl

äther-3-carbonsäureamid 5 Mol-°/oether-3-carboxamide 5 mol%

4,4'-Diaminodiphenyläther 45 Mol-%4,4'-diaminodiphenyl ether 45 mol%

Pyromellitsäure-dianhydrid 25 Mol-% 3,3',4,4'-Benzophenontetracarbon-Pyromellitic acid dianhydride 25 mol% 3,3 ', 4,4'-Benzophenonetracarbon-

säuredianhydrid 25 Mol-%acid dianhydride 25 mol%

Lösungsmittelbestandteile:Solvent components:

N-Methyl-2-pyrrolidon 50 Gew.-%N-methyl-2-pyrrolidone 50% by weight

N,N-Dimethylacetoamid 50 Gew.-%N, N-dimethylacetoamide 50% by weight

Konzentrationconcentration

der nichtflüchtigen Stoffe 20 Gew.-%of non-volatile substances 20% by weight

Viskosität der Lösung etwa 300 cPSolution viscosity about 300 cP

Wird diese Vorpolymerlösung nach dem Schleuderverfahren bei einer Rotordrehzahl von 5000 min-1 aufgebracht, so wird eine Polyimidharz-Schicht mit einer Dicke von 1 μπι erhalten. Diese Dicke kann durch eine Veränderung der Viskosität der Vorpolymerlösung, durch eine Änderung der Konzentration der nichtflüchtigen Bestandteile, durch eine Änderung der Drehzahl des Rotors oder durch Kombination dieser Maßnahmen eingestellt werden. Je nach den Erfordernissen des Einzelfalls können so Polyimidharz-Schichten im Größenordnungsbereich von 1 bis 10 μΐη hergestellt werden. Die Dicke der Polyimidharz-Schicht beträgt vorzugsweise ca. 5 μΐη.If this prepolymer solution is applied by the centrifugal method at a rotor speed of 5000 min- 1 , a polyimide resin layer with a thickness of 1 μm is obtained. This thickness can be adjusted by changing the viscosity of the prepolymer solution, by changing the concentration of the non-volatile constituents, by changing the speed of the rotor or by a combination of these measures. Depending on the requirements of the individual case, polyimide resin layers in the order of magnitude from 1 to 10 μm can be produced. The thickness of the polyimide resin layer is preferably about 5 μm.

Nach dem Auspolymerisieren der vorstehend angeführten Vorpolymerlösung wird ein Polyimidharz aui der SiOrSchicht gebildet, das Baugruppen der folgenden Struktur besitzt:After the above-mentioned prepolymer solution has polymerized to completion, a polyimide resin is formed The SiOr layer is formed, which has assemblies of the following structure:

(ID(ID

Das öffnen von Fenstern in der Polyimidharz-Schicht erfolgt vorzugsweise unter Verwendung eines Sauerstoffplasmas. Bei Verwendung eines 0,7-kW-Plasmas mit einem Sauerstoffpartialdruck von 0,8mbar und einem Volumenstrom von 3 l/min wird eine 5 μΐη dicke Polyimidharz-Schicht nach 10 min vollständig abgeätzt. Diese Ätzdauer kann durch eine Änderung des Sauerstoffvolumenstroms, des Sauerstoffpartialdrucks und bzw. oder der aufgeprägten Hochfrequenzleistuni eingestellt werdeaWindows in the polyimide resin layer are preferably opened using an oxygen plasma. When using a 0.7 kW plasma with an oxygen partial pressure of 0.8 mbar and a volume flow of 3 l / min is a 5 μm thick Polyimide resin layer is completely etched off after 10 minutes. This etching time can be changed by changing the oxygen volume flow, the oxygen partial pressure and / or the impressed high-frequency power is set

Da das Plasmaätzen unter Verwendung eine Metallmaske 33 erfolgt, ist darauf zu achten, daß dl· Maske entweder deutlich dünner als die unterste! Elektrodenmetallschichten 26 und 29 ausgebildet is oder aus einem Werkstoff besteht, der durch eii Lösungsmittel abgelöst werden kann, das die ElektroSince the plasma etching is carried out using a metal mask 33, it must be ensured that dl Mask either significantly thinner than the bottom one! Electrode metal layers 26 and 29 are formed or consists of a material that is characterized by eii Solvent can be peeled off that the electro

denmetallschichten 26 und 29 nicht angreift. In dem hier beschriebenen Ausführungsbeispiel bestehen sowohl die Elektrodenschichten 26 und 29 als auch die Maske 33 aus Aluminium. Die Maske ist 0,4 μιη dick, während die Elektrodenmetallschichten 26 und 29 1 μηι dick sind. Unter diesen Verhältnissen kann die Maske 33 vollständig abgelöst werden und bleiben gleichzeitig die Elektrodenmetallschichten 26 und 29 in ausreichender Dicke stehen.denmetallschichten 26 and 29 does not attack. In the embodiment described here, there are both Electrode layers 26 and 29 as well as the mask 33 made of aluminum. The mask is 0.4 μm thick, while the Electrode metal layers 26 and 29 are 1 μm thick. Under these conditions, the mask 33 are completely detached and at the same time the electrode metal layers 26 and 29 remain in sufficient Thick standing.

Es ist nicht erforderlich, daß die beiden Metallschicht ten ein und derselben Elektrode aus verschiedenen Metallen bestehen. In dem bier beschriebenen Ausführungsbeispiel bestehen auch die zweiten Elektrodenmetallschichten 27 und 30 aus Aluminium. Sie werden durch Aufdampfen einer Aluminiumschicht auf die Oberfläche der Polyimidharz-Schicht 24 und in deren geöffnete Anschlußelektrodenfenster hinein und anschließendes selektives Ätzen der Aufdampfschicht hergestellt. Um zu gewährleisten, daß die relativ tiefen Fenster in der Polyimidschicht 24 beim Aufdampfen des Aluminiums auch gleichmäßig und vollständig ausgefüllt werden, wird das Halbleitersubstrat 20 während des Aufdampfens vorzugsweise gedrehtIt is not necessary that the two metal layers ten one and the same electrode consist of different metals. In the embodiment described here the second electrode metal layers 27 and 30 also consist of aluminum. You will go through Vapor deposition of an aluminum layer on the surface of the polyimide resin layer 24 and in its opened Connection electrode window into it and subsequent selective etching of the vapor deposition layer. Around to ensure that the relatively deep window in the polyimide layer 24 during the vapor deposition of the aluminum are also evenly and completely filled, the semiconductor substrate 20 is during the vapor deposition preferably rotated

Ein weiteres Ausführungsbeispiel der Erfindung ist in F i g. 3 gezeigt. Dieser Transistor entspricht im wesentli- 2.s chen dem in F i g. 2 gezeigten Transistor und unterscheidet sich von diesem dadurch, daß zwischen der SiO2-Schicht 23 und der Polyimidharz-Schicht 24 eine Haftvermittlerschicht 36 eingefügt ist. Der Haftvermittler enthält Alkoxysilangruppen zur Vermittlung einer chemischen Bindung zu anorganischen Werkstoffen als auch Aminogruppen und bzw. oder Epoxygruppen zur Vermittlung chemischer Bindungen zur Polyimidharz-Schicht. Another embodiment of the invention is shown in FIG. 3 shown. This transistor corresponds in essential 2 .s chen the in F i g. 2 and differs therefrom in that an adhesion promoter layer 36 is inserted between the SiO2 layer 23 and the polyimide resin layer 24. The adhesion promoter contains alkoxysilane groups to mediate a chemical bond to inorganic materials as well as amino groups and / or epoxy groups to mediate chemical bonds to the polyimide resin layer.

Als Werkstoff für die Haftvermittlerschicht 36 können handelsübliche Aminosilane in Form von Lösungen mit Konzentrationen von 0,05 bis 20 Gew.-% dienen. Vorzugsweise wird eine lgew.-%ige Isopropanollösung von N-jS-iAminoäthyO-y-aminopropyl-methyldimethoxysilan zur Herstellung der Haftvermittlerschicht 36 verwendet. Die aufgetragenen Lösungen werden in gebräuchlicher Weise etwa 30 min bei 100° C getrocknet.Commercially available aminosilanes in the form of Solutions with concentrations of 0.05 to 20% by weight are used. A 1% strength by weight isopropanol solution is preferred of N-jS-iAminoäthyO-y-aminopropyl-methyldimethoxysilane used to produce the adhesion promoter layer 36. The applied solutions are usually about 30 minutes at 100 ° C dried.

Das in der F i g. 4 gezeigte Ausführungsbeispiel der Erfindung unterscheidet sich von den in den Fi g. 2 und 3 gezeigten Ausführungsbeispielen im wesentlichen dadurch, daß die Basiselektrode 25 und die Emitterelektrode 28 aus nur jeweils einer Metallschicht bestehen.The in the F i g. The embodiment of the invention shown in FIG. 4 differs from that in FIGS. 2 and 3 embodiments shown essentially in that the base electrode 25 and the emitter electrode 28 consist of only one metal layer each.

Bei der Herstellung der in F i g. 4 gezeigten Struktur wird nach dem Trocknen der Haftvermittlerschicht 36 die zuvor beschriebene Vorpolymerlösung des PoIyimidharzes aufgebracht, bei 1000C getrocknet und anschließend 1 h bei 300° C gehärtet Die Polyimidharz-Schicht ist 8 μπι dick. Auf diese Polyimidharz-Schicht 24 wird dann eine Alumimiummaske 33 mit Fenstern 34 und 35 über dem Basisbereich bzw. dem Emitterbereich ausgebildet (F i g. 4a). Durch Plasmaätzen werden dann durch die Masktnöffnungen 34 und 35 hindurch Fenster in der Polyimidharzschicht bis auf die Oberfläche der SiO2-Schicht geöffnet Durch das Plasmaätzen wird also auch ein Fenster in der Aminosilan-Haftvermittlerschicht 36 geöffnet. Unter Verwendung der so geöffneten Fenster in der Polyimidharz-Schicht wird dann auch in der freiliegenden SiOj-Schicht unter Verwendung gebräuchlicher Ätzmittel, beispielsweise einer fluorwasserstoffsauren Ammoniumfluoridlösung. ein Fenster geöffnet. Auf diese Weise sind schließlich durch die gesamte Schichtstruktur hindurchgreifende Anschlußkontaktfenster 37 für die Basis und 38 für den Emitter geschaffen. Nach Ablösen der Aluminiummaske 33 wird durch Kathodenzerstäubung eine Aluminiumschicht aufgebracht, die auch die Fenster vollständig und unter Herstellung eines elektrischen Kontaktes zur Basis und zum Emitter füllt. Die Aluminiumschichi wird dann unter Ausbildung der Anschlußelektrodenflächen selektiv geätzt. Die Anschlußdrähte 31 und 32 werden dann durch Heißpressen oder Ultraschallschweißen aufgeschweißt. Dabei hält selbst die relativ dicke Polyimidharzschicht relativ hohen Schweißlemperaturen im Bereich von 4500C ohne eine Verschlechterung ihrer dielektrischen Kenndaten stand. Weder tritt eine Rißbildung noch eine Abnahme der Durchbruchspannung auf.In the production of the in F i g. 4 is applied, the structure shown prepolymer of PoIyimidharzes previously described, after drying the adhesive layer 36, dried at 100 0 C and then for 1 h cured at 300 ° C, the polyimide resin layer 8 μπι thick. An aluminum mask 33 with windows 34 and 35 is then formed on this polyimide resin layer 24 over the base region and the emitter region, respectively (FIG. 4a). By means of plasma etching, windows in the polyimide resin layer are then opened through the mask openings 34 and 35 down to the surface of the SiO2 layer. Using the window opened in this way in the polyimide resin layer, common etching agents are then also used in the exposed SiOj layer, for example a hydrofluoric acid ammonium fluoride solution. opened a window. In this way, terminal contact windows 37 for the base and 38 for the emitter that extend through the entire layer structure are created. After the aluminum mask 33 has been detached, an aluminum layer is applied by cathode sputtering, which also completely fills the windows while making electrical contact with the base and the emitter. The aluminum layer is then selectively etched to form the terminal electrode surfaces. The connecting wires 31 and 32 are then welded on by hot pressing or ultrasonic welding. Even the relatively thick polyimide resin layer withstands relatively high welding temperatures in the region of 450 ° C. without any deterioration in its dielectric characteristics. Neither cracking nor a decrease in breakdown voltage occurs.

In der F i g. 5 ist schließlich ein weiteres Ausführungsbeispiel der Erfindung ebenfalls am Beispiel eines Planartransistors dargestellt. Die Basiselektrode 25 und die Emitterelektrode 28 bestehen je aus einem im Querschnitt im wesentlichen trapezförmigen Metallsteg 39,40, der an seinem Fuß den elektrischen Kontakt zur Basis bzw. zum Emitter herstellt und dessen obere Stirnfläche in der Oberfläche der Polyimidharz-Schicht 24 freiliegt und dort elektrisch leitend mit Anschlußplättchen 41, 42 verbunden ist Die Haftvermittlerschicht ist nicht nur zwischen die SKVSchicht 23 und die Polyimidharz-Schicht 24 eingefügt, sondern umschließt auch die mit der Polyimidharz-Schicht in Berührung stehenden Seitenflächen der Elektrodenstege 39,40.In FIG. Finally, FIG. 5 is a further exemplary embodiment of the invention, also using the example of one Planar transistor shown. The base electrode 25 and the emitter electrode 28 each consist of an im Cross-section of essentially trapezoidal metal web 39.40, the electrical contact to the Base or to the emitter produces and its upper end face in the surface of the polyimide resin layer 24 is exposed and there electrically conductive with connection plate 41, 42 is connected. The adhesive layer is not only between the SKV layer 23 and the polyimide resin layer 24 is inserted, but also encloses the one with the polyimide resin layer in Contacting side surfaces of the electrode webs 39,40.

Bei der Herstellung dieses Bauelementes wird in der Weise verfahren, daß die Substratoberfläche zunächst mit einer S1O2-Schicht bedeckt wird, in der dann Fenster zur Basis und zum Emitter geöffnet werden. Auf diese Struktur wird eine 5 μπι dicke Aluminiumschicht niedergeschlagen. Durch selektives Ätzen ν orden die in F1 g. 5a gezeigten Eiektrodenstege 3S und 40 auf der Basis und dem E'.mitter ausgebildet. Die erhaltene Struktur wird auf ihrer gesamten Oberfläche mit einer Aminosilan-Haftvermittlerschicht 36 überzogen. Auf diese Schicht wird dann in der beschriebenen Weise unter Drehung der Halbleiterstruktur eine schließlich 6 μιη dicke Polyimidharzschicht aufgebracht (Fig. 5b). Durch Ätzen mit einem Sauerstoffplasma wird die erhaltene Struktur gleichmäßig so weit abgetragen, bis die oberen Stirnflächen der Elektrodenstege 39, 40 in der Oberfläche der Polyimidharz-Schicht 24 freiliegen Die erhaltene Struktur wird schließlich mit Aluminium bedampft und unter Ausbildung der Anschlußplättcher 41, 42 selektiv geätzt. Nach Befestigen der Anschluß drähte 31 und 32 wird die in F i g. 5 gezeigte Struktui erhalten.In the manufacture of this component, the procedure is that the substrate surface is initially is covered with an S1O2 layer, in which then window to the base and to the emitter. A 5 μm thick aluminum layer is applied to this structure dejected. By selective etching ν the in F1 g. 5a shown Eiektrodenstege 3S and 40 on the Base and the E'.mitter formed. The structure obtained is on its entire surface with a Aminosilane adhesion promoter layer 36 coated. This layer is then applied in the manner described while rotating the semiconductor structure, a finally 6 μm thick polyimide resin layer is applied (FIG. 5b). By etching with an oxygen plasma, the structure obtained is removed evenly until the upper end faces of the electrode webs 39, 40 are exposed in the surface of the polyimide resin layer 24 The structure obtained is finally vapor-deposited with aluminum and the connection plates are formed 41, 42 selectively etched. After attaching the connecting wires 31 and 32 is the in F i g. 5 shown structure obtain.

Um eine möglichst gute Oberflächenausbildung zi gewährleisten, wird die Polyimidharz-Schicht 24 vor zugsweise so dick ausgebildet, daß sie die mit den Haftvermittler beschichteten Elektrodenstege gut be decktIn order to ensure the best possible surface formation zi, the polyimide resin layer 24 is in front preferably made so thick that they be well coated with the adhesion promoter electrode webs covers

Die Polyimidharz-Schicht 24 besteht vorzugsweisi aus einem Polymer der allgemeinen chemischen Forme I. in der Ar1 eine Diphenyläthergruppe, Ar? einei Benzolring. Ar3 eine Diphenyläthergruppe und Ar4 eini Benzophenongruppe bedeuten.The polyimide resin layer 24 preferably consists of a polymer of the general chemical formula I. In which Ar 1 is a diphenyl ether group, Ar? a benzene ring. Ar 3 denotes a diphenyl ether group and Ar 4 denotes a benzophenone group.

Die Polyimidharz-Schicht 24 kann statt mit einen Sauerstoffplasma auch chemische selektiv geätz werden. Nach dem Auftragen der Vorpolymerlösuni und einer Wärmebehandlung des nassen Überzugs voi einer Stunde bei 160°C wird das Lösungsmittel de Beschichtung weitgehend verdampft, ohne daß daThe polyimide resin layer 24 can also be selectively etched chemically instead of with an oxygen plasma will. After applying the prepolymer solution and a heat treatment of the wet coating voi one hour at 160 ° C, the solvent is de Coating largely evaporated without being there

Polyimid bereits voll ausgehärtet ist. In diesem noch nicht auskondensierten Zustand läßt sich die Schicht mit 40- bis 8Ogew.-°/oiger Hydrazinlösung gut ätzen. Durch eine anschließende Wärmebehandlung von jeweils einer Stunde bei 2000C und anschließend 3000C wird das Polyimid vollständig ausgehärtet und weist die gleichen Eigenschaften auf wie die in einem Prozeß durchgehärtete und durch das Sauerstoffplasma geätzte Polyimidharz-Schicht. Polyimide is already fully cured. In this condition, which has not yet condensed, the layer can be easily etched with 40 to 80% by weight hydrazine solution. The polyimide is completely cured by a subsequent heat treatment of one hour each at 200 ° C. and then 300 ° C. and has the same properties as the polyimide resin layer which has been hardened through in one process and etched by the oxygen plasma.

Als Elektrodenmaterial in Verbindung mit der ι ο Polyimidharz-Schicht können neben Aluminium auch andere Werkstoffe, insbesondere Titan, Molybdän, Gold, Silber, Kupfer, Chrom und Platin sowie Legierungen dieser Metalle, verwendet werden.As an electrode material in connection with the ι ο polyimide resin layer, in addition to aluminum other materials, especially titanium, molybdenum, gold, silver, copper, chromium and platinum as well Alloys of these metals can be used.

Die Polyimidharz-Schicht hat vorzugsweise eine Dicke von 2 bis 15 μΐη. Aus Gründen der mechanischen Festigkeit beim Herstellen der Drahtanschlüsse sollte die Schichtdicke mindestens 2 μπι und aus Gründen der Ätzbarkeit nicht mehr als 15μΐη betragen. Aus wirtschaftlichen Erwägungen wird eine Dicke für die Polyimidharz-Schicht im Bereich von 3 bis 10 μπι vorzugsweise eingehalten. Der Grund hierfür ist der F i g. 6 zu entnehmen. Bei der automatischen Fertigung beträgt die Produktionsausbeute der Drahtanschlußstufe bei einer Polyimidharz-Schicht von 2 μπι nur 50%, während sie bei einer Schichtdicke von 3 μπι bereits praktisch 100% beträgt.The polyimide resin layer preferably has a thickness of 2 to 15 μm. For the sake of mechanical Strength when making the wire connections, the layer thickness should be at least 2 μπι and for reasons of Etchability should not be more than 15μΐη. the end economic considerations will be a thickness for the polyimide resin layer in the range of 3 to 10 μπι preferably complied with. The reason for this is the fig. 6 can be found. In automatic production is the production yield of the wire connection stage with a polyimide resin layer of 2 μπι only 50%, while it is already practically 100% with a layer thickness of 3 μm.

Statt der zuvor beschriebenen Aminosilane als Haftvermittler können auch Epoxysilane verwendet werden, vorzugsweise /?-(3,4-Epoxycyclo-Instead of the aminosilanes described above as adhesion promoters, epoxysilanes can also be used be, preferably /? - (3,4-Epoxycyclo-

hexyl)-äthyl-trimethoxysilan und y-Glycidoxypropyl-trimethoxysilan. hexyl) ethyl trimethoxysilane and γ-glycidoxypropyl trimethoxysilane.

Zum Beleg des verbesserten Temperaturverhaltens der elektrischen Kenndaten von Halbleiterbauelementen mit der erfindungsgemäßen Polyimidharxschicht wurden in Vergleichsversuchen zwei Serien von Planartransistoren der in Fig.2 gezeigten Struktur hergestellt. Prüflinge einer Serie A haben eine Polyimid-Schicht mit Baugruppen der Formel II, während Prüflinge einer Serie B eine Polyimidharz-Schicht mit Baugruppen der folgenden Formel enthalten: To prove the improved temperature behavior of the electrical characteristics of semiconductor components With the polyimide resin according to the invention, two series of Planar transistors of the structure shown in Figure 2 are produced. Series A specimens have one Polyimide layer with components of the formula II, while test objects of a series B have a polyimide resin layer with assemblies of the following formula included:

Gemessen werden die Stromverstärkungsfaktoren der Prüflinge, also jeweils das Verhältnis des Kollektorstroms zum Basisstrom. Die in der beschriebenen Weise identisch hergestellten Prüflinge werden zunächst bei Raumtemperatur, dann nach einer Wärmebehandlung von 60 min bei 35O0C, dann nach einer anschließenden Wärmebehandlung von 10 min bei 4500C und schließlich nach einer sich daran anschließenden Wärmebehandlung von 3 min bei 5000C gemessen. Die entsprechenden Werte betragen für die Prüflinge A gemäß der Erfindung 58%, 58%, 60% und 59%. Die Vergleichswerte für die Prüflinge B betragen 57%, 57%, 18% und 8%. Die Ergebnisse zeigen, daß das Halbleiterbauelement der Erfindung erforderlichenfalls auch noch bei 500° C verdrahtet werden kann, während beim Vergleichsbauelement beim Verdrahten Temperaturen von höchstens 300 bis 350° C verwendet werden sollten.The current amplification factors of the test items are measured, i.e. the ratio of the collector current to the base current. The samples identically prepared in the manner described are initially at room temperature, then after a heat treatment of 60 minutes at 35O 0 C, then after a subsequent heat treatment of 10 minutes at 450 0 C and finally by a subsequent heat treatment of 3 min at 500 0 C measured. The corresponding values for specimens A according to the invention are 58%, 58%, 60% and 59%. The comparison values for test items B are 57%, 57%, 18% and 8%. The results show that the semiconductor component of the invention can, if necessary, also be wired at 500.degree. C., while temperatures of at most 300 to 350.degree. C. should be used for wiring in the case of the comparative component.

Außerdem wurden an den beiden genannten Polyimidharz-Schichten in einer Schichtdicke von je 1 μιτ die Durchschlagspannungen bei Raumtemperatur ge messen, nachdem die Prüflinge jeweils 5 h bei 250, 350 400 und 4500C wärmebehandelt wurden. Die Durch Schlagfestigkeiten für die Polyir.iidharz-Schichten, wii sie im Halbleiterbauelement der Erfindung verwende werden, betragen in Einheiten von V/μΐη 420, 425, 41C 390 und 340. Die gleichen Werte für die Vergleichsprüf linge betragen 260,280,285,200 und 50.Moreover, polyimide resin layers were at the two mentioned μιτ in a layer thickness of 1 per the breakdown voltages at room temperature ge measured after the samples were heat treated respectively for 5 h at 250, 350 400 and 450 0 C. The impact strengths for the polyamide resin layers as they are used in the semiconductor component of the invention are 420, 425, 41C, 390 and 340 in units of V / μm. The same values for the comparative test specimens are 260, 280, 285, 200 and 50.

Hierzu 4 Blatt ZeichnungenFor this purpose 4 sheets of drawings

Claims (1)

Patentansprüche:Patent claims: 1. Halbleiterbauelement mit einer auf der Oberfläche des Halbleiterkörpers liegenden SKVSchicht und einer über der SiC^-Schicht liegenden Schutzschicht aus einem Polyimidharz mit Baugruppen der allgemeinen Struktur1. Semiconductor component with an SKV layer lying on the surface of the semiconductor body and a protective layer made of a polyimide resin with assemblies of the general structure
DE19732352329 1972-10-18 1973-10-18 Semiconductor component and method for its manufacture Expired DE2352329C3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10358872 1972-10-18
JP47103588A JPS5131185B2 (en) 1972-10-18 1972-10-18

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DE2352329A1 DE2352329A1 (en) 1974-05-02
DE2352329B2 true DE2352329B2 (en) 1977-02-24
DE2352329C3 DE2352329C3 (en) 1977-10-06

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NL163368C (en) 1980-08-15
JPS5131185B2 (en) 1976-09-04
HK29979A (en) 1979-05-18
JPS4962081A (en) 1974-06-15
DE2352329A1 (en) 1974-05-02
NL163368B (en) 1980-03-17
NL7314375A (en) 1974-04-22
MY7900031A (en) 1979-12-31
FR2209218B1 (en) 1978-05-26
GB1414245A (en) 1975-11-19

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Free format text: STREHL, P., DIPL.-ING. DIPL.-WIRTSCH.-ING. SCHUEBEL-HOPF, U., DIPL.-CHEM. DR.RER.NAT., PAT.-ANW., 8000 MUENCHEN