DE2350146C2 - Steuerandordnung für einen digitalen Speicher mit überlappt arbeitenden Speichermoduln - Google Patents

Steuerandordnung für einen digitalen Speicher mit überlappt arbeitenden Speichermoduln

Info

Publication number
DE2350146C2
DE2350146C2 DE2350146A DE2350146A DE2350146C2 DE 2350146 C2 DE2350146 C2 DE 2350146C2 DE 2350146 A DE2350146 A DE 2350146A DE 2350146 A DE2350146 A DE 2350146A DE 2350146 C2 DE2350146 C2 DE 2350146C2
Authority
DE
Germany
Prior art keywords
mms
memory
memory modules
control arrangement
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2350146A
Other languages
German (de)
English (en)
Other versions
DE2350146A1 (de
Inventor
Louis V. Billerica Mass. Cornaro
John L. Sudburry Mass. Curley
Thomas J. Hudson Mass. Donahue
Benjamin S. Boston Mass. Franklin
Wallace A. Nashua N.H. Martland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Publication of DE2350146A1 publication Critical patent/DE2350146A1/de
Application granted granted Critical
Publication of DE2350146C2 publication Critical patent/DE2350146C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Memory System (AREA)
DE2350146A 1972-10-05 1973-10-05 Steuerandordnung für einen digitalen Speicher mit überlappt arbeitenden Speichermoduln Expired DE2350146C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US29541772A 1972-10-05 1972-10-05

Publications (2)

Publication Number Publication Date
DE2350146A1 DE2350146A1 (de) 1974-04-18
DE2350146C2 true DE2350146C2 (de) 1987-02-05

Family

ID=23137616

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2350146A Expired DE2350146C2 (de) 1972-10-05 1973-10-05 Steuerandordnung für einen digitalen Speicher mit überlappt arbeitenden Speichermoduln

Country Status (7)

Country Link
US (1) US3796996A (enExample)
JP (1) JPS5924461B2 (enExample)
CA (1) CA999976A (enExample)
DE (1) DE2350146C2 (enExample)
FR (1) FR2202612A5 (enExample)
GB (1) GB1423698A (enExample)
IT (1) IT994355B (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7415966A (nl) * 1974-12-09 1976-06-11 Philips Nv Werkwijze en inrichting voor het opslaan van binaire informatie-elementen.
US4158227A (en) * 1977-10-12 1979-06-12 Bunker Ramo Corporation Paged memory mapping with elimination of recurrent decoding
JPS559260A (en) * 1978-07-03 1980-01-23 Nec Corp Information processing system
US4280176A (en) * 1978-12-26 1981-07-21 International Business Machines Corporation Memory configuration, address interleaving, relocation and access control system
JPS55110355A (en) * 1979-02-16 1980-08-25 Toshiba Corp Memory board and selection system for it
JPS5676860A (en) * 1979-11-28 1981-06-24 Nec Corp Interleaving system for memory device
US4408305A (en) * 1981-09-28 1983-10-04 Motorola, Inc. Memory with permanent array division capability
US4507730A (en) * 1981-10-01 1985-03-26 Honeywell Information Systems Inc. Memory system with automatic memory configuration
US4636973A (en) * 1982-07-21 1987-01-13 Raytheon Company Vernier addressing apparatus
JPS60205760A (ja) * 1984-03-30 1985-10-17 Fuji Xerox Co Ltd メモリ制御装置
US4754394A (en) * 1984-10-24 1988-06-28 International Business Machines Corporation Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage
US4739473A (en) * 1985-07-02 1988-04-19 Honeywell Information Systems Inc. Computer memory apparatus
US4924375A (en) * 1987-10-23 1990-05-08 Chips And Technologies, Inc. Page interleaved memory access
US5051889A (en) * 1987-10-23 1991-09-24 Chips And Technologies, Incorporated Page interleaved memory access
US5287470A (en) * 1989-12-28 1994-02-15 Texas Instruments Incorporated Apparatus and method for coupling a multi-lead output bus to interleaved memories, which are addressable in normal and block-write modes
JPH0430231A (ja) * 1990-05-25 1992-02-03 Hitachi Ltd 主記憶アドレッシング方式
US5253354A (en) * 1990-08-31 1993-10-12 Advanced Micro Devices, Inc. Row address generator for defective DRAMS including an upper and lower memory device
US5572692A (en) * 1991-12-24 1996-11-05 Intel Corporation Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving
US5522069A (en) * 1993-04-30 1996-05-28 Zenith Data Systems Corporation Symmetric multiprocessing system with unified environment and distributed system functions
US5473573A (en) * 1994-05-09 1995-12-05 Cirrus Logic, Inc. Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
JPH08115592A (ja) * 1994-10-14 1996-05-07 Sega Enterp Ltd データ処理システム、データ処理方法、並びにメモリカセット
US5941775A (en) * 1994-10-14 1999-08-24 Sega Of America, Inc. Data processing system, method thereof and memory cassette
JP3059076B2 (ja) * 1995-06-19 2000-07-04 シャープ株式会社 不揮発性半導体記憶装置
US5809555A (en) * 1995-12-15 1998-09-15 Compaq Computer Corporation Method of determining sizes of 1:1 and 2:1 memory interleaving in a computer system, configuring to the maximum size, and informing the user if memory is incorrectly installed
US5987581A (en) * 1997-04-02 1999-11-16 Intel Corporation Configurable address line inverter for remapping memory
US20030046501A1 (en) * 2001-09-04 2003-03-06 Schulz Jurgen M. Method for interleaving memory
KR101673233B1 (ko) * 2010-05-11 2016-11-17 삼성전자주식회사 트랜잭션 분할 장치 및 방법

Also Published As

Publication number Publication date
JPS5924461B2 (ja) 1984-06-09
GB1423698A (en) 1976-02-04
IT994355B (it) 1975-10-20
CA999976A (en) 1976-11-16
DE2350146A1 (de) 1974-04-18
FR2202612A5 (enExample) 1974-05-03
US3796996A (en) 1974-03-12
JPS4974448A (enExample) 1974-07-18

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Legal Events

Date Code Title Description
OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HONEYWELL BULL INC., MINNEAPOLIS, MINN., US

8339 Ceased/non-payment of the annual fee