DE2348348A1 - DIGITAL WORKING TEACHABLE MATRIX-SHAPED ASSIGNMENT - Google Patents

Description

The invention relates to a digitally working teachable matrix-shaped allocator.

Teachable allocators can be used for classification tasks that occur e.g. in speech recognition, character recognition and the classification of examination material. Such tasks are currently still solved by simulation on the computer. However, extensive classification tasks lead to long computing times and are no longer economical with computers solvable. Computers are not always available for such tasks.

Teachable allocators are known which, in a learning phase, have groups of binary input signals at the columns in memory elements at the crossing points of the matrix and in an optional phase when offering a pattern from the memory content and the assigned input signals across the lines Assign a binary coded meaning to the pattern by means of a digital evaluation circuit.

Such allocators are known from the literature as learning matrices (Cybernetik 1, 1961, pp. 36-45) or networks of adaptive threshold elements (hereinafter referred to as 'ASE') (WESCON 63, Techn. Papers, pt, 7, 1963, p. 1 - 10) became known. These systems order a pattern x = (x _1? ·. ·, X) with binary components x. = +1 a binary coded meaning b = (b ,., ..., b _m ) to. They contain a matrix of weights w,. with k = 1, ..., m and i = 1,

in the optional phase, line sums

7. ss ¹ C "wr V.

k ^ t] ki -x

educated. In the learning matrix, the maximum line total is

v.

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averages and assigns the pattern to this line. For systems off ASE will each line with an associated threshold w, compareL- "

If Z, = w, then the meaning component assigned to this line becomes b, = + 1, otherwise it becomes b, = - 1. Also the summary several threshold outputs through logical gates for the formation of the binary meaning component has become known **

In the learning phase is the meaning or the class affiliation of the pattern known. The weights w,. certain lines adjusted. The learning matrix is the addition of the sample components x. required for weights:

^w ki ^{i = w} ki ^{+ x} i »
For systems from ASE, addition and subtraction are necessary:

^w ki ^{: = W} ki t ^x i.
(: = means »goes over to)

The basic building blocks of these systems are the variable weights. The implementation proposals have become known from the literature, in which a wide variety of physical effects are used to build these elements. So became teachable Allocator with motor-driven potentiometers, with transfluxors and with tape wrapping ring core as weights. These arrangements have the disadvantage that they either work very slowly or the weight adjustment and formation the line sums are complex and additional arrangements are required for connection to digital computers

In recent years, a variety of digital integrated circuits have been developed for digital computers, the are suitable for mass production. These circuits are also suitable for the construction of teachable allocators, since

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In principle, entire assemblies of a teachable allocator can be accommodated in an integrated circuit for which Series production, mature technologies are available and assigners from these circuits directly to digital computers can be connected and controlled by them.

There are digital arrangements for variable weights (IEEE Trans. Comp. C-18, 1969, pp. 699-706) and teachable systems (Electronics, 1966, August 22, pp. 86-93). A pattern recognition device with digital logic has also been proposed (U.S. Patent 3,275,985). This system uses number shift registers as weights, in which the weight is a binary number with a Yor character bit is stored. In an addition device, positive and negative numbers are added. These operations are similar to those in calculating machines and require a relatively high number of components.

The purpose of the invention is to process binary input signals in such a way that that the expenditure on components as low as possible, the processing times short and an adaptation to digital calculating machines is possible,

The invention is based on the object of a digitally working specify instructable matrix-shaped assigner in which the weighting of the components of the input signals and 'the line sum is simplified compared to known systems.

According to the invention, this object is achieved in that for the Weights w,. binary V / R counter (forward-backward counter) with or without counter limit and logic gates for sequential output of the counter can be used. In the In the learning phase, the numbers +1 or -1 assigned to the sample components are added to or subtracted from the count. In the Can not phase the products w,. x. of a line summed up, but the numbers w, increased by a certain amount. x. + N,

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where Ii is the same number for all weights of the matrix and is chosen so that all occurring numbers w, · x. + N can only be positive · The number Ή depends on the number of digits in the up / down counter. If the counter has 2 counting positions, then

TC-1 TC-1

2 is set for N, and the w,. x. + 2 can be formed by logic gates from the outputs of the counters and the associated sample components «When using a binary 4-bit V / R counter with the outputs DCBA and equivalence gates, the result is w,. x. + 2 ^ as a binary number from:

(DHx ₁ ') (CS xp (Bexjp (ASxj)

+ 0 0 0 x!

¹ »

where x 'is the switching signal L for x. = +1 and the switching signal 0 for x. = -1 is.

In the optional phase, only positive numbers then need to be added. With η weights in a line, the line-

TC-1

sum increased by η 2 "". When determining the maximum line total (Learning matrix) is the addition of a constant to all row sums without meaning. Should the instructable assigner for If a system from ASE is used, each increased line sum must be compared with an associated variable threshold which also consists of a binary V / R counter and

K-1

expediently preset to η 2 at the beginning of the learning process becomes

If the line sum is greater than or equal to the threshold, the output signal assigned to the line of the matrix becomes L, otherwise 0, The output signals can be used in the learning phase to adapt the system from ASE. You can also use the output signals several ASE can be combined with logic gates and the adjustment of the weights and threshold in the learning phase in known Way to be modified.

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23A83A8

With the learning matrix, there is also the possibility of changing the values of the To restrict weights to +1 and -1. Then the weighted input signals w,. = -1 is increased by +1, they are closed summing signals always positive and can be read from the counter DCBA of the 4-bit V / R counter through the logical function DSxj are formed.

The invention is to be explained in more detail below using exemplary embodiments. In the accompanying drawings, j

Pig. 1: a simplified block diagram of a teachable matrix-shaped allocator,

2j shows the structure of the weight according to the invention;

3s shows the arrangement for forming and storing the line sum;

4s shows the circuit for reading out the maximum line sum;

5s shows the circuit for comparing the line sums with the associated threshold for a system made up of ASE and

Fig. 6s the feedback of the output signal of an ASE in the Learning phase.

The clock inputs TL contained in FIG. 1, the weights w, ₁ to

, one line are galvanically connected, as are the inputs x. of the weights W ₁ . to w. a column. A pulse L at TL,

X I 1 IuX IC

causes the pattern components x. in the V / R counters 21 of the weights w _v1 to w, of the k-th row are added. In the optional phase , the counters of a line and the sample components arrive sequentially in a linking network V, where w,. X * + 8 is formed and fed to an adder A. For further evaluation, the line total Z is stored in a memory SZ,

Ki IC

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Pig. 2 shows the structure of a weight w,. , consisting of a binary 4-bit V / R counter 21, gates 22 to limit the count and to enter a component x! of the luster. the Gates 23 are used to output the counter status. Lead the Clock line TZ. the state L, then lie at the outputs the AND gate 23 the outputs DCBA of the counter 21. 13er Counter 21 counts one position forward in a known manner, if x! = L and TL, = L becomes, it counts one place backwards, if x! = 0 and TL, = L becomes. If the counter 21 is in the extreme upper counting state, then it does not count at x! = L and TL, = L,

1 IC

likewise it does not count in the extreme lower state at x! = '0 and TL, = L.

-L it

Pig. 3 shows the totalization of lines for the first cell. The Zeilensunnnenspeicher SZ ^ consists of the memory plip-flops 27 and a forward he counts 24, which are initially on Hull. With TZ ₄ J. = L, the UIID gate 23 is used to enter the counter DCBA of the first weight W ₁₁ and the first sample component xl into the link network V ₁

To form W ₁ . xl + 8, the counter status DCBA is passed to the equivalence gates 25 via the OR gates 26. Where x! at the other inputs of the equivalence gates should the weights w,. only assume the values + 1 and - 1, then the upper OR gate 26 and the upper equivalence gate 25 are sufficient: U { SD) = d _k .

At the output of the network V ₁ appears w, .. x '+ 8 as a binary number dcba + OOOc with c = xJ. It goes through the adder A and

ο οι

is transferred to the four flip-flops 27 and the counter 24 with t = L. If TZp = L, then w, ρ xA + 8 is formed and the memory 24; 27 added. IThe TZ, _T = L is then the line _{total Z 1} in the flip-flops 27 and in the 7orwaertszaehler 24. '

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-, 7 -

I-'i ^ v 4 shows the circuit for determining the maximum line sum Z. The memories SZ contain the line sums Z as binary numbers. The memory 28 and the flip-flops 29 are initially at zero. With TY ₁ = L, the binary number is given to the input a of the comparator 32 via the UMD gate 30 and the OR gate 31. (For a better overview, only one line is shown for each binary number.) The content of the memory 28, which is initially 0, is at input b. The state L is present at the output of the comparator 32, since a - b. Z .. is taken over into memory 28 with tV = L and. the flip-flop 29, FF ₁ * switches to L. 3ei TV ₂ = L, Z _{2 is} at the input a of the comparator 32. If Z ₂ = Z ^ (Z ₁ is memory content), then Zp passes through the AND gate 33 into the memory 28, and the flip-flop 29.PF ₂ switches to L. If Z ₂ <Z ₁ , then Z ₁ remains in the memory and the flip-flop 29 »FB * 2 does not switch. Each line sum Z i (k = 1, ·· #, m) is compared with the memory contents and transferred to the memory 28 if it is greater than or equal to the line sum Z i that is in the memory 28. After TV _ffi = L, the largest line total Z ^ is in the memory 28, and the last switched flip-flop indicates which line contains the largest line total.

The threshold value reading is shown in FIG. The line tags Z ^ are in the memories SZ ^, the threshold values w , in the memories _{34With TV 1} = L, the first line sum Z ^ and the associated threshold value W ₁ pass through the UiJD gates 35 and the OR gates 36 - to the comparator 37. If the line sum Z _{1 is} greater than or equal to the threshold value w -, the state L appears at the output and the flip-flop 38. ^ 1 switches. If the line total Z _{1 is} less than the threshold value W ₁ , the flip-flop 38.PP ₁ does not switch. After TV = L, the binary is in the flip-flops 38

I ul j

coded meaning b of the entered pattern. In the learning phase, the b of the individual patterns are given. From the b that is with the offer of a sexton in the learning phase and the given b can be the known adjustment for

- ο -,

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the weights w,. the matrix and the threshold values w _k »

b * = +1 b _k = -1 w _ki j = w _ki -X ₁ (i = 1, ..., n) w _ofci = w _{ok +} 1 b * = -1 b _k = +1 w _ki : = w _{ki +} x _± (i = 1, ..., n) w _ok : = w _ok -1

b * = b _k or any, no adjustment

with the circuit according to Pig. 6 realize. If bj * = b _k , then the state 0 is present at an input of the UITD gate 39 and thus also with TL, = L the state 0 is present at the output. The weights w _k ^ and the threshold w are not adjusted. With antivalence of bi and b, the sample components are dependent on b £ on the weights w ,.
or subtracted.

the weights w ,. and the threshold w _{k of} the k-th row is added

The outputs of these digital systems carry the same signals as the inputs. Therefore, more complicated Systems such as cascade connections can be built from ASE. There can also be several outputs from ASE with logical gates are interconnected.

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Claims (1)

1. Digitally working instructable allocator with input (columns) and lumination lines (rows) connected in a matrix-like manner by weights, the groups of input signals with the components x ^ =. + 1 ^ hcJ [= logical L and X ₁ = -1 BMB "^ Assigning a meaning to xj = logical Q, characterized in that the weights (Wj.) consist of binary K-bit forward-backward counters (21) which are added or subtracted line by line in the learning phase by adding or subtracting the groups of input signals (x ^ ) and are used in the optional phase for the positive and negative weighting (w.) of the input signals (x.) in connection with an arrangement of logic gates (23), each weighted input signal (wj. x.) being used by the logic combination (" V ^) of the dual present counter status w-,. = K ... CBA with x! according to