DE2844125C2 - - Google Patents

Description

The invention relates to a device for evaluating Dual pulse sequences by division according to the preamble of Claim 1.

The task of such a device is often too see that an analog detected by a measuring device value is converted into a time value, which is then replaced by Counting by means of clock pulses in an equi the analog value valent digital value is converted. This principle is used e.g. B. used in analog-digital converters. This is mostly - especially if the result is to be expressed in a unit of measurement - required that the result first be in dual form a division process determined by the unit of measurement throw. The installation of a computer working in the usual way requires considerable effort in terms of both Circuit as well as in terms of operating for each one required time.

DE-OS 22 53 006 describes a digital divider circuit, especially for tachometers, known for binary numbers is provided and in which the dual pulse sequence to be entered gets directly to a digital counter, which in connection with a register for storing the divisor one out of one Binary number adder, a sum register and a binary frequency comparator built-in frequency controller controls. Abge see the considerable logical effort for the binary number The known circuit needs a comparator adder wise great expenditure of time to carry out the individual Operations, being the usual method of dividing by more times subtraction or addition is provided. Furthermore is the well-known circuit only for duadic numbers system suitable.

It is therefore an object of the invention to find another solution Find. The task is solved by the characteristics of the kenn Drawing part of claim 1.

The invention uses a modular counting method for division, in which a switchable divider is connected upstream of the main counter is whose division rate by the divisior and the current Meter reading is determined anew with each new pulse.

The design of the digital counter and the register can any p-adic number system besides the dual system, in particular the decimal system, be based on, before especially the decimal system for the use of the device in measuring instruments is of particular importance. Also for the ver The invention is the use of the decimal system particularly suitable.

Embodiments of the invention are characterized in the subclaims draws.

The following Be serve to understand the invention traditions.  

If a number M is to be divided by a divisor D , the following applies

M = D · Q (1)

where Q is the quotient we are looking for. In order to simplify the consideration, the decimal system is used and it is assumed that D is a decimal fraction with only one place d Stelle before the decimal point and k -1 places behind the decimal point, so that D is in the form

D = d ₀ + d ₁: 10+ d ₂: 100+. . . + d _{k -1} : 10 ^{k -1} (2)

can be represented. Together with (1) then follows:

M = d ₀ · Q + d ₁ · Q: 10+ d ₂ + Q: 100+. . . + D _{k -1} · Q: 10 ^{k -1} (3)

or reshaped

M = (d ₀ + 1) · [ d ₁ · Q : 10+ d ₂ · Q : 100+. . . + d _{k -1} · Q : 10 ^{k -1} ]
+ d ₀ · [(10- d ₁-1) · Q : 10+ (10- d ₂-1) · Q : 100+. . . + (10- d _{k -1} ) · Q : 10 ^k ] (4)

or abbreviated:

M = (d ₀ + 1) · f (d ₁, d ₂, ... D _{k -1} ) + d ₀ · g (d ₁, d ₂, ... D _{k -1} ). (5)

With regard to those based on the dual principle Frequency divider underlying operation results the following statement:

The division can be carried out with the divisor D by alternately changing the frequency divider to the divider (d ₀ + 1) and to the divider d nach in the course of the vision in accordance with the respective function value of f and g a pulse sequence to be divided consisting of M clock pulses is passed over the frequency divider.

It should be noted that a representation according to (5) is also correct if D is an arbitrary number and not just a decimal fraction with a decimal place. It is also possible to use the divisors d ₀ and (d ₀-1) instead of the divisors d ₀ and (d ₀ + 1), resulting in a representation analogous to the representation (5). Such a Dar finally applies to the digital digits d ₀, d ₁,. . . in any p-adic number system.

The selector is now to determine the values of the functions f and g belonging to this, based on the value stored in the register for the divisor D, and the frequency divider, depending on the values for these two functions, alternately to the divider value d ₀ and the divider value (d ₀ +1) switch. To determine the function values, for. B. a computer or - if only the use of a single value for the divisor D is seen before - a fixed circuit dimensioned according to this value can be used.

However, it is preferably provided in the further embodiment of the invention that, with the exception of the memory stage used to store the first digital position d ₀ of the divisor D, all the other memory stages of the register are provided for controlling a selector each, in addition that one of the number of these register memories stages equal number of successive to the count input memory stages of the digital counter is also provided for loading one of these selectors, that the second digital position of the D visor D assigned selector to control the frequency divider and each of the other selectors to control that selector , which is assigned to the digital position d _{i of} the divisor D which lies immediately before the digital position d _{i -1 which} is assigned to the respective controlling selector.

The selectors preferably have the same structure, which is otherwise based on the number system used for the division. An embodiment for the decimal system is shown in Fig. 2, an execution example for the dual system in Fig. 7.

Embodiments of the invention will now be described with reference to FIGS. 1-7.

In Fig. 1 the basic circuit diagram of an arrangement according to the invention is shown.

A number M to be divided is represented by a sequence comprising M individual pulses of identical equidistant clock pulses. It is placed at the input of the frequency divider FT , the z. B. consists of a number of successive and mutually identical bistable flip-flops with two signal outputs each, with twice the number of these flip-flops equal to the maximum value of the first digital digit d ₀ of the divisor D , that is to say on the basis of the decimal system of the number 9. With a suitable control, it is possible to switch either the signal output of the frequency divider FT corresponding to the digital number d ₀ or the digital output (d ₀ + 1) to the counting input of the digital counter DZ .

The digital counter DZ consists of a number m of memory stages Z _{m -1} , Z _{m -2} , Z _{m -3} , connected in series. . . Z _{m - k +1,.} . . Z _k . . . Z ₁, Z ₀. If the counter DZ is designed as a dual counter, the memory stages are each provided by a single bistable multivibrator with two signal inputs and two signal outputs, via which the combination of these individual flip-flop cells to form the chain forming the counter is given. As bistable flip-flops z. B. Master-slave flip-flops, in particular special toggle flip-flops used.

If the structure of the arrangement is to be based on a different number system, then the individual memory stages, i.e. the counter stages of the digital counter DZ , consist in a known manner of correspondingly complicated combinations of bistable flip-flops such that the individual memory stages are one of the basic number of the selected number system has a corresponding number of different stable operating states. When using the decimal system, the individual memory stage or counter stage Z _{i should have} 10 different operating states corresponding to the numbers 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9.

Similar to the frequency divider FT , the digital outputs DZ have the signal outputs of the individual memory stages not only connected to the corresponding signal inputs of the following memory stages, but also individually to the outside so that the respective counter can be read. Each counter level can be reset to its initial state via a special reset input.

If only one divisor D is provided, the register RG can consist of a programmed read-only memory. Otherwise a read / write memory is recommended. The register RG consists of a number k of memory stages, ie the register cells R ₀, R ₁, R ₂,. . . R _{k -1} , in each of which the individual digital digits d ₀, d ₁, d ₂,. . . d _{k -1 of} the divisor D corresponding information can be stored. The register stage R ₀ used to hold the first digital digit d ₀ is switched in such a way as to define those outputs of the frequency divider FT which, due to the stored divisor D or its first digital digit d ₀, must be connected to the counting input of the digital counter DZ are.

Finally, k -1 selectors S ₁, S ₂,. . . S _{k -1} seen before, which are constructed in the same way and which have the task of determining the two divisor values d ₀ and (d ₀ + 1) determined by the content of the first register cell R nach, in accordance with the by the in the other Re Gister cells R ₁, R ₂,. . . R _{k -1} stored values of the functions f and g according to (4) by connecting the signal outputs of the frequency divider FT corresponding to the values d ₀ and d ₀ + 1 to the counting input of the digital counter DZ .

For this purpose the register cell R ₁ storing the second digital digit d ₁ of the divisor D is connected with its signal output to the one input of the first selector S ₁, the second input of which is immediately following the counting input of the digital counter DZ counting stage Z _{m - 1} (lowest-value p-ade) is applied. The output of the selector S ₁ provides a signal C ₁ which is zero if the frequency divider FT is only to divide by d ₀ and which is one if the divider (d ₀ + 1) is to be used. The signal C ₁ thus controls the choice of one of the two divider values d ₀, (d ₀ + 1), which is to come into play with the next cycle of the pulse sequence M. The occurrence of the signal value of C ₁ is partly by comparing the information stored in the counting stage Z _{m -1} with the pending value in the second register storage stage R ₁ of the two-th digital digit d ₁ and partly by one of the second selector S. ₂ delivered control signal C ₂ (Carry C ₂) be true.

The second selector S ₂ is on the input side by the third digital digit d ₂ of the divisor D storing register level R ₂ and the memory level Z _{m -2} following the counting input of the digital counter as the second counter level and possibly by a third selector S ₃ output signal C ₃ (Carry C ₃) determined.

The same applies analogously to the i- th selector S _i that from the counter DZ through its i-th counting stage Z _mi following the counting input, from the register RG through through its memory stage R _i and containing the digital position d _{i of} the divisor D. the signal supplied by the selector S _{i +1 is} controlled C _{i +1} and its output is provided for controlling the selector S _{i -1} to generate a signal C _i (carry C _i ).

The division of a sequence of M equidistant dual pulses pending at the input of the frequency divider FT is now achieved by appropriately switching the frequency divider FT to the divider values d ₀ and (d ₀ + 1) while passing through the pulse sequence, if one switches over to the two divider values in accordance with the following scheme resulting from relationships (4) and (5):

Under ten states of the decade of counters Z _{m -1} (corresponds to 10 output pulses from FT) , the selector S ₁ d ₁ times the output pulse C ₁ = 1, (10- d ₁-1) times the output pulse C ₁ = 0 and once that value of the output pulse C ₂ that is currently pending at the output of the selector S ₂.

Under ten states of the decade of counters Z _{m -2} (corresponds to 100 output pulses from FT) , the selector S ₂ supplies the output pulse C ₂ = 1 in total d ₂ times and the output pulse C ₂ = 0 in total (10- d ₂-1 ) times both that value of the output pulse C ₃, which is pending at the output of the selector C ₃.

Under 10 states of the decade of counters Z _{mk -1} (corresponds to 10 ^{k -1} output pulses from FT) , the selector S _{k -1} d _{k -1} times delivers the output pulse C _{k -1} = 1 and (10- d _{k -1} ) times the pulse C _{k -1} = 0.

Each output pulse C _i is to be evaluated as a carry, through which the information content of the following selector stage S _{i -1 is} acted upon either by the information "one" or by the information "zero".

It should also be noted that, in accordance with the relationship (4) in the considerations just made, the decimal system and thus an embodiment of the memory stages of the register RG and the digital counter DZ is based on this number system.

So that any number of pulses M delivers a result Q of division by D accurate to k digital digits, the division by (d ₀ + 1) must be distributed as evenly as possible over the period in which the pulse train M is passed through the frequency divider FT . For this purpose, in a further development of the invention, each of the selectors provided is designed as comparison logic, the internal structure of which corresponds to the case for the application of the decimal system as the basis for the construction of the memory stages in the digital counter DZ and in the register RG in FIG. 2, provides uniformly distributed over the ten states of a decade and in accordance with the pulse diagram according to Fig. 3, which lead to a carry C _i = 1 pulses.

In the digital counter DZ constructed as a decimal counter, one counter stage is provided per decade, each of which has four outputs to which dual signals are applied, which display the counter reading of the counter stage in a binary-coded decimal code. In the i- th counter stage Z _mi, these are the outputs q _{mi , 1} , q _{mi , 2} , q _{mi , 4} and q _{mi , 8} , the last output q _{mi , 8} also being used to control the following counter stage, ie the next decade i +1 is provided.

The structure of the individual counter stages Z _{mi of} the decimal counter DZ can, for. B. corresponding to FIG. 4. One has four identical flip-flop cells FF ₁- FF ₄ per counter stage, the clocks to be counted being present at the signal inputs of all flip-flop cells at the same time if the counter, as in the example, is constructed as a synchronous counter. The clocks to be counted are in the case of the first memory stage Z _{m -1} directly from the frequency divider FT , in the case of the other counter stages Z _{m -2} ,. . . Z _{mk +1} , Z _mk,. . . Z _{m is} supplied by the counting stage adjacent in the direction of the counting input. In order to ensure the synchronicity of the counting method and also to make the counter a decimal counter, the four AND gates U ₁, U ₂, U ₃ and U ₄ are provided as an OR gate O , which is shown in FIG. 4 obviously are switched. The clock pulses serving to apply the i- th counter stage Z _mi are in the case i = 1 from the outputs of the frequency divider FT set via the highest digital digit d ₀ of the divisor D and in the case i <1 in accordance with the statements just made by the q _{mi +1.8} output of the (i -1) th counter stage Z _{mi +1} delivered. As flip-flop cells FF ₁- FF ₄ master-slave flip-flop cells are preferably used ver.

Has the register RG each for receiving a Digi talstelle d ₀, d ₁,. . . d _{k -1} serving (and in the example also designed according to the decimal system) memory stages R ₀, R ₁,. . . R _{k -1} , each of these register memory stages R _i with i <1 is assigned a selector S ₁, which on the other hand is controlled by the memory stage or counter stage Z _{mi of} the decimal counter DZ . (The index i runs through the numbers 1 to k -1 both in the case of the storage stages R _{i of} the register and in the case of the storage stages of the digital counter DZ) . Accordingly, the memory stages Z _{m -1} and R ₁ belong together via the selector S ₁. Only the register memory stage R ₀ used to store the first digital position d ₀ of the divisors D is, as already stated above, switched in a different manner.

As already mentioned, the individual selectors S _i are formed as identical logic comparison circuits, the circuit diagram of which is shown in FIG. 2.

The circuit is constructed in the interest of a realization in MOS technology exclusively from NOR gates and inverters, a total of 13 NOR gates N ₁- N ₁₃ and two inverters IN ₁ and IN ₂ being used. The circuit also has 13 logic inputs, each of which is designated in accordance with the signals intended to be applied to it.

The signal inputs of the selector controlled by the memory stage Z _mi assigned to the respective selector S _i are q _{mi , 1} , q _{mi , 2} , q _{mi , 4} , q _{mi , 8} and the associated inverted signal inputs

designated. The inputs q _{mi , 1} to q _{mi , 8} correspond to the signal outputs of the i- th counter stage Z _mi and thus the outputs of the flip-flops FF ₁- FF ₄. The inputs of the selector S _i marked in the same way but marked with a dash are each connected to the same flip-flop but with its inverted output. The signals q _{mi , 1} each carry the lowest, the signals q _{mi , 8} each the highest dual digit in the relevant decimal decade.

The register RG associated inputs of the selector S _{i, k} of units each one of the provided-register R ₁ to R _-1, with the exception of the register storage stage R ₀ set so that so that for controlling the Selek tors S _i in accordance with their order in divisor D is the 2nd, 3rd, etc. and finally the k- th digit (= decimal place) of divisor D. It should be noted that depending on the total number k of memory cells R ₀, R ₁, provided for the storage of divisors D. . . R _{k -1 contains} the memory unit R _{k -1} the least significant digital digit and R ₀ the most significant, ie first digital digit d ₀. The information corresponding to the relevant digital position of divisor D has the name of the relevant digital position of divisor D. It is, what is indicated by overstretching applied inverted to the signal input designated in the same way. The label

states so that be apt input of the selector S _i in which the digital entity in question d _i receiving register-memory stage R _i to the inverting output of the first or the second or the third or the fourth Binärspeicherein standardize the register memory stage R _i is connected.

Since the structure of the individual register memory stages R ₀, R ₁. . . . R _{k -1 must} also be based on the decimal system in order to achieve a match with the digital counter DZ , the individual register memory stage R _i also has four binary stages, of which the stage leading the signal d _{i 1 has} the lowest dual position and that Signal d _{i 8} leading stage of the highest dual digit is assigned to the decimal place d _{i of} the divisor D stored in the register stage R _i . The register RG and its individual memory stages are also constructed in a known manner. The implementation of the individual Bi närstufen can be done in a known manner by conventional D flip-flops, which take over the division value D to be set from a data source (not shown) in parallel by a common clock pulse.

Now for the construction of the logic comparison circuit representing the individual selector S _i according to FIG. 2.

The four signal inputs of the first NOR gate N ₁ are each at one of the inputs q _{mi , 1} , q _{mi , 2} , q _{mi , 8} and q _{mi , 4th} The second NOR gate N ₂ has three inputs, each at one of the inputs

lie. The signal input q _{mi , 1} and the signal input is connected to one of the two inputs of the third NOR gate N ₃.

The fourth NOR gate N ₄ has four inputs, each from one of the signal inputs

are acted upon. The fifth NOR gate N ₅ lies with one of its three inputs on one of the signal inputs

and the sixth NOR gate N ₆ with its three inputs each on one of the signal inputs

The seventh NOR gate N ₇ has two inputs, each of which is acted upon by the second NOR gate N ₂ and the third NOR gate N ₃. The eighth NOR gate N ₈ also has two inputs, one of which is controlled by the output of the first NOR gate N ₁ via the inverter IN ₁ and the other by the signal input d _{i 1 applied} by the register cell R _i .

The two inputs of the ninth NOR gate N ₉ are switched in such a way that the one input with the signal input of the i- th register memory unit R _i , which is connected to the output of the seventh NOR gate N ₇.

The tenth NOR gate N ₁₀ has seven logic inputs, of which the first with the signal input, the second te with the signal output of the first NOR gate N ₁, the third with the signal output of the second NOR gate N ₂, the fourth with the signal output of the third NOR gate N ₃, the fifth to the output of the fourth NOR gate N ₄, the sixth to the output of the fifth NOR gate N ₅ and the seventh to the output of the sixth NOR gate N ₆ .

The eleventh NOR gate N ₁₁ has three inputs, one of which is connected to the signal input, the other to the output of the first NOR gate N ₁ and the last to the output of the sixth NOR gate N ₆. The output of the sixth NOR gate N ₆ is also connected via the inverter IN ₂ to one input of the twelfth NOR gate N ₁₂, the other input of which by the thirteenth NOR gate N ₁₃ of the (i +1) th selector S _{i +1} in inverted form supplied signals C _{i +1 is} controlled.

The thirteenth NOR gate N ₁₃ has five signal inputs, each of which is connected to the output of one of the NOR gates N ₈- N ₁₂, that is, the eighth to twelfth NOR gate, in the manner shown in FIG. 2. From the output of the thirteenth NOR gate N ₁₃ provides the signals C _i in inverted form. In the case of i = 1, the signal appearing at the output of N ₁₃ is used to control the frequency divider FT , in the case of i <1 to control the selector S _{i -1} having the next lowest index in accordance with the definitions given above.

The comparison logic just described and forming the individual selectors S _i effects a linkage accordingly

C _i = I ₁ · d _{i 1} + I ₂ · d _{i 2} + I ₄ · d _{i 4} + I ₈ · _i d ₈ + I _C · C _{i + 1,} (6)

where I ₁ that at the output of the eighth NOR gate N ₈, I ₂ that at the output of the ninth NOR gate N ₉, I ₄ that at the output of the tenth NOR gate N ₁₀, I ₈ that at the output of the eleventh NOR gate N ₁₁ and I _C the signal appearing at the output of the twelfth NOR gate and d _{i 1} - d _{i 8} mean the three dual digits of the i th decimal stage of the divisor D , that is to say the content of the memory stage R _{i of} the register RG . The relationship (6) can be read in the sense of Boolean algebra.

At the signal inputs q _{m -1.1} to q _{mi , 8} , in the i- th comparison logic S _i or memory stage Z _mi, the pulses apparent from the diagrams in FIG. 3 occur, the frequency of the pulse sequences corresponding to one another being compared the adjacent counter stage Z _{mi +1 of} the decimal counter DZ or the selector S _{i -1 assigned} to it is reduced to the tenth part. The same also applies with regard to the switching speed of the corresponding logic gates in the individual selector stages S ₁, S ₂,. . . S _{k -1} . This also includes those when the entrances are loaded

and with the control signal (carry) C _{i +1} to be supplied with the input of the comparison logic S _i with a logic ZERO at all of these inputs occurring signals I ₁- I _C , which in the manner shown in FIG eighth to 12. NOR gates, that is, the gates N ₈- N ₁₂ are assigned.

The carry pulse C _i to be transmitted from a selector S _i to the selector S _{i -1} is taken over by the stage S _{i -1} in a state which, both when counting up and when counting down, has enough time for the transmission pulse to pass C _i guaranteed by all levels. This corresponds to the state "5", that is, the state in which the counting process just passes the number 5. If only an upward count is intended, the transfer to state "9" is cheaper, if only a downward count is intended, the transfer is transferred to state "" more favorably.

The value for the quotient Q which increases successively in the decimal counter DZ due to the effect of the selectors S _i and the supply of the sequence of clock pulses representing the number M to be divided via the frequency divider FT increases along a staircase function, the steepness of which is determined by the numerical value of the Divisors D , that is, the content of the register RG . With reference to FIG 6, this is the basis of the visors Di D = 2.1. D = 2.6; D = 3.2 and D = 3.9 shown.

Generalizing to a p-adic number system, to which an arrangement according to the invention is designed,  can with regard to the functioning of a front determine the direction according to the invention:

• 1. encoding of the p states of the memory stage Z _{mi of} the digital counter designed for the p-adic system in question;
• 2. Combine individual of these states accordingly the individual bits of the binary coding of this p-adic Number system for summable combinations;
• 3. Link the compositions corresponding to the bits with the bits of the division register RG and add them to the carry output

From this point of view, the comparison logic forming the individual selector should generally be selected. In the case of the decimal system, this is expedient (in particular also with a view to implementation in integrated MOS technology) in the manner shown in FIG. 2. If it is a different number system, the comparison logic will also have a correspondingly modified appearance.

In the event that the arrangement according to the invention is based on the dual system as a number system, there is an embodiment according to FIG. 7, which is still discussed.

A particularly advantageous embodiment of the frequency divider FT and the associated circuit for applying the frequency divider with the signals coming from the first register memory stage R und and the first digital position d ₀ of the divisor D assigned signals d ₀₁, d ₀₂ and d ₀₄ and their associated inverted Sig nals is shown in Fig. 6.

The frequency divider is an on in this embodiment well-known three-stage shift register ring divider  with EXOR feedback of the last two stages, its maximum divisor value is 2³-1, i.e. 7.

The first shift register stage of the device shown in Fig. 6 contains a NOR gate G ₁, with two inputs, one input via the source-drain path of a first MOS field effect transistor T ₁, the other is acted upon by a common reset signal R. The gate of the transistor T ₁ is controlled via the clock TM ge.

The output of the NOR gateG₁ performs one the beatTS controlled field effect transistorT₂ both to the one input of the output of the frequency divider forming another NOR gateG₄ with three entrances, as well as to the input of an inverterIn₁, whose out output the first shift register stage of the Fre quenz dividerFT forms. The input of the inverterIn₁ is also above a controlled by the reset signal reset Field effect transistorT₃ to ground, so at the reference point potential. The input of the inverterIn₁ is simultaneous the inverted output , the output of the inverter In₁ simultaneously the non-inverted outputQ the first Shift register level.

The second shift register stage is the first Schiebere gisterstufe constructed according to: In the interface, the NOR gate G ₂ speaks ent the NOR gate G ₁ of the first shift register stage, the input transistor T ₄ corresponds to the transistor T ₁, the transistor T ₅ the Tran sistor T ₂, the transistor T ₆ the second stage, the Tran sistor T ₃ of the first stage and the inverter In ₂ of the second stage inverter ₁ In the first stage.

The third shift register level contains the same basic elements as the first and the second shift register level. The stage T from the output of the inverter In ₂ of the second stage fe controlled input of the third shift register corresponds to transistor T ₇ corresponds to the transistors T ₁ and T ₄, the NOR gate G ₃, the NOR gates G ₁ and G ₂ the first and second shift register stage. Furthermore, the transistor T ₈ corresponds to the transistors T ₂ and T ₅, the transistor T ₉ to the transistors T ₃ and T ₆ of the other two stages of the frequency divider FT . Finally, the inverter corresponds to the In ₃ In vertern In ₁ and ₂ in the first two stages.

To feed back the ring counter, an exclusive OR gate G ₁₃ is provided, the two inputs of which are formed from the outputs of the inverters In ₂ and In ₃ of the last two shift register stages of the frequency divider FT . The output of the exclusive OR gate G ₁₃ is connected via the source-drain path of the input transistor T ₁ of the first shift register stage to the one input of the NOR gate G ₁ this shift register stage. The to be controlled with the reset signal R second inputs of the NOR gates G ₁, G ₂, G ₃ of the three stages of the frequency divider FT are common to the output of a fourth inverter In ₄, whose input via a clock controlled by the master TM field effect transistor T ₁₀ is connected to the output of a NOR gate G ₁₂. This is referred to below.

The already mentioned output gate G ₄ - also a NOR gate with three signal inputs - is, as already mentioned, with one input at a circuit point between the field effect transistor T ₂ clocked by the slave clock TS and the input of the inverter In ₁ of the first shift register stage . The second input of this output NOR gate G ₄ is acted upon by a switching point between the transistor T ₅ controlled by the clock TS and the input of the inverter In ₂ in the second shift register stage of the frequency divider FT . In an analogous manner, the third input of the output NOR gate G ₄ is conductively connected to a circuit point between the field effect transistor T ₈ controlled by the clock TS and the inverter In ₃ of the third slide gate stage. The signal output of the NOR gate G ₄ forms the clock output of the frequency divider FT , which is therefore connected to the counting input of the decimal counter designed as a digital counter DZ .

The OR gate G ₅ has three inputs, one of which is connected to the input of the inverter In ₂ of the second shift register stage, while the second input together with an input of the output NOR gate G ₄ to the input of the inverter In ₃ the third shift register stage is connected. The last input of the NOR gate G ₅ is at the output of the inverter In ₁ the first shift register stage of the frequency divider FT .

An OR gate G ₆ with three inputs is an input with the output of the inverter In ₁ the first shift register stage, with the second input with the input of the inverter In ₃ the third shift register stage and with its third input with the output of the inverter In ₂ the second shift register stage and thus connected to the one input of the exclusive OR gate G ₁₃.

Another OR gate G ₇ with three inputs lies with one input at the input of the inverter In ₁ the first stage of the frequency divider FT , with the second input at the output of the inverter In ₂ the second divider stage and with the last input at the output of the inverter In ₃ the third stage.

A fourth OR gate G ₈ with three inputs is with its first input to the output of the inverter In ₁ the first shift register stage, with the second input to the input of the inverter In ₃ the third shift register stage and with the last input to the output of Inverters In ₃ the third shift register stage of the frequency divider FT switched.

The outputs of the OR gates G ₅, G ₆, G ₇ and G ₈ are used to act on the three signal inputs of a previously mentioned and via the inverter In ₄ the R signal generating NOR gate G ₁₂ in the one shown in FIG. 6 Wise. In each case, a field effect transistor T ₁₂ to T ₁₇ interposed as a transfer transistor which is controlled by the carry signal C ₁ supplied by the selector S ₁ ge.

Accordingly, the output of the OR gate G ₅ is connected via the transistor T ₁₂ to the first input of the NOR gate G ₁₂, which is also the output of the OR gate G ₆ via the transistor T ₁₃. The output of the OR gate G ₆ is also connected via the transistor T ₁₄ to the second input of the NOR gate G ₁₂. The second input of the NOR gate G ₁₂ is also via the transistor T ₁₅ at the output of the OR gate G ₇, which in turn is connected via the transistor T ₁₆ with the dirtiest input of the NOR gate G ₁₂. Finally, the output of the OR gate G ₈ via the transfer transistor T ₁₇ is also at the third input of the NOR gate G ₁₂.

To control the gate electrodes of the transfer transistors T ₁₂- T ₁₇ serves, as already mentioned, the signal C ₁, the transistors T ₁₂, T ₁₄ and T ₁₆ directly, the transistors T ₁₃, T ₁₅ and T ₁₇ via an inverter In ₅ is fed.

The first digital digit d ₀ of the divisor D receiving memory stage R ₀ of the register RG supplies the signals d ₀₁, d ₀₂ and d ₀₄ and the associated inverted signals

which are connected to the correspondingly labeled inputs of the circuit shown in FIG. 6. The signal d ₀₁ corresponds to the first dual digit ( i.e. the decimal numbers 0 to 1), the signal d ₀₂ to the second dual digit ( i.e. the decimal numbers 2 and 3) and the signal d ₀₄ corresponds to the third dual digit ( i.e. the decimal numbers 4-7 ) of d ₀.

In order to transmit these signals in the required manner to the three inputs of the NOR gate G ₁₂ and to control the generation of the R signals, three NOR gates G ₉, G ₁₀ and G ₁₂ are provided with three signal inputs each. They are switched in the following way:

The NOR gate G ₉ is with its first input on the signal d ₀₁, with its second input and with its third input at d ₀₄, while its output is wired-OR-connected to that input of the NOR gate G ₁₂ , on which the OR gates G ₅ and G ₆ are also located.

The NOR gate G ₁₀ is on the input side with the Signalein

and connected on the output side to that input of the NOR gate G ₁₂ in wired-OR operation, which is controlled by the two OR gates G ₆ and G ₇ ge.

Finally, the NOR gate G ₁₁ with the one input on the signal d ₀₁, with the second input on the signal d ₀₂ and with the last input on the signal Its output is with that input of the NOR gate G ₁₂ in wired-OR Connected, which is controlled by the two above-mentioned OR gates G G and G ₈. The field effect transistor T ₁₁ is the load element of the NOR gate G ₄.

The clocks TS and TM which serve to supply the system with clocks, in particular the three shift register stages of the frequency divider FT , and which consist of clock pulses which are inverted and do not overlap, simultaneously form the sequence of M clock pulses to be shared. The clock pulses supplied by a clock generator in the usual manner can, for. B. via a by a time gate, which also provides for the reset pulses, can be keyed by means of a NOR gate in such a way that the desired number M of clock pulses just passes the gate. You will z. B. used as the sequence TM of clock pulses. The sequence TS is z. B. won by inversion of the sequence TM ge.

The task of the OR gate G ₅- G ₈ is to encode the various states of the shift register ring counter. The NOR gates G ₉- G ₁₁ encode the most important states of the most important divisor decade d ₀. Together with the three-stage ring counter FT, this results in the following logical behavior, with the counter reading which is set after each reset pulse being given by the sequence 1 1 1.

When encoding the binary combination in shift gate selected via d ₀ and C ₁ (on the gate G ₉, G ₁₀ and G ₁₁ and on the transfer transistors T ₁₂ / T ₁₃, T ₁₄ / T ₁₅, T ₁₆ / T ₁₇), this is shifted G ₁₂, T ₁₀ and In ₄ deferred.

The arrangements described all use a so-called modular counting method for the vision with D. The main counter is preceded by a switchable n / (n +1) divider, the division rate of which is determined anew by the divisor D and the current counter reading with each new pulse. This method requires less logic and no time in addition to counting the impulses of the dividend M.

In contrast, the usual method of Division by repeated subtraction of the divisor from Dividends are a significant logical effort for the sub traction and additional functions required for this, like decimal correction, counting subtractions, Left shift when moving to the next position, as well as a great deal of time spent performing the operations.

As expected, the amount of logic is particularly low if a device according to the invention is based on the dual system. A related direction is shown in Fig. 7, from which the structure of the individual selectors S _i can also be seen. The basis of the dual system also requires the configuration of the individual memory stages of the counter DZ and the register RG as dual memory stages, ie primarily as flip-flop cells, such that both the register stages R ₀, R ₁,. . . R _{k -1} , as well as the counting stages Z _{m -1} ,. . ., Z _{k -1,.} . . are each represented by a flip-flop cell. As a frequency divider TF , only a 1: 2 divider is required, through which the chain forming the digital counter DZ is acted upon by master-slave flip-flops.

The individual selector cell S _i contains a NOR gate L ₁, at the output of which the signal appears and whose de inputs through an AND gate L ₂ or a NOR gate L ₃ - both with two inputs - are each beat . The inputs of the AND gate L ₂ are acted on the one hand by the Q output of the memory stage Z _{mi +1 of} the counter DZ on the other hand by the register memory stage R _i , while the two inputs of the NOR gate (L ₃) by the of the each subsequent selector unit S _{i +1} supplied carry signal C _{i +1} or the respectively assigned memory stage R _{i of} the register RG are controlled.

The illustration in FIG. 7 is only limited to the connection of a selector stage S _i .

Claims (28)

1. Device for evaluating dual pulse sequences by Tei treatment with a register (RG) for storing a divisor used to control divider values (D) and with a digital counter (DZ) , the memory stages (Z _mi ; R _i ) on the same number system are aligned, and with selectors (S _i ), which are controlled by information stored in respectively assigned individual memory stages of the register (RG) and the digital counter (DZ) , characterized in that one with the dual pulse sequences (M) to be evaluated supply the frequency divider (FT) , which can be switched to at least two different divider values (d ₀, (d ₀ + 1)), is connected to the counting input of the digital counter (DZ) providing the result (Q) of the evaluation,
that between the second digital digit (d ₁) of the divi sors (D) receiving the memory stage (R ₁) of the register (RG) and the first applied to the counting input of the digital counter (DZ) dual pulses memory stage (Z _{m -1} ) of the digital counter (DZ) arranged selector (S ₁) causes a switchover of the frequency divider (FT) between two special divider values (d ₀, (d ₀ + 1)) which differ in particular and
that the frequency divider is tuned to the first digital position (d ₀) of the divisor stored in the register (RG) in such a way that one of the two divider values (d ₀, (d ₀ + 1) that can be set via the selector (S ₁) ) is identical to the first digital digit (d ₀) of the divisor (D) . 2. Device according to claim 1, characterized in that with the exception of storing the first (= highest most) digital digit (d ₀) of the divisor (D) serving storage stage (R ₀) all other storage stages (R ₁,... R _{k -1} ) of the register (RG) for controlling one selector (S _i ) are provided that, in addition, the number of these register memory stages is the same number of immediately successive and beginning at the counting input memory stages (Z _{m -1} , Z _{m -2} ,... (Z _{mk +1} ) of the digital counter (DZ) is also provided for controlling one of these selectors (S ₁, S ₂,... S _{k -1} ), that the one of the second Digital position (d ₁) of the divisor (D) associated memory stage (R ₁) of the register (RG) controlled selector (S ₁) for controlling the frequency divider (FT) and each of the other selectors (S _i ) for controlling a different selector ( S _{i -1} ) serves that the respective controlled selector (S _{i -1} ) of that memory level (Z _{mi +1} ) of the digita l counter (DZ) is assigned, which is adjacent to the control stage selector (S _i ) associated memory stage (Z _mi ) in the direction of the counting input of the digital counter (DZ) , and finally that is assigned to the respective control selector (S _i ) memory stage (R _i) of the register (RG) for receiving a digital position (d _i) of the divisor (D) and _(-1 S _i) associated with the memory stage (R _{i -1)} to receive those digital position (d _i the respective controlled selector _-1 ) of the divisor (D) is seen, which is one digital stage before the control selector (S _i ) assigned digital stage (d _i ). 3. Device according to claim 1 or 2, characterized draws that the intended selectors are equal to each other 4. Device according to one of claims 1 to 3, characterized in that the memory stages (Z _i ) of the digital counter (DZ) and that of the register (RG) are aligned with the decimal system. 5. Device according to one of claims 1 to 4, characterized records that excludes to build the arrangement Lich MOS field effect transistors are used. 6. Device according to one of claims 1 to 5, characterized in that the of the respective memory stage (Z _mi ) of the digital counter designed as a decimal counter (DZ) and the individual binary stages of the individual decade corresponding dual signals in both non-inverted and are placed in inverted form on each of a signal input (q _{mi, r} r = 1, 2, 4, 8) of a comparison logic forming the selector (S _i ), that furthermore a signal input of the comparison logic is also provided for the data from the selector (S _i ) assigned register memory stage (R _i ) provided signals (d _is ; s = 1, 2, 4, 8) and for the signal (S _{i +1} ) supplied by the respective downstream selector (S _{i +1} ) is and that finally the comparison logic is only made up of NOR gates (N ₁- N ₁₃) and inverters (IN ₁, IN ₂). 7. The device according to claim 6, characterized in that a first NOR gate (N ₁) with four inputs per input by one of the signals q _{mi , 1} , q _{mi , 2} supplied by the associated memory stage of the decimal counter (DZ) , q _{mi , 4} , q _{mi , 8} , controlled that a second NOR gate (N ₂) with three inputs per input by one of the signals from the assigned memory stage (Z _mi ) of the decimal counter (DZ) and a third NOR gate (N ₃) with two inputs is acted upon by the signal q _{mi , 1} , on the one hand, and by the signal that a fourth th NOR gate (N ₄) with four inputs per input by one of each Signals is controlled that also a fifth NOR gate (N ₅) with three inputs per input for control by means of one of the signals is provided and that the last logic gate directly controlled by the signals supplied by the assigned memory stage (Z _mi ) of the decimal counter (DZ) is a sixth NOR gate (N ₆) with three inputs, each of which is one of the signals assigned. 8. The device according to claim 7, characterized in that an eighth NOR gate (N ₈) with two inputs at one input by the associated register cell (R _i ) and the smallest dual unit assigned signal and at the other input through the output the seventh NOR gate (N ₇) is controlled that also a tenth NOR gate with seven inputs (N ₁₀) at the first input by the signal supplied by the register memory stage (R _i ), at the second input by the first NOR -Gat (N ₁), at the third input through the second NOR gate (N ₂), at the fourth input through the third NOR gate (N ₃), at the fifth input through the fourth NOR gate (N ₄), on sixth input is controlled by the fifth NOR gate (N ₅) and at the seventh input by the sixth NOR gate (N ₆) and that finally an eleventh NOR gate (N ₁₁) with three inputs at the first input by the from the register (RG) delivered signal, at the second input directly through the output de s first NOR gate (N ₁) and at the third input by the output of the sixth NOR gate (N ₆) is applied. 9. The device according to claim 8, characterized in that the output of the sixth NOR gate (N ₆) is connected via an inverter (IN ₂) to the one input of a two-input twelfth NOR gate (N ₁₂), the second Input to the signal output of the following selector stage (S _{i +1} ). 10. The device according to claim 9, characterized in that a the signal output of the selector (S _i ) forming and having five logic inputs NOR gate (N ₁₃) with one input to the output of the eighth NOR gate (N ₈), with the second input to the output of the ninth NOR gate (N ₉), with the third input to the output of the tenth NOR gate (N ₁₀), with the fourth input to the output of the eleventh NOR gate (N ₁₁) and is connected with the fifth input to the output of the twelfth NOR gate (N ₁₂). 11. Device according to one of claims 1 to 10, characterized in that the intended selectors (S ₁, ... S _{k -1} ) are constructed in the same way 12. The device according to one of claims 1 to 10, characterized in that a shift gister ring divider with feedback by an exclusive OR gate is used as a frequency divider (FT) . 13. The apparatus according to claim 12, characterized in that a counter reset is provided for the operation of the frequency divider (FT) . 14. The apparatus of claim 12 or 13, characterized in that each NOR divider (G ₁, G ₂, G ₃) is provided per frequency divider stage, each with two inputs and the one input is controlled by a clock TM MOS field effect transistor ( T ₁, T ₄, T ₇) is controlled by the respectively preceding frequency divider stage or by the last frequency divider stage via the exclusive OR gate (G ₁₃) and the second input by a common R signal supplied by the counter reset that furthermore, the output of the NOR gate of the frequency divider stage in question via a clock TS inverse to the clock TM controlled MOS field effect transistor (T ₂, T ₅, T ₈) to the input of an inverter forming the output of the relevant frequency divider stage (In ₁, In ₂ , In ₃) and that finally the input of the inverter via the source-drain path of a MOS field-effect transistor (T ₃, T ₆, T ₉) to ground and the gate electrode of the latter field-effect transistor (T ₃, T ₆, T ₉) is applied to a general reset signal (reset). 15. The apparatus according to claim 14, characterized in that the clocks TS and TM form the pulse sequence M to be divided . 16. The apparatus according to claim 14 or 15, characterized in that the output of the inverter (In ₂) the penultimate and the output of the inverter (In ₃) of the last divider stage of the frequency divider (FT) to act upon one input only with two inputs provided exclusive OR gate (G ₁₃) and that the output of this exclusive OR gate (G ₁₃) via the input transistor (T ₁) of the first divider to the one input of the NOR gate (G ₁ ) this stage is switched. 17. The apparatus according to claim 16, characterized in that the signal output of the first selector (S _i ) and the signal outputs (d ₀₁ ,...) Of the first memory stage (R ₀) of the register (RG) for controlling the reset during the operation of the frequency divider (FT) via a NOR gate (G ₁₂) are provided that the output from the NOR gate (G ₁₂) via a ge controlled by the clock TM MOS field effect transistor (T ₁₀) to an inverter ter (In ₄) and its output to the second inputs of the NOR gates (G ₁, G ₂, G ₃) of the divider stages of the frequency divider (FT) is placed. 18. The apparatus according to claim 17, characterized in that to act upon the generation of the reset signals (R) serving NOR gate (G ₁₂) the six signal outputs of the first register memory stage (R ₀) in such a way to the inputs three - three each Inputs having - NOR gates (G ₉, G ₁₀, G ₁₁) are placed that the gate G ₉ on the signals d ₀₁, d ₀₄, the gate G ₁₀ on the signals, d ₀₄, and the gate G ₁₁ sig nals d ₀₁, d ₀₂ and lies and that also the outputs of these three NOR gates (G ₉, G ₁₀, G ₁₁) with one of the three inputs of the NOR gate provided for generating the reset signals (R) ( G ₁₂) are connected. 19. The apparatus according to claim 18, characterized in that four OR gates (G ₅- G ₈) are provided with three inputs each for further control of the NOR signals ( G ₁₂) provided for generating the reset signals (R) , that to act on the first OR gate (G ₅) whose one input with the input of the inverter (In ₂) of the penultimate frequency divider stage, whose second input with the input of the inverter (In ₃) of the last frequency divider stage and its third input with the output of the inverter (In ₁) of the first frequency divider stage is connected, that also an input of the second OR gate (G ₆) with the output of the inverter (In ₁) of the first frequency divider stage, a second input of this gate (G ₆ ) is connected to the input of the inverter (In ₃) of the last frequency divider stage and its last input to the output of the inverter (In ₂) of the penultimate frequency divider stage that an input of the third of these OR gates (G ₇) at an input of the inverter (In ₁) of the first frequency divider, the second input of this OR gate at the output of the inverter (In ₂) of the penultimate frequency divider and the third output of this gate (G ₇) at the output of the inverter (In ₃ ) of the last frequency divider stage and that finally the output of the inverter (In ₁) of the first frequency divider stage, the input of the inverter (In ₃) of the last frequency divider stage and the input of the last-mentioned inverter (In ₃) each at an input of the last OR- Gates (G ₈) lie. 20. The apparatus according to claim 19, characterized in that the output of the first OR gate (G ₅) via a controlled by the selector signal (C ₁) MOS field effect transistor (T ₁₂) on the simultaneously by the NOR gate (G ₉) controlled input of the generation of the return signals (R) serving NOR gate (G ₁₂). 21. The apparatus according to claim 20, characterized in that the output of the second OR gate (G ₆) via a field effect transistor controlled by the inverted selector signal (C ₁) to the input of the at the same time by the first OR gate (G ₅) the generation of the reset signals (R) serving NOR gate (G ₁₂) and via a controlled by the selector signal (C ₁) controlled further MOS field effect transistor (T ₁₄) to the second input of this NOR gate (G ₁₂). 22. The apparatus according to claim 21, characterized in that the output of the third OR gate (G ₇) via an inverted by the from the first selector (S ₁) signal (C ₁) controlled MOS field effect transistor (T ₁₅) on the second Input as well as via a MOS field effect transistor (T ₁₆) controlled by the non-vertized selector signal (C ₁) at the third input of the generation of the reset signals (R) serving NOR gate (G ₁₂) is switched on. 23. The apparatus according to claim 22, characterized in that the output of the fourth OR gate (G ₈) via a MOS field effect transistor (T ₁₇) controlled by the inverted selector signal (C ₁) to the third input of the generation of the reset signals ( R) serving NOR gate (G ₁₂) is connected. 24. The apparatus according to claim 23, characterized in that the output of the frequency divider (FT ) to be connected to the counting input of the digital counter (DZ) is given by the output of a NOR gate (G ₄) having three inputs, the inputs of which are provided with the inputs of the inverters (In ₁, In ₂, In ₃) of the frequency divider stages are connected. 25. The device according to claim 24, characterized in that a total of three frequency divider stages are provided are. 26. The device according to one of claims 1 to 3, characterized in that the structure of the register (RG) and the digital counter (DZ) is based on the dual system as a number system. 27. The apparatus according to claim 26, characterized in that the individual selectors (S _i ) are given by the combination of two NOR gates (L ₁, L ₃) and an AND gate (L ₂) that each of these gates only has two inputs, that the output of a NOR gate (L ₁) is provided for controlling the respective following selector (S _{i -1} ) or the frequency divider (FT) , that the two inputs of this NOR gate ( L ₁) are controlled by the outputs of the other two gates (L ₂, L ₃) and that finally, in order to act on the inputs of the AND gate (L ₂), the respectively assigned memory stage (Z _mi ) of the digital counter designed as a dual counter (DZ ) and the assigned register memory stage (R _i ) and for controlling the inputs of the NOR gate (L ₃) the associated regi ster memory stage (R _i ) and the respective controlling selector (S _{i +1} ) are provided. 28. Device according to claims 26 and 27, characterized in that the frequency divider (FT) is designed as a 1: 2 divider.