GB1452519A - Digitally operating instructable translator - Google Patents

Abstract

1452519 Trainable processors AKADEMIE DER WISSENSCHAFTEN DER DDR 16 Oct 1973 [16 Oct 1972] 48077/73 Heading G4R A trainable digital processor includes a matrix array of weighting units for weighting the bits of an input signal. Each weighting unit comprises a reversible counter which is incremented or decremented during training. During recognition the input signal bits are weighted, and a preset value is added to ensure that the result is positive. Training mode. An input signal xl, x2, ..., x n is applied to a row of weighting units Wkl-Wkn selected by a pulse on a corresponding line TLk (k = 1-m). If the bit xi(i = 1-n) has a first bit state the content of a counter in weighting unit Wki is incremented, whereas if the bit has the other state it is decremented. Incrementing and decrementing are prevented if the count reaches 111 ... and 000 ..., respectively. This procedure is repeated for further training signals. Recognition mode. A signal xl, x2, ..., x n to be recognized is applied to each of a number of units V 1 -V m . Each unit Vk also receives the weighting values from the corresponding units W ki and forms the n products W ki .x i . To each product is added the value 2<SP>c-1</SP>, where c is the number of stages in the counter in the weighting unit. The row n sum Zk = # (W ki .x i + 2<SP>c-1</SP>) is formed and is i=1 stored at A k . The input signal is then identified by the row sum having the greatest value. Alternatively, each row sum is compared with a threshold (which may be adjusted during training) to provide a signal b 1 , b 2 , ..., b m indicative of the match between the unknown and the training signals.