DE2323471A1 - VARIABLE IMPEDANCE CIRCUIT WITH LINEAR CHARACTERISTICS USING A RIS FIELD EFFECT TRANSISTOR - Google Patents

Description

Patent application

Variable impedance circuit with linear characteristics using a RIS field effect transistor

The invention relates to a variable impedance circuit with a wide range of variation, for example
can be used in analog computers, circuits with automatic gain control, in devices for four-channel stereophony, etc. It is known,
for this purpose a conventional FET, a CdS photoconductive impedance element, etc. can be used to achieve the
To keep disturbances relatively low. The amplitude of the
The input signal must be smaller than a certain one
be relatively low levels. A relatively low noise level is required in order to achieve a correspondingly high signal-to-noise ratio, which is increasingly being set higher for hi-fi equipment.

A semiconductor unit that has a resistive layer over an insulating layer on a semiconductor substrate
is known from US Pat. No. 3,714,522.

309848/0887

The invention has for its object to design a semiconductor unit and circuit so that this has a wide range has a linear impedance characteristic.

Furthermore, the semiconductor unit or circuit should be suitable for use as a novel attenuator.

According to the invention, one end of the resistance channel is previously mentioned transistor via a capacitor with the source electrode or via a capacitor with the drain electrode connected, or both the source electrode and the drain electrode are connected via separate capacitors connected to one end of the resistance channel.

Embodiments of the invention are based on the following of the drawings.

Show it:

1 shows a perspective cross section through a field effect transistor according to the present invention;

2 shows a basic circuit. for a field effect transistor with resistance channel of the type under consideration here;

3 to 8 circuit examples for the use of the field effect transistor considered here.

In Fig. 1, reference numeral 10 denotes a new semiconductor unit in which 1 is an N-type semiconductor substrate. A ρ - source region 2 and a p ⁺ drain region 3, which are separated from one another by a distance L, are doped into the surface of the substrate. On the surface of the substrate 1 is at least between

309848/0887

! the source electrode 2 and the drain electrode 3 an insulating layer 4, which consists _{for example of SiO 2 ″}

ι insulating layer 4 is a resistance layer 5. This ! . Resistance layer can, for example, consist of polycrystalline!

Silicon, the surface resistance of which is between 10 kilo-ohms and 30 giga-ohms. For the source electrode 2, a metallic electrode connection 6 is provided and a metallic electrode is provided for the drain electrode 3

connection 7 provided. A first gate electrode 8 is located in the vicinity of the source electrode 6 A second gate electrode 9 is located near the drain electrode 7. There are two gate electrodes 8 and 9 also on the resistance layer 5. The drain-side edge of the electrode 8 must exactly match the drain-side edge of the source area 2 are aligned. The source-side edge the electrode 9 must be exactly with the source-side edge of the Align the dr ^ in electrode 3. Any deviation from this exact regulation leads to malfunctions.

The substrate 1 has, for example, a relatively low density of impurities. In particular, if the semiconductor unit is to be used in the context of an integrated circuit which is built up on a further substrate which lies under the substrate 1 and is of a different conductivity type, the impurity density of the substrate 1 is chosen so that the resistance is 50 ohms χ cm or more in order to avoid or reduce the influence of the * IC substrate. The Störst ellendichtea of the areas 2 and 3 are chosen in this case about 10 ^ atoms / cm. The length L of the channel is about 20 microns. Its width is about 300 μl and the thickness Tox of the insulating layer 4, if it is made of SiOp, about 1,200 A (Angstrom). The layer 5 made of polycrystalline silicon has a thickness of about 1 / *. . The Flächenwiderst? .Ηά the layer 5 is in the range of 10 kilo-ohms to ZO giga-ohms. The sheet resistance of the layer 5 is therefore extraordinarily high. For the elec-

309848/0887

electrode connections 8 and 9, special contacts must be used. At point X (where X indicates the distance from the source area 2) the potential is V (x). The gate voltage at the corresponding point of the gate area is V _G (X). A so-called step voltage Vth of the semiconductor unit is now defined as follows:

V _G (X) - V (X)> Vth

Where the variation in Vth due to the voltage across the Substrate 1 is very low or negligible. The number of charge carriers N at point X per unit area results then follows like JT:

N - 2 ?. f Vg ₁ (x) - VCx) - VtK J / o *,

Where Co = £ ox / Tox.

ox: dielectric constant of the insulating layer 4, q: electron charges of the carriers.

On the other hand, the resistance is R (X) in the channel between the region 2 and the point X.

where ^ g (X) is the surface resistance of the channel and is the mobility of the charge carriers.

30984870887

The result is

dR (x) ^{A dt}

Coyu [% (X) -V (X) - Wi]

Accordingly, the result for the current I in the channel

Wyu Co fVe, (X) -

Assuming that "Vq (X) - V (X) - V ^ ₀ = constant ....! And the equation (i) is integrated from χ>" ο to χ = L (channel length), one obtains :

W μ Co

We get I = (V _GQ -Vth) V (3)

where V = V (L) and =. Finally, it should be noted that equation (3) is a linear function for condition (2). If the potential of the source region 2 is V ₀ and the potential of the drain region 3 is V ₀ , then equation (3) is fulfilled, provided that the first gate electrode has a potential Vq + V _GQ and the second gate has a potential -Electrode 9 has a potential of V ₀ + V _GQ .

This means that you have a first linear equation (I = RV) for the current between the source area 2 and the drain

309848/0887

Area 3 receives. The resistance R (X) of the channel is a straight line. The resistance or impedance can be controlled _{by the gate voltage V ^ 0 alone.} With this semiconductor unit, a circuit having a variable impedance can be easily manufactured.

As can be seen from FIG. 3, the drain electrode is connected to a terminal 11, which in turn is connected to the second gate electrode 9 via a capacitor 14. Furthermore, the source electrode is connected to a terminal 12, which in turn is connected to the first gate electrode 8 via a capacitor. A control terminal 13 is connected to the first gate electrode via a resistor 16 to which a control signal is fed. In the present case, the substrate 1 can be supplied with a reverse bias voltage. If the transistor is of the P-channel enhancement type, a positive reverse bias is applied. The control voltage V ^ ₀ is then negative.

If the frequency of the input signal it with f ,,, the frequency of the control signal Vq ₀ with fp, the capacitance of the capacitor 14 with C * λ, the capacitance of the capacitor 15 with C ₁ C, the resistance of the resistor 16 with R ^ g and the resistance value between the first and second gate electrodes denoted by Rj- (resistance of the resistance layer 5) and also presupposes that

is, where f "is usually zero (direct current) or a low one Frequency-is, so one obtains

R ₅ and R ₁₆

^R 15

309848/0887

The reactances of the capacitors 14 and 15 are in terms of f ,. of the input signal is low. With regard to f ₂ of Vq _0, however, the reactances are high. The gate potential of the first electrode should be Vc ₅ + V _GQ and the gate potential of the second electrode should be V ^ + V ~ _o .

According to equation (3), a linear characteristic is thus obtained between the connections 11 and 12, which can be set by the control voltage V _G0 which is fed to the connection 13. The circuit shown in Fig. 3 is very simple and is therefore suitable for use in a circuit arrangement with automatic gain control, since the necessary condition f 1. »Fρ can be fulfilled here.

Fig. 4 shows a circuit in which the source electrode is grounded. The capacitor 15 from FIG. 3 is omitted here, since V ₀ = 0. If an internal capacitance 14 is used, the electrode 9 can be eliminated.

Fig. 5 shows a bridge circuit in which a resistor 17 (R ^ y) is used, where C ^ χ R ^ ~ = Cj ^ χ R ^ g is selected. The potential difference between the gate electrodes G ^ and Gp is almost zero; and the terminals G 1 and Gp are supplied from the terminal 13 with the same control voltages V _GQ. This example uses ^ VfTf ₂ instead of I ^ f ₂ .

Fig. 6 shows a T-type attenuator employing two circuits of Fig. 5, 21 and 22 being the input terminals. 23 and 24 are the output terminals. 10A is a similar semiconductor device to 10. 18 and 18A are snubber and shunt resistors. 15A and 16A correspond to capacitor 15 and resistor 16, where ^C 14 ^{x R} 17 ⁼ ^ λ 5 ^{x R} 16 ^{= C} 15A ^{x R} 16A g ^ uh ¹ ^ ^is-fc · ^Es

309848/0887

an attenuation value of 80db and more can be achieved without disturbances occurring.

7 and 8 show a signal level control circuit with reverse bias (ground potential) applied to the FET. Accordingly, no noise is added to the FET and the signal-to-noise ratio is improved. j The FET 10 is an N-channel depletion> Τ3Φ in the present example, and F _nn is positive.

In FIG. 7, the FET 10 is connected in series in the signal path, while in FIG. 8 it is connected in parallel. A capacitor 15 _: (or ground) and the source electrode of the FET 10 are connected so that they form a signal shunt.

In these examples, a signal coming from the emitter follower transistor 25 comes, can be changed in its level without any interference over a wide range appear. The circuit itself is very simple. It is controlled only by a DC control voltage. A The high-frequency signal fed to the connections 21 and 22 can be changed in its amplitude in this way. 23 and 24 are the output terminals.

In the field effect transistor shown in Fig. 1, it is particularly desirable that those parts of the resistance layer 5j which is immediately below the gate electrodes 8 and 9, have a much lower resistance than the part of the resistive layer 5 which is above the channel lies. There must be good ohmic contact with the parts of the Layer 5 exist, which are under the gate electrodes 8 and 8. Since the resistance layer 5 is preferably polycrystallized 1st, and has little or negligible doping, it is easy to identify the parts immediately below the

309848/0887

—9— Electrodes 8 and 9 are highly doped.

309848/0887

Claims (1)

Expectations 1W field effect transistor, characterized by a substrate (1) of the one type of impurity, by two arranged on one side of the substrate (1) and one spacing areas (2, 3) which have a source area (2) and a drain area (3) and from the opposite conductivity tjT? like the substrate (1) are, by one on the mentioned side of the substrate (1) overlying layer (4) made of an insulating material, by a layer (5) lying on the insulating layer (4) a resistance material, and by two gate electrodes (8,9) which are connected to those parts of the resistance layer (5) Ohm's view form contact, which are above the source area (2) and the drain area (3), the drain-side Edge of the gate electrode (8) over the source area (2) exactly with the drain side edge of the acid area (2) is aligned and wherein the source-side edge of the gate electrode (9) over the drain area (3) exactly with the source-side Edge of the drain area (3) is aligned. 2) field effect transistor, characterized by a semiconductor substrate (1) of the one type of impurity, by two arranged on one side of the substrate (1) and one spacing areas (2, 3) which have one another and which form a source area (2) und.ein drain area (3) and between enclose a channel region, the source region (2) and the drain region (3) of the opposite conductivity type like the substrate (1), by a layer (4) of an insulating material, which is on the mentioned side of the substrate rests through a polycrystalline layer (5), which is on the insulating layer above the channel area 309848/0887 and above part of the source area (2) and the ''. drain area (3) rests, and through gate electrodes (8,9) i • which ^{form an ohm 1} with those parts of the polycrystalline layer (5) j see which contact is above the source area; (2) and the drain area (3). | 3) Field effect transistor, characterized by a semiconductor j substrate (1) of the one type of impurity, by two areas (2, 3) on one side of the substrate (1) and at a distance from one another, which have a source area (2 ) and form a drain region (3) and a channel region between them, the source region (2) and the drain region (3) being of the opposite conductivity type to the substrate (1), through one on the mentioned one side layer (4) of an insulating material lying on top of the substrate, through a polycrystalline layer (5) which is deposited on the insulating layer (4) above the channel area and above part of the source area. (2) and the drain area (3) rests, and through gate electrodes (8, 9) which ^{form an ohm 1} contact with those parts of the polycrystalline layer (5) which are above the source area (2) and the drain region (3), the parts of the polycrystalline layer (5) lying under the gate electrodes (8, 9) having a significantly lower resistance than the remaining part of the polycrystalline layer (5) have. 4) Variable impedance circuit, characterized by a resistive layer-insulating layer field effect transistor (10), with a source area (2), a drain area (3) and an intermediate channel, through no electrode (6) on the source area (2) and an electrode (7) on the drain area (3), v / same electrodes (6,7) for connection of the two areas (2,3) serve with a main signal source, through a capacitor (14,15) between 309848/0887 one end of the resistance layer (4) and one of the two areas (2, 3) is connected and through one to the supply a control signal serving gate electrode (8,9) at one end of the resistance layer (4), whereby by a variation of the control signal is a variation in the impedance of the channel through which the signal coming from the main signal source flows, is effected. 5) Circuit with variable impedance, characterized by a resistive layer insulating layer field effect transistor (10) with a source area (2), a drain area (3) and an intermediate channel, by means of connecting the source area. (2) and the drain area (3) with a main signal AC voltage source, such that the main signal stream flows through the channel, and through means for connecting the opposite ends of the resistive layer to a control voltage source, whereby by variation the control voltage causes a variation in the impedance of the channel. 6) Circuit according to claim 5, characterized in that between one end of the resistive layer (4) and the source area (2) and a capacitor between the other end of the resistance layer (4) and the drain area (3) (14,15) is switched. 7) circuit npch claim 6, characterized in that the capacitance value of the capacitors (14,15) is chosen so that the capacitors for the main signal have a lower one Impedance and form a high impedance for the control signal. .8) Circuit characterized by a large number of resistor, insulating layer field effect transistors (10), each with a source area (2), a drain area (3) and an intermediate channel, by means of connecting the source areas (2) and the drain areas (3) 309848/0887 j with a main signal source, such that the main signal ! current through the corresponding channels of the transistors (10) ! flows, and through means for connecting a control signal ; source with all resistance layers (4), by the ! Control signal determines the impedances of all channels. 9) circuit with variable impedance according to claim & _t 'characterized in that the means for connecting the control voltage source to the opposite ends of the resistance layer (4) include two resistance elements (16,17), which between the control voltage source and the opposite ends of the resistance layer (4) are connected in such a way that the resistance elements (16, 17) are parallel to one another. old 309843/0887