DE2343206C2 - - Google Patents

Description

The invention relates to an insulating layer Field effect transistor arrangement according to the preamble of claim 1.

An insulating layer field effect transistor arrangement of the The type referred to above is already due to the older one German Patent 23 23 471 recorded. It has shown, that the transistor arrangement in question only in one relative low frequency range can be used.

It is also an insulating layer field effect Known transistor arrangement, the resistance layer and has a gate electrode attached thereto (IEEE Transactions on Electron Devices, Volume ED-18, 1971, pages 418 to 425). However, it has been shown that the hit in this known transistor arrangement Measures are not enough to make an excellent one  Linearity of the output impedance depending on To achieve control signals in the high-frequency range.

The invention is based on the object Transistor arrangement according to the preamble of the claim 1 so that they are in the high frequency range can be used.

The above problem is solved by those specified in the characterizing part of claim 1 Activities.

The invention has the advantage that relatively simple way an insulating layer field effect Transistor arrangement is created that too can be used in the high frequency range.

Appropriate developments of the invention result itself from the subclaims.

An exemplary embodiment is illustrated by drawings the invention explained in more detail below. In the Shows drawings

Fig. 1 shows a schematic cross section of a transistor arrangement already proposed kind

Fig. 2 shows a schematic cross section of a transistor arrangement according to the invention,

Fig. 3 is a basic circuit for operating a transistor arrangement according to FIG. 1 and

Fig. 4 shows a basic circuit for operating a transistor arrangement according to the invention.

For a better understanding of the invention and the advantages that can be achieved with it, a transistor arrangement of the type already proposed is first described, which is shown in FIG. 1 and is designated by 10 . A semiconductor substrate 1 of the N- (or P-) conductivity type is provided with a P + (N +) - source region 2 and a P + (N +) - drain region 3 on an outer surface, both regions being at a distance L from one another. On the surface of the substrate 1 or at least between the source region 2 and the drain region 3 , an insulating layer 4 , for example an SiO₂ film, is provided, on which in turn a resistance layer 5 is formed. This layer can consist, for example, of polycrystalline silicon, the specific surface resistance of which can be 10 kOhm to 30 GOhm. A metal electrode 6 for the source region 2 and a metal electrode 7 for the drain region 3 are attached to the respective region, a first gate electrode 8 is provided near the source electrode 6 , a second gate electrode 9 is near the drain - Electrode 7 provided. Both gate electrodes 8 and 9 are attached to the resistance layer 5 . The edge of the electrode 8 facing the drain area must be exactly aligned with the edge of the source area 2 facing the drain area, similarly the edge of the electrode 9 facing the source area must be exactly aligned with the edge of the source area facing the source area Drain area 3 can be aligned. Any modification to this exact arrangement causes distortions, as will be shown.

The substrate 1 can, for example, have a relatively low impurity density. Particularly in the case of an integrated circuit, in which a further substrate is normally provided under the substrate 1 with a different conductivity type, the density of the substrate 1 results in a specific resistance of approximately 50 ohm.cm or more in order to reduce the effect of the IC - reduce substrates. The density of regions 2 and 3 is also approximately 10¹⁹ atoms / cm³. The length L of the channel is about 20 microns, its width about 300 microns, and the thickness Tox of the insulating layer 4 is about 0.12 microns in the case of SiO₂. The layer 5 made of polycrystalline silicon has a thickness of approximately 1 μm. The specific surface resistance of this layer is in the range from 10 kOhm to 30 GOhm. If this specific resistance of layer 5 is very high, special contacts for electrodes 8 and 9 must be used. In such an arrangement, a potential V (X) at a point X in the channel region is at a distance from the source region 2 , a gate voltage V _G (X) at the corresponding point in the gate region and a threshold voltage Vth of this arrangement in the following context:

V _G (X) -V (X) ≧ Vth

The change in Vth due to the voltage of the substrate 1 is very small or negligible, so that the number N of charge carriers per unit area at point X has the following value: It is

Co = Eox / Tox Eox : dielectric constant of the insulating layer 4 , q : electron charges of the carrier.

On the other hand, the resistance is R (X) in the channel between the end of area 2 and point X. ρ _s (X) is the specific surface resistance of the channel and μ is the mobility of the charge carriers.

This results in:

The channel current I is correspondingly

If

V _G (X) -V (X) = V _{G 0} = constant (2)

assuming and equation (1) is integrated from x = 0 to xL (channel length), the result is:

this means

I = β (V _{G 0} - Vth) V (3)

in which

Finally, it should be noted that equation (3) represents a linear function for condition (2). If the potentials of the source region 2 and the drain region 3 are V _S + V _{G 0} and the potential at the second gate electrode 9 is V _D + V _{G 0} , as shown in FIG. 1, then the equation can (3) be met.

This means that a first linear equation (I = RV) is obtained in the channel between source region 2 and drain region 3 and the channel resistance R (X) represents a straight line. The resistance or impedance can only be controlled by the gate voltage V _{G 0} . With this arrangement 10 , a circuit with variable impedance can be easily implemented.

As shown in Fig. 3, the drain electrode is connected to a terminal which is further connected to the second gate electrode 9 via an inner or outer capacitor C ₁. Further, the source electrode is connected to a terminal which is also connected to the first gate electrode 8 via an internal or external capacitor C ₂. A control terminal is connected to the first gate electrode 8 , to which a control signal is applied. In such a case, a reverse gate voltage may be present on the substrate 1 , if desired. In the case of a P-channel enhancement type, a positive gate counter voltage is applied and a control voltage V _{G 0} is negative.

An input signal of the frequency f ₁, the control signal V _{G 0 of} the frequency f ₂, the capacitance C ₁, the capacitance C ₂ and the resistance R ₅ between the first and the second gate electrode (resistance of layer 5 ) are each determined, in which

f ₁ » f ₂

Here f ₂ is usually given by direct current or a low frequency, with which the relationships apply:

Then the reactances of the capacitors C ₁ and C ₂ with respect to the input signal f ₁ are small, with regard to the signal V _{G 0} with the frequency f ₂ large. The gate potentials of the first and second gate electrodes are V _S + V _{G 0} and V _D + V _{G 0,} respectively.

According to equation (3), a linear impedance between the source region and the drain region is therefore obtained, which can be set at the electrode 8 by the control signal V _{G 0} . The circuit shown in Fig. 3 is very simple and is therefore suitable for arrangements for automatic gain control, since the required condition f ₁ » f ₂ can be met therein.

A field effect transistor of the type shown in FIG. 1 and a circuit according to FIG. 3 are very suitable for the low-frequency range, but not for most applications in the high-frequency range. If a high-frequency amplifier is installed, the capacitance between the second gate electrode 9 and the drain region 3 or the drain electrode 7 has a detrimental effect, and a leakage current arises. At high frequencies, the channel resistance (impedance) can therefore not be easily controlled only by the gate voltage V _{G 0} . Furthermore, the change range for the resistance becomes smaller. In addition, with regard to the electrode 9, the area of the drain region 3 must necessarily be relatively large, and the transition capacitance between the substrate 1 and the drain region 3 cannot be neglected in the high-frequency region.

These difficulties are avoided by the invention; a corresponding transistor arrangement is shown in FIG. 2 and has only one gate electrode. In Fig. 2, an N (P) conductivity type substrate 11 is provided on one face with a P + (N +) source region 12 and a P + (N +) drain region 13 ; both areas have the distance L from each other. On the surface of the substrate 11 between the source region 12 and the drain region 13 , an insulating layer 14 (SiO₂) is formed, under which a channel 21 is formed. Furthermore, a resistance layer 15 is preferably formed from polycrystalline silicon on the insulating layer 14 . A single gate electrode 16 is provided over the source region 12 and over a thicker part 17 of the insulating layer 14 . The distance a to the edge of the source region 12 facing the drain region 13 represents a preferred value.

The source and drain electrodes 18 and 19 are provided in the manner shown. In the embodiment shown, the resistivity of the substrate 11 is ρ = 50 ohm · cm (ie, low doped), and the impurity concentration of the source and drain regions is 10²⁰ atoms / cm³ (ie, highly doped). The length of the channel L is 10 microns, the values S ₁, D ₁ are 42.5 and 20 microns. The thickness Tox of the insulating layer 14 is approximately 0.1 μm, but the thickness in the region 17 at the source region is approximately 1.2 μm. The value a is approximately 2.5 µm. The resistance layer 15 consists of polycrystalline silicon, its thickness is approximately 1 μm. The specific surface resistance is 10 kOhm to 30 GOhm.

According to the invention, a gate control voltage V _{G 0 is applied} as a constant value to the entire channel 21 with a single gate electrode. This means that with an input signal with a high frequency f ₁ between the source region and drain region and a control signal with a voltage V _{G 0} low frequency f ₂ (where f ₁ » f ₂) the voltage at the drain edge of the resistance layer 15 the value of V _D + V _{G 0,} as has the drain voltage V _D is the layer 15 is added on the internal capacitance between the channel 21 and the layer 15 °. On the other hand, the voltage V _S + V _{G 0 is applied} to the gate electrode 16 , so that the potential relationships correspond to those of the arrangement according to FIG. 1. The potential difference in channel 21 between the source region and the drain region is then constant, so that the conditions for good linearity are met (see equation (2)).

FIG. 4 shows a circuit for operating an arrangement according to FIG. 2, in which the source electrode 18 is grounded ( V _S = 0) and there is only one gate voltage V _{G 0} at the gate electrode 16 . The capacitor C ₁ between the gate electrode and the drain electrode corresponds to an inner or an outer (parasitic) capacitance.

A transistor arrangement according to the invention, as shown in Fig. 2, leads to certain advantages. Only the distance a must be set to a predetermined value during production, which lies in a range a »0. The production is therefore very simple. D ₁ is smaller than the corresponding value according to FIG. 1, since there is no gate electrode 9 . This means that the transition capacitance between the drain region and the substrate is smaller. In the transistor arrangement according to the invention, S ₁ is greater than D ₁. Due to the thicker and more extensive part 17 of the insulating layer 14 , the gate electrode is free of the input signal, in particular with regard to the configuration of the source region. Finally, the length L of the channel can be smaller than in the arrangement shown in FIG. 1. This means that a field effect transistor arrangement according to the invention is better suited for use in the high-frequency range. In fact, some 100 MHz can be achieved with good linearity.

Claims (4)

1. Insulating layer field-effect transistor arrangement with a semiconductor substrate of the one conductivity type, in one surface of which a source region and a drain region of the opposite conductivity type are arranged and with a gate which is arranged on an insulating layer and composed of a resistance layer and one there is a gate electrode attached to the resistance layer and arranged above the source region, characterized in that the edge of the gate electrode ( 16 ) arranged above the source region ( 12 ) facing the drain region ( 13 ) in the direction of the drain Region ( 13 ) from the source region ( 12 ) has a distance (a) from the edge of the source region ( 12 ) facing the drain region ( 13 ). 2. Transistor arrangement according to claim 1, characterized in that the insulating layer ( 14 ) at least over the source region ( 12 ) has a thickening ( 17 ). 3. Transistor arrangement according to claim 2, characterized in that the gate electrode ( 16 ) over the thickening ( 17 ) is arranged. 4. Transistor arrangement according to one of the preceding claims, characterized in that the resistance layer ( 15 ) consists of polycrystalline silicon.