DE2343206A1 - FIELD EFFECT TRANSISTOR ARRANGEMENT - Google Patents

Description

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The invention relates to a field effect transistor arrangement with a semiconductor substrate in which a surface, a source region and a drain region as well as an insulating region running between these Layer are provided on which a resistive layer is arranged and under which a Channel trains.

It is already through U.S. Patent 3,714,522 known a resistive layer on an insulating Layer and both layers to be arranged on a semiconductor substrate. In industry there is a need for a variable impedance element that is not constructed with contacts. Such elements are especially used for stereophonic four-channel devices as well as for analog computers and automatic gain control circuits. The usual field effect transistors, photoconductive CdS elements

40981 1/0914

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as well as other devices can only maintain relatively little distortion and good linearity with relatively small Input signal amplitudes are controlled, which are often below predetermined and relatively low level values. this "means that the signal-to-noise ratio must have a predetermined maximum value, but this with regard to lifelike Sound reproduction with a low noise level is increasingly required.

The object of the invention is to provide a field effect transistor arrangement indicate which shows a linear impedance behavior within a wide range and thereby has improved properties compared to previous arrangements. Such an arrangement should only have three connections and can be used within large frequency ranges can.

A field effect transistor arrangement of the type mentioned is designed according to the invention to solve this problem in such a way that that a gate electrode is provided which is in contact with the resistance layer and only over a partial area one of the areas mentioned is arranged.

The following is an embodiment of a transistor arrangement described according to the invention with reference to comparative examples shown in the figures. Show it:

1 shows a schematic cross section of a transistor arrangement of the type already proposed,

2 shows a schematic cross section of a transistor arrangement according to the invention,

J shows a basic circuit for operating a transistor arrangement according to Fig. 1 and

Fig. 4- shows a basic circuit for operating a transistor arrangement according to the invention.

For a better understanding of the invention and the

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target / baren. Advantages, a transistor arrangement of the type already proposed is described first, which is shown in FIG. 1 and denoted by 10. A semiconductor substrate 1 of the N (or P) conductivity type is provided with a P + (N +) source region 2 and a P + (N +) drain region 3 on an outer surface, the two regions being at a distance L from one another. On the surface of the substrate 1 or at least between the source region 2 and the drain region 3, an insulating layer 4-, for example an 8102-E ¹ um, is provided, on which in turn a Vi of the standing layer 5 is formed. This layer can for example consist of polycrystalline silicon material, the specific surface resistance of which can be 10 kOhm to JO GOhm. A metal electrode 6 for the source region 2 and a metal electrode 7 for the drain region 3 are attached to the respective region, a first gate electrode 8 is provided near the source electrode 6, and a second gate electrode 9 is near the drain -Electrode 7 provided. Both gate electrodes 8 and 9 are attached to the resistance layer 5. The edge of the electrode 8 facing the drain region must be precisely aligned with the edge of the source region 2 facing the drain region, similarly the edge of the electrode 9 facing the source region must be precisely aligned with the edge facing the source region of the drain region 3 be aligned. Any change in this precise arrangement will cause distortion, as will be shown.

The substrate 1 can, for example, have a relatively low impurity density. Particularly in the case of an integrated circuit in which another substrate is normally provided under the substrate 1 with a different conductivity type, a specific resistance of about 5> O Ohmcm or more is realized with the density of the substrate 1 in order to reduce the effect of the IG -Substrate decrease. The density of areas 2 and 3 is also about 10 ^ ° atoms / cm ^. The length L of the channel is approx. 20 microns, its width approx. 300 microns, and the thickness Tox of the insulating layer 4 is approx. 1200 angstrom units _{in the case of SiO 2.} the

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Layer 5 made of polycrystalline silicon has a thickness of approx. 1 micron. The specific surface resistance of this layer is in the range from 10 kOhm to 30 GOhm. If the specific Layer 5 resistance is very high, need special contacts for electrodes 8 and 9 can be used. With such an arrangement there is a potential V (X) at a point X in the channel area at a distance from the source region 2, a gate voltage V ^ (X) at the corresponding point in the gate region and a threshold voltage Vth of this arrangement in the following context:

V _G (X) - V (X) ^ Vth

Where is the change in Vth due to the voltage of the substrate 1 very small or negligible, so that the number N of charge carriers per unit area at point X denotes has the following value:

N = | 2. / V _G (X) - V (X) - Vth / / cm " ²

Where Go = Eox / Tox

Eox: dielectric constant of the insulating layer 4, q: electron charges on the carrier.

On the other hand, the resistance R (X) is in the channel between the end of region 2 and point X.

dβ (x) = P

where ^ "(X) is the specific surface resistance of the

Channel and u the mobility of the charge carriers.

This results in:

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dX

Co u

The channel current is I correspondingly
I dß (X) = dV (X)

^dX

wu Co £ V _Q (X) - v (x; - vtK7

If V _& (X) - V (X) = V _Q0 * constant (2)

assuming and equation 1 from χ = 0 to χ - L (channel length) is integrated, the following results:

Γ Yo

/ v _G (x) - v (x) - vtj / dv (x) = ι o '

This means I «ß (V ^ ₀ - Vth) V (3)

where V «V (L) _t ß -

Finally, it should be noted that equation (3) represents a linear function for condition (2) . When the potentials of the source regions 2 and drain regions 3 Vg + Vqq and dae potential at the second gate Elektrod · 9 PY ₅ + V ^ _0, as shown in Fig. 1, the equation 3 may be fulfilled will.

This means that a first linear equation (I ■ IiV) is obtained in the channel between source region 2 and drain region 3 and the channel resistance fi (X) represents a linear line. The resistance or impedance can only be controlled by the gate voltage Vqq. With this arrangement 10, a variable impedance circuit can be easily realized.

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As shown in Fig. 5, the drain electrode is provided with a Terminal connected, which is also connected to the second gate electrode 9 is connected via an inner or outer capacitor G. Furthermore, the source electrode is connected to a terminal, the further to the first gate electrode 8 via an inner or outer capacitor Cp is connected. A control connection is connected to the first gate electrode 8 to which a control signal is applied. In such a case, if desired, a gate counter voltage to be applied to the substrate 1. In the case of a P-channel enrichment type, a positive gate counter voltage applied, and a control voltage is negative.

An input signal of the frequency f * , the control signal V ^ q of the frequency fg »the capacitance C-, the capacitance C ^ and the resistance Rc between the first and the second gate electrode (resistance of the layer 5) are each determined, with

Where fp is normal direct current or low frequency

> 7

are also determined.

Then the ßeaktanten of the capacitors

and Cp small with respect to the input signal f ₁ , with respect to the

f ~ large. The gate potentials

Signal V ^ q with the frequency f ~ large

the first and second gate electrodes are Vg +

respectively.

GO.

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! According to equation (3), a linear impedance is therefore obtained between the source region and the drain region, which can be set by the control signal V ^ ₀ at the electrode 8. The circuit shown in Fig. 3 is very simple and is therefore suitable for arrangements for automatic gain control, since the required condition f ^ £> f _{2 can} be met therein.

A field effect transistor of the type shown in FIG. 1 and a circuit according to FIG. 3 are very suitable for the low-frequency Range, but not for most applications in the high-frequency range. Namely, it becomes a high frequency amplifier built up, the capacitance acts between the second gate electrode 9 and the drain region 3 or the drain electrode 7 harmful, and there is a leakage current. The channel resistance (impedance) cannot therefore be used at high frequencies can easily be controlled only by the gate voltage V ^ q. Further the change range for the resistance becomes smaller. In addition, with regard to the electrode 9, the surfaces of the Drain area 3 must necessarily be relatively large, and the junction capacitance between the substrate 1 and the drain area 3 cannot be neglected in the high-frequency range.

These difficulties are avoided by the invention; a corresponding transistor arrangement is shown in FIG. 2 and has only one gate electrode. In FIG. 2, a substrate 11 of the N (P) conductivity type is provided on one surface with a P + (N +) source region 12 and a P + (H +) drain region 13, both regions being at a distance L from one another. _{An insulating layer 14- (SiO 2} ), under which a channel is formed, is formed on the surface of the substrate 11 between the soarce region 12 and the drain region 13. Furthermore, a resistance layer 15 is preferably formed from polycrystalline silicon on the insulating layer 14. A single gate electrode 16 is over the source region 12 and over a thicker part 17 of the insulating

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Renden layer 14 is provided. The distance a to that of the drain region 13 facing edge of the source region 12 represents a preferred value.

The source and drain electrodes 18 and 19 are shown in FIG illustrated manner provided. In the embodiment shown, the resistivity of the substrate is 11

f «50 ohm cm (ie lightly doped), and the impurity concentration of the source and drain regions are 10 atoms / cm (ie highly doped). The length of the channel L is 10 microns, the values S ₁ , D ₁ are 42.5, respectively. 20 microns. The thickness Tox of the insulating layer 14 is approx. 1000 Angstrom units. However, the thickness in the area 17 at the source area is approx. 1.2 microns. The value a is approximately 2.5 microns. The resistor se not 15 consists of polycrystalline silicon, its thickness is approximately 1 micron. The specific surface resistance is 10 k ohm to 30 G ohm.

According to the invention, a gate control voltage V ^ q is applied as a constant value to the entire channel 21 with a single gate electrode. This means that with an input signal with a high frequency f ^ between the source region and drain region and a control signal with a voltage VnQ of low frequency fp (where f ^ ^ f ~) the voltage at the drain edge of the resistance layer 15 den Has the value V ^ + V ^ ₀ , since the drain voltage Vp of the layer 15 is added via the internal capacitance between the channel 21 and the layer 15. On the other hand, the voltage Vg + V ™ is applied to the gate electrode 16, so that the potential relationships correspond to those of the arrangement according to FIG. The potential difference in channel 21 between the source area and drain area is then constant, so that the conditions for good linearity are met (see equation (2)).

4 shows a circuit for operating an arrangement according to FIG. 2, in which the source electrode 18 is grounded (Vg «= 0) and only a gate voltage V ^ ₀ is applied to the gate electrode 16.

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The capacitor C- between the gate electrode and the channel corresponds an internal or an external (parasitic) capacitance.

A transistor arrangement according to the invention, as shown in FIG. 1, leads to certain advantages. Only the distance a has to be set to a predetermined value during manufacture, which is in a range a £> O. Production is therefore very simple. · D ^, is smaller than the corresponding value according to FIG. 1, since no gate electrode 9 is present. This means that the junction capacitance between the drain region and the substrate is smaller. One of the features of the invention is shown in the fact that S. is larger than D-. Due to the thicker and more extensive part 17 of the insulating layer 14, the gate electrode is free from the input signal, in particular with regard to the configuration of the source region. Finally, the length L of the channel can be smaller than in the case of the arrangement shown in FIG. 1. This means that a field effect transistor arrangement according to the invention is better suited for use in the high-frequency range. In fact, a few 100 MHz are achieved with good linearity.

The same results as those described are achieved if the gate electrode 16 is not above the source region 12, but instead is arranged above the drain region 19.

Patent claims :

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Claims (6)

Claims Field effect transistor arrangement with a semiconductor substrate, in one surface of which a source region and a Drain area and an insulating layer running between these are provided, on which a resistance layer is arranged and under which a channel is formed, characterized in that one with the Resistance layer (15) in contacting gate electrode (16) is provided, which is arranged only over a partial area of one of said areas (12, 13). j 2. Transistor arrangement according to claim 1, characterized in that that the G-ate electrode (16) over the source area (12) is arranged. 3. Transistor arrangement according to claim 1 or 2, characterized in that that the insulating layer (14) at least over the source region (12) or the drain region (13) e-. Has a thickening (17). 4. transistor arrangement according to claim 3 »characterized that the gate electrode (16) is arranged over the thickening (17). 5- transistor arrangement according to one of the preceding claims, characterized in that a polycrystalline resistance layer (15) is provided which extends over part of the source region (12) and the drain region (13) extends. 6. Transistor arrangement according to one of the preceding claims, characterized in that the drain region (13) facing edge of the gate electrode (16) arranged above the source region (12) in the direction of the drain region (13) to the source region (12) a distance (a) from the edge of the source region facing the drain region (13) TÜWT T7Ö9T4 Reichs (12) has. Patent attorney TtTa Ö1 Τ7ΊΓ9ΤΤ Blank page